EP1483682A2 - Reconfigurable processor - Google Patents
Reconfigurable processorInfo
- Publication number
- EP1483682A2 EP1483682A2 EP03706240A EP03706240A EP1483682A2 EP 1483682 A2 EP1483682 A2 EP 1483682A2 EP 03706240 A EP03706240 A EP 03706240A EP 03706240 A EP03706240 A EP 03706240A EP 1483682 A2 EP1483682 A2 EP 1483682A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- register
- configuration
- data
- ciw
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
Definitions
- the present invention relates to the preamble and thus deals with reconfigurable multidimensional logic fields and their operation.
- Reconfigurable elements are designed differently and according to the application, depending on the application to be executed.
- a reconfigurable architecture is understood to mean modules (VPU) with configurable function and / or networking, in particular integrated modules with a plurality of arithmetic and / or logical and / or logical and / or analog and / or storing and / or in one or more dimensions - External / externally networking modules that are connected to each other directly or by a bus system.
- the category of these modules includes, in particular, systolic arrays, neural networks, multiprocessor systems, processors with several arithmetic units and / or logical cells and / or communicative / peripheral cells (10), networking and network modules such as crossbar switches, as well as known modules of the Genus FPGA, DPGA, Chameleon, VPUTER, etc.
- the above architecture is used as an example for clarification and is referred to below as the VPU.
- the architecture consists of any arithmetic, logical (also memory) and / or memory cells and / or network cells and / or communicative / peripheral (10) cells (PAEs), which can be arranged in a one- or multi-dimensional matrix (PA), whereby the matrix different, any can have configured cells; the bus systems are also understood as cells.
- a configuration unit (CT, loading logic) is assigned to the matrix as a whole or in part, which configures the networking and function of the PA.
- the CT can e.g. B. as a dedicated unit.
- PACT05, PACT10, PACT17 be configured or assigned to the PA as a host microprocessor according to P 44 16 881.0-53, DE 102 06 856.9 or implemented with or by such.
- the invention describes a processor model for reconfigurable architectures, which is essentially based on the model of a classic processor.
- the classic model is first considered. We do not consider resources external to the processor (e.g. main memory for program and data, etc.).
- a processor executes a program in a process.
- the program consists of a finite set of commands (this set may contain multiple elements) and information about the order in which commands can follow one another. This order is primarily determined by the linear arrangement of the instructions in the program memory and the destinations of jump instructions.
- Figure 1 (a) shows a program in VAX assembler for exponentiation.
- a program can also be regarded as a directed graph, where the commands form the nodes and the order is modeled as edges of the graph.
- This graph is shown in Figure 1 (b).
- the graph has a unique start and a unique end node. (Not shown in the picture, indicated by the arrows.)
- the edges can also be marked with transition probabilities. This information can then be used to predict the jump.
- the jump prediction can in turn be used to preload configurations into the memory of the CT of a VPU (cf. patent application PACT10, which is fully integrated for disclosure purposes) and / or to preload configurations into the configuration stack of a PAE (according to patent applications PACT13, PACT17, PACT31, the are fully incorporated for disclosure purposes).
- the object of the invention is to provide something new for commercial use.
- the exemplary VPU architecture is a reconfigurable processor architecture that is essentially based on the patent (s) (or Registrations PACT01, 02, 03, 04, 05, 07, 08, 09, 10, 13, 17, 22, 23, 24, 31 is defined. As mentioned above, these writings are fully incorporated for disclosure purposes. Reference is also made to PACT11, 20, 27, in which corresponding high-level language compilers are described, and to PACT 21, in which a corresponding debugger is described. These writings are also fully incorporated for disclosure purposes.
- the classic command is replaced by a configuration in the familiar sense, hereinafter referred to as complex instruction (complex instruction word, CIW).
- complex instruction word, CIW complex instruction word
- the edges of the graphs in Figure 1 (b) are realized by trigger signals to the CT.
- a complete program can thus be implemented in that after the processing of a CIW, the CT and / or the configuration cache of the PAEs (see PACT31 and / or as described below) loads the following CIW.
- VPU Since the VPU essentially works on data streams, a register must be able to store a data stream or parts thereof.
- a register must be allocated and released. It must remain occupied as long as the program is running on the VPU. (HW support for resource management of the operating system.)
- a configuration (CIW) is removed from the array the moment it requests the next CIW via a trigger to the CT.
- the Reconfig trigger (see PACT08) can either be generated via the Reconfig port of an ALU-PAE or implicitly by the CT. In optimally designed versions, this should always be done from the CT.
- a CIW on the VPU preferably runs without interruption until it requests the next CIW via a trigger to the CT. It will not end prematurely.
- the maximum execution time of a CIW is limited. This demands the second property of a command. It is preferably the task of the compiler to ensure that each CIW generated meets this condition. A CIW that violates this condition is an invalid command. It can be z. B. via a watchdog timer that generates a trigger after a certain time, as it were, as a warning signal.
- the warning signal is preferably managed as a TRAP by the hardware and / or the operating system.
- the signal is also preferably sent to the CT.
- a Reconfig trigger which causes the reset-like deletion of all configurations in the PA, and / or also preferably sends an exception to the operating system.
- a subroutine in the graph display is a subgraph of a program with clearly defined input nodes.
- the edge of the subroutine call within the graph is thus known statically. However, the leading edge at the output node of the subroutine is not known statically. This is illustrated in FIG. 2.
- the edges from the main program (0201/0202) to the subroutine (0205) are present, but the continuation (0206) after the subroutine is not known to subroutine 0205.
- the respective continuation is permanently linked to the subroutine call (marked by dashed or dotted lines). It must be inserted into the graph in a suitable manner before reaching the input node (0207, 0208). This is illustrated in Figure 3. In classic processors, this usually happens when the subroutine call (Call, 0203, 0204) stores the address of the command following the subroutine (this is exactly the missing edge) on a call stack. From there it can be fetched at the return.
- a stack PAE is required to be transferred to the VPU. Like the register PAEs, this is a process resource and is managed in the same way.
- the CIW which causes the subroutine call to terminate, configures the return edge on the stack PAE. With a trigger, the last CIW of the subroutine causes the stack PAE to remove the uppermost entry from the stack and to send it to the CT as a reconfiguration call.
- a solution within the CT is implemented within the CT in software or as a dedicated hardware unit.
- a special Config-ID e.g. -1 can be reserved as a return. When the CT receives this ID, it replaces it with the top entry of its locally managed stack.
- a stack PAE which can be constructed, for example, as a modified RAM PAE according to PACT13 Fig. 21.
- Stack overflow and stack underflow are exceptions that are preferably passed on to the operating system.
- a classic processor register contains a data word at all times.
- a command can read, write or change the register content (Read-Modify-Write).
- a VPU register will now have the same properties, however, according to the invention, it contains a value vector or parts thereof instead of a single value. It is possible and usually preferred that the organization of a VPU register be done as a kind of FIFO. In certain cases, random access may also be required. The three register accesses mentioned above are explained in detail below. Random access is not considered here.
- the register When a CIW is started, the register contains a data vector of unknown length. The individual elements of the vector are extracted sequentially. A trigger is generated for the last element of the vector, which indicates that the register is now empty and the CIW can terminate.
- the state of the register can be characterized with 3 pointers, they point to the first (0403), last (0401) and current (0402) entry in the data vector. The position of the pointers at the beginning of a CIW is shown by way of example in FIG. 4 (a). The pointer for the current entry stands on the first entry.
- Figure 4 (b) shows in an example what the pointer position of a register at the end of a CIW can look like. In the case shown there, the vector was not read completely.
- the register is emptied. All data not processed will be deleted.
- the pointer for the current entry is set to the last entry.
- the register is reset to its original state. This enables the next CIW to access the full data vector again.
- the pointer for the current entry is reset to the first entry.
- the third possibility is particularly interesting if a CIW cannot process the data vector completely due to the maximum execution time for a CIW. See also section 7.
- FIG. 5 (a) shows a register prior to a write access that still contains data. It is suggested that existing data can NEN are deleted so that write access begins with an empty vector ( Figure 5 (b)). Alternatively, the written data can also be attached to the existing content. This is shown in Figure 5 (c). This is interesting if the previous CIW could not generate the complete vector due to the maximum execution time.
- Separation line between read and write data happens. This can either remain where it is. This is useful when a CIW has to be terminated due to the time limit. Alternatively, the dividing line is placed at the end of all data.
- Figure 6 shows the operation using an example.
- 0601 marks the virtual dividing line.
- the register contains data (a), which are read in part (b) or in full (c) below. Newly written and read entries are identified by different hatching.
- the drawing files (d) and (e) show the state of the register after the necessary pointer update, which changes the position of the dividing lines. This is not an explicit step, but is only shown here for clarification. The read entries must be removed immediately to make room for the new entries to be written.
- a process that is a program that also shares resources with other programs, particularly in a multitasking operation, must allocate each required register before it can use it. This is preferably done via an additional configuration register within the RAM and / or register PAE. The process to which the register now belongs is also entered there. This configuration is retained even after reconfigurations. The register must be explicitly released by the CT. This happens, for example, when a process ends. With the configuration of each CIWs must be informed of the registers to which process the CIW belongs. This enables switching between several register sets. The procedure is described in more detail in Section 6 below.
- interrupts there are the hardware interrupts, where the processor has to react to an external event. These are usually processed by the operating system and are not visible to the running processes. They should not be dealt with further here.
- the second type is software interrupts. These are often used to implement asynchronous interactions between the process and the operating system. So it is z. B. under VMS possible to send a read request to the operating system without waiting for the actual data. As soon as the data is available, the operating system interrupts the running program and asynchronously calls a procedure of the program. This process is called the Asynchronous System Trap (AST).
- AST Asynchronous System Trap
- This procedure can be used in the same way on the VPU. Support for this can be provided in the CT.
- the CT knows whether an asynchronous routine has to be called for a process. In this case, the next request that comes from the array is not processed directly, but saved.
- the optimal number of register sets can be determined depending on the average execution time of a CIW and the average loading and decoding times of the CIWs.
- Latency can be intercepted by a larger number of register sets. It is important for the function of the method that the average CIW runtime is greater than the time actually required to load or decode the CIW.
- the corresponding registers of the different register sets are on the same for the programmer PAE address. This means that only the registers of one register set can be used at any time.
- the context change between the register sets can be realized by transferring the corresponding context to the PAEs before each CIW.
- the context switch can be done automatically in detail by the PUSH / POP operations according to PACT11 and / or by special RAM / register PAE hardware as shown in PACT13 Fig. 21. In both cases there is a similar stack structure in the memory.
- Each stack entry stores the data of a process.
- a stack entry comprises the complete content of all registers, in other words all memory cells of all memories which serve as registers for a process.
- a stack entry can also contain internal PA data and states.
- the for loop has a maximum runtime that can be determined by the compiler. It can therefore be mapped to a CIW. MAX is determined by the compiler depending on the maximum runtime and the individual runtimes of the instructions.
- the resulting CIW has two starting edges.
- the exit via the goto leads to the next CIW, the exit via the regular end of the for forms an edge on itself.
- the endless loop is implemented above this.
- debugging takes place on an instruction basis, ie the execution of a program can be interrupted at any time between two instructions. At these breakpoints, the programmer has access to the registers. He can view and modify them. Breakpoints can be implemented in different ways.
- the program can be modified, ie the command to stop before is replaced by other commands that call the debugger. In the graph model, this corresponds to the replacement of a node by another node or a subgraph. Another method is based on additional hardware support. The processor is informed of the command at which the program is interrupted. that should. The corresponding command is usually identified by its address.
- a debugger can replace a CIW with another CIW.
- This CIW can e.g. B. copy the register contents into the main memory, where they can either be analyzed with an external VPÜ debugger.
- the debugger can also run on the VPU.
- Hardware support can also be provided in the CT, which identifies CIWs on the basis of their ID request and then calls the debugger.
- an interruption can also be made to an edge of the graph, since this is explicitly available in contrast to classic program code.
- the programmer is able to define the CIWs, which form a kind of "processor instructions". Accordingly, the ones so defined could be in themselves
- Microcode debugging is designed so that the programmer has access to all internal registers and data paths of the processor; it it was recognized that the effort required for this can easily be justified by the increased functionality.
- the data and states are via bus interface, memory and / or preferably via debug interface such as Transfer JTAG to the debugger.
- a PACT21 debugger is preferably used, which preferably contains a mixed-mode debugger with an integrated simulator for processing the micro-debugging.
- the debugger can also be called when an exception occurs within a command. For this it makes sense that the registers can be reset to the state before the start of the command and otherwise no side effects have occurred. Then the command in question can be started in the software simulator and simulated until the exception occurs.
- Microcode debugging can preferably be implemented by configuring a debug CIW after or during the processing of a CIW, which initially receives all states (eg in the PAEs) and then saves them in an external memory by means of a suitable configuration of the networking resources. rather writes.
- the PUSH / POP methods described in PACT11 can be used with particular preference. This can preferably be done via an industry standard interface, such as JTAG.
- a debugger can then take over the data from the memory or via the JTAG interface and, if necessary, further simulate it in conjunction with a simulator (cf. PACT21), which enables microcode debugging.
- Each PAE receives its own local cache for this. This saves the configuration data of different configurations for exactly this PAE. The fact that a PAE has not received any data from a configuration is also saved. For each requested configuration, the cache can make one of the following statements:
- the configuration data are available in the cache.
- a PAE does not have the configuration data, this must be reported back to the FILMO. In the simplest case, this is done via a reject on the existing line. Based on this signal, the FILMO then knows that at least one PAE of the PAC is missing the configuration data. He can then transfer the complete data. Alternatively, each PAE can trigger a request for the data separately. A suitable compromise must be found here between the number of requests and the amount of configuration data to be transferred. Small PAC sizes are also advantageous due to the lower latency on the configuration bus.
- a cache always consists of two parts.
- One part contains the actual data (here the configuration words, 0902), the other part contains administrative information (here the contained configuration numbers and their age, 0901)
- FIG. 7 shows an example of a modified FIFO stage for this purpose.
- the hatched modules are in addition to a normal FIFO stage according to the prior art.
- the entries in this FIFO contain additional information in addition to the configuration number. This is either a pointer (address) to the configuration data or one of the two options "no data required" (e.g. coded as 0) or "data must be requested” (e.g. -1).
- the interconnection of several stages is shown in Figure 8.
- the read chain is initialized with the required configuration number and the status -1. This value remains unchanged at the output of the read chain if the configuration number is not stored in the FIFO. This means that the output of the read chain can always be used to write the configuration number to the FIFO.
- the signal ack_in is activated when the FIFO is full and the searched configuration number is not in the FIFO.
- the actual data storage is organized as a linked list due to the different number of configuration words per configuration. Other implementations are possible. A chained The list can be implemented as RAM simply by storing the address of the subsequent data word in addition to the data.
- FIG. 9 shows a possible cache content during operation. Free entries in the data memory are highlighted in white, hatched by a configuration. Configurations do not have to be on consecutive addresses. Configuration 18 has no configuration data, which is why no pointer leads to the data memory.
- a new configuration is written to the free list in the data memory.
- the pointer information of the data memory is not modified.
- the pointer information is only changed for the last data word in a configuration to indicate that the list is now changing here.
- the pointer to the free list is set to the next entry.
- the oldest configuration is to be removed, it is taken from the FIFO.
- the pointer of the last entry in the free list is set to the value taken from the FIFO. From this address, you can continue to configure as usual.
- Figure 10 shows this using an example.
- the configuration with the number 7 is to be reconfigured.
- the free list has been completely occupied in FIG. (A). It is decided to remove the oldest configuration (No. 5) from the cache and continue to write configuration No. 7 to the cache.
- the pointer at the end of the free list is converted to the start of the former configuration 5. This extends the free list again and there is space for new configuration words.
- the memory parts involved in this step are hatched in diagonal fashion in FIG. (B). With a suitable division of the memory, this can be done in one cycle.
- the corresponding pointer is set to the end and the free pointer to the next entry. Space in the data memory is not only freed up again if this is required due to the inclusion of a new configuration. Even if the administrative memory is full and an entry is therefore removed from the administrative memory, the free list in the data memory must be adapted. To do this, either the pointer at the end of the
- an additional pointer to the respective end of a configuration is stored in the management memory. Now the modification is easy.
- the free pointer receives the start address of the old configuration, and the pointer at the last configuration word in the data memory is set to the free pointer.
- the buses are explicitly determined by the router. This can result in two configurations overlapping on a bus and therefore not being able to run simultaneously, even though there are enough buses available overall.
- buses can be mixed mixed. Two short non-overlapping buses, which have been configured for different bus numbers due to previous occupancy, can be switched to the same bus number when resources are freed up. This creates space for future longer connections.
Abstract
Description
Claims
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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DE10202044 | 2002-01-19 | ||
DE10202044 | 2002-01-19 | ||
DE10202175 | 2002-01-20 | ||
DE10202175 | 2002-01-20 | ||
PCT/DE2003/000152 WO2003060747A2 (en) | 2002-01-19 | 2003-01-20 | Reconfigurable processor |
Publications (1)
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EP1483682A2 true EP1483682A2 (en) | 2004-12-08 |
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EP03706240A Withdrawn EP1483682A2 (en) | 2002-01-19 | 2003-01-20 | Reconfigurable processor |
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US (1) | US8281108B2 (en) |
EP (1) | EP1483682A2 (en) |
AU (1) | AU2003208266A1 (en) |
DE (1) | DE10392560D2 (en) |
WO (1) | WO2003060747A2 (en) |
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- 2003-01-20 US US10/501,845 patent/US8281108B2/en not_active Expired - Lifetime
- 2003-01-20 EP EP03706240A patent/EP1483682A2/en not_active Withdrawn
- 2003-01-20 WO PCT/DE2003/000152 patent/WO2003060747A2/en not_active Application Discontinuation
- 2003-01-20 DE DE10392560T patent/DE10392560D2/en not_active Expired - Fee Related
Non-Patent Citations (1)
Title |
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See references of WO03060747A2 * |
Also Published As
Publication number | Publication date |
---|---|
AU2003208266A8 (en) | 2003-07-30 |
US8281108B2 (en) | 2012-10-02 |
WO2003060747A2 (en) | 2003-07-24 |
US20060090062A1 (en) | 2006-04-27 |
DE10392560D2 (en) | 2005-05-12 |
WO2003060747A3 (en) | 2004-03-04 |
AU2003208266A1 (en) | 2003-07-30 |
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