WO2002103807A1 - Lateral junction type field effect transistor - Google Patents

Lateral junction type field effect transistor Download PDF

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Publication number
WO2002103807A1
WO2002103807A1 PCT/JP2002/005816 JP0205816W WO02103807A1 WO 2002103807 A1 WO2002103807 A1 WO 2002103807A1 JP 0205816 W JP0205816 W JP 0205816W WO 02103807 A1 WO02103807 A1 WO 02103807A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor layer
layer
impurity
region
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2002/005816
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English (en)
French (fr)
Japanese (ja)
Inventor
Shin Harada
Kenichi Hirotsu
Hiroyuki Matsunami
Tsunenobu Kimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to US10/362,345 priority Critical patent/US7023033B2/en
Priority to KR10-2003-7002084A priority patent/KR100467421B1/ko
Priority to EP02736054.4A priority patent/EP1396890B1/en
Priority to CA2420821A priority patent/CA2420821C/en
Publication of WO2002103807A1 publication Critical patent/WO2002103807A1/ja
Anticipated expiration legal-status Critical
Priority to US11/337,143 priority patent/US7528426B2/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Definitions

  • the present invention relates to a lateral junction field-effect transistor, and more particularly, to a structure of a lateral junction field-effect transistor capable of reducing on-resistance while maintaining good withstand voltage performance.
  • JFET Joint Field Effect
  • Transistor is to apply a reverse bias voltage from the gate electrode to the pn junction provided on the side of the channel region through which the carrier passes, thereby expanding the depletion layer from the pn junction to the channel region, Controls the conductance of the area and performs operations such as switching.
  • the horizontal J FET refers to one in which carriers move parallel to the element surface in the channel region.
  • the carrier of the channel may be an electron (n-type) or a hole (p-type), but usually, in a JFET using SiC for the semiconductor substrate, the channel region is often an n-type impurity region.
  • the carrier of the channel is an electron, and thus the channel region is an n-type impurity region.
  • the channel region may be a p-type impurity region.
  • Figure 7 is a sectional view showing a conventional lateral JFET (U.S. Patent Registration No. 5, 264, 713 Junction Field- Effect Transistor Formed in Silicon Carbide) 0 p -type S i C substrate 1 1 0 p + -type on An epitaxial layer 112 is arranged thereon, and an n-type channel layer 114 is formed thereon. Above the channel layer 114, an n-type source region 116 is placed on one side, and an n-type drain region 118 is placed on the other side, sandwiching the trench 124. A source electrode 120 and a drain electrode 122 are arranged at the center.
  • JFET U.S. Patent Registration No. 5, 264, 713 Junction Field- Effect Transistor Formed in Silicon Carbide
  • a gate contact layer 130 is formed on the back surface of the SiC substrate 110, and a gate electrode (not shown) is provided thereon. Depth through source / drain regions 1 16, 1 18 and into channel layer 1 14 A trench is provided in the second conductive type epitaxial layer 114 between the bottom of the trench 124 and the first conductive type epitaxial layer 112. Is formed.
  • the value of the concentration of the p-type impurity in the epitaxial layer 112 is higher than the value of the n-type concentration in the epitaxial layer 114 including the channel, and the depletion layer is formed by applying a reverse bias voltage to the junction. It is configured to expand toward channels. When the depletion layer blocks the channel, the current cannot pass through the channel, so that the channel is turned off. Therefore, it is possible to control whether the depletion layer blocks the channel region by adjusting the magnitude of the reverse bias voltage. As a result, for example, by adjusting the reverse bias voltage between the gate and the source, it is possible to perform the on / off control of the current.
  • FIG. 8 is a cross-sectional view illustrating a channel, a source, a drain, and a gate for explaining the withstand voltage performance of the lateral JFET.
  • FIG. 9 is a cross-sectional view illustrating the electric field distribution between the drain / gate at the time of a breakdown voltage.
  • the electric field distribution shown in Fig. 9 is the electric field distribution in the n-type epitaxial layer from the p-type epitaxial layer to the drain electrode.
  • Emax represents the breakdown electric field when the distance W from the drain to the pn junction is the depletion layer. This Emax can be expressed as in the following equation (1).
  • q is the elementary charge
  • Nd is the distance from the drain electrode to the pn junction.
  • ⁇ s is the dielectric constant of the semiconductor.
  • the breakdown voltage Vb that is, the breakdown voltage is given by the following equations (2) to (4).
  • Vdgmax is the maximum voltage that can be applied between the drain and the gate
  • Vgs is the gate-source voltage required to turn off.
  • Vb Vdgmax- Vgs (2)
  • Vdgmax q NdW2 / (2 ⁇ s) (3)
  • Vgs qNdh2 / (2 ⁇ s) (4)
  • Vgs is larger than in equation (4), and Vb is smaller than in equation (2). That is, the withstand voltage performance is degraded.
  • An object of the present invention is to provide a lateral JFET having a structure capable of further reducing on-resistance while maintaining high withstand voltage performance.
  • a gate region layer containing a first conductivity type impurity concentration higher than the material concentration instead of the electric field distribution normally seen at the junction (PN junction) between the first conductivity type impurity and the second conductivity type impurity, the electric field distribution of an equal electric field close to a parallel plate type capacitor Will be realized. As a result, it is possible to reduce the on-resistance while maintaining the withstand voltage, as compared with the conventional structure of the lateral JFET.
  • the second semiconductor layer and the third semiconductor layer have substantially the same impurity concentration.
  • a first semiconductor layer containing a first conductivity type impurity located on a semiconductor substrate and a first semiconductor layer located on the first semiconductor layer are provided.
  • the impurity concentration being higher than the impurity concentration of the second semiconductor layer.
  • the distance between the uppermost portion of the first semiconductor layer and the lowermost portion of the gate region layer is increased by a diffusion potential at a junction between the second semiconductor layer and the gate region layer. It is characterized in that it is smaller than the interval between layers.
  • the second semiconductor layer sandwiched between the first semiconductor layer and the gate region layer has an impurity concentration substantially the same as that of the gut region layer and has the same potential.
  • An area is provided.
  • the distance between the uppermost part of the impurity-implanted region and the lowermost part of the gate region layer is a diffusion potential at a junction between the second semiconductor layer and the gate region layer.
  • the distance between the lowermost part of the impurity-implanted region and the uppermost part of the first semiconductor layer is smaller than twice the distance between the expanding depletion layers, and the diffusion at the junction between the second semiconductor layer and the impurity-implanted region. It is smaller than the space between the depletion layers that spreads with the potential.
  • the channel resistance can be more effectively reduced, and the on-resistance can be further reduced.
  • a distance between an uppermost portion of the impurity injection region closest to the gate region layer and a lowermost portion of the gate region layer is set such that the distance between the second semiconductor layer and the gate region is smaller.
  • the spacing between the impurity-implanted regions is smaller than twice the distance between the depletion layers at the junction with the layer and the depletion layer at the junction between the second semiconductor layer and the gate region.
  • the distance between the lowermost part of the impurity injection region closest to the first semiconductor layer and the uppermost part of the first semiconductor layer is smaller than twice the distance between the layers, and the distance between the second semiconductor layer and the impurity It is smaller than the space between the depletion layers that spreads due to the diffusion potential at the junction with the implantation region.
  • a lower surface is provided so as to have a region extending to the first semiconductor layer and a region extending to the second semiconductor layer, and the lower surface has a concentration higher than an impurity concentration of the second semiconductor layer. And a gut region layer containing an impurity concentration of one conductivity type.
  • the thickness of the second semiconductor layer and the thickness of the third semiconductor layer are substantially the same, and the impurity concentration of the third semiconductor layer is the same as that of the second semiconductor layer. It is provided at a concentration approximately half of the impurity concentration.
  • the thickness of the third semiconductor layer is approximately half of the thickness of the second conductor layer, and the impurity concentration of the third semiconductor layer and the impurity concentration of the second semiconductor layer are different. And concentration are provided almost identically.
  • the third semiconductor layer located between the gate region layer and the drain region layer and the second semiconductor layer in a range where the third semiconductor layer is in contact with the third semiconductor layer are all required. Can be filled by the depletion layer. As a result, a horizontal JFET having a large withstand voltage can be easily obtained without increasing the thickness of the second semiconductor layer or increasing the resistance.
  • the third semiconductor layer Each of the gate region layer, the second semiconductor layer, and the third semiconductor layer is depleted so that the entire second semiconductor layer in the area in contact with the third semiconductor layer can be deplete
  • FIG. 1 is a schematic diagram for explaining the operation principle of the horizontal J FET based on the present invention.
  • FIG. 3 is a cross-sectional view showing a structure of a horizontal JFET in Example 2 based on the present invention.
  • FIG. 4 is a cross-sectional view illustrating a structure of a horizontal JFET in Example 3 based on the present invention.
  • FIG. 5 is a cross-sectional view showing the structure of a horizontal JFET in Example 4 based on the present invention.
  • FIG. 6 is a cross-sectional view showing the structure of the horizontal JFET in Example 5 based on the present invention.
  • FIG. 7 is a cross-sectional view showing the structure of a horizontal J F.ET according to the related art.
  • FIG. 8 is a schematic diagram for evaluating the withstand voltage of the horizontal J FET in the conventional technology.
  • FIG. 9 is a diagram showing the relationship between the maximum voltage g max that can be applied between the source Z drain and the channel impurity concentration.
  • FIG. 10 is a diagram showing the relationship between the maximum current Vdgmax that can be applied between the drain and the gate and the impurity concentration of the channel layer.
  • FIG. 1 is a schematic diagram for conceptually explaining the operation principle of the present invention.
  • FIG. 1 illustrates the electric field distribution between the gate region and the drain region, the electric field distribution between the gate region and the source region can be similarly considered.
  • the basic structure of a lateral JFET based on the present invention is composed of an n-type semiconductor layer 3 composed of an n-type impurity region and a p-type impurity region on the n-type semiconductor layer 3! ) Type semiconductor layer 8. Furthermore, this: extends into the n-type semiconductor layer 3 in the p-type semiconductor layer 8 and has a concentration higher than the impurity concentration of the n-type semiconductor layer 3!
  • Type impurity concentration Including a p + -type gate region layer 7, and an n-type impurity concentration higher than the impurity concentration of the n-type semiconductor layer 3, which is located at a predetermined distance from the p + -type gate region layer 7. And an n + -type drain region layer 9.
  • the Poisson equation of the ⁇ -type semiconductor layer 3 can be expressed as the following equation (5).
  • a SiC single crystal substrate is used regardless of the conductivity type.
  • a P-type epitaxial layer 2 as a first semiconductor layer containing an impurity of the first conductivity type is provided on the SiC single crystal substrate 1.
  • an n-type epitaxial layer 3 is provided as a second semiconductor layer containing a second conductive type impurity having a higher impurity concentration than the P-type epitaxial layer 2. It has been done.
  • this n-type epitaxial layer 3 there is a p-type epitaxial layer as a third semiconductor layer.
  • a char layer 6 is provided.
  • n + -type source containing n-type Epitakishi catcher Le layer 3 impurity of a second conductivity type concentration higher than the impurity concentration of the A region layer 5 and an n + type drain region layer 9 are provided. Also, between the source region layer 5 and the drain region layer 9, the first conductive layer having a concentration higher than the impurity concentration of the n-type epitaxial layer 3 is formed so that the lower surface extends into the n-type epitaxial layer 3.
  • a p + -type gate region layer 7 containing a type impurity is provided.
  • n + type source region layer 5 On the surfaces of the n + type source region layer 5, the n + type drain region layer 9, and the p + type gate region layer 7, a source electrode 10, a gate electrode 11, and a drain electrode 12 are provided, respectively. I have. Note that a p + type semiconductor layer 4 reaching the p ⁇ type epitaxial layer 2 is formed beside the source region layer 5.
  • the thickness of the n-type epitaxial layer 3 is 1. ⁇
  • the thickness (d) of the source region layer 5 and the drain region layer 9 is 0. 5 / m
  • the impurity concentration of the p-type epitaxial layer 6 and the impurity concentration of the n-type epitaxial layer 3 are equal to 1.2 ⁇ 1017 cm— 3
  • the thickness (h) of the p-type epitaxial layer 2 is 3.0 ⁇
  • L gd is 2.2 ⁇ .
  • L gs 0 and a is 160 nm.
  • an electric field distribution of an equal electric field close to that of a parallel plate type capacitor is realized instead of the electric field distribution observed in a normal PN junction.
  • the second semiconductor layer By making the impurity concentration of the type epitaxial layer 6 equal to that of the type epitaxial layer 6, it is possible to more effectively reduce the on-resistance while maintaining the breakdown voltage.
  • Lateral J FET is in the upper Symbol Example 1, p-type Epita Kisharu layer 6 is provided on the n-type Epitakisharu layer 3, this; the type Epitakisharu layer 6, n + -type source region of The lateral JFET in this embodiment includes the layer 5, the n + type drain region layer 9, and the p + type gate region layer 7.
  • the p-type epitaxial layer 6 is formed on the n-type epitaxial layer 3.
  • the n-type epitaxial layer 3 is provided with an n + -type source region layer 5, an n + -type drain region layer 9, and a p + -type gate region layer 7.
  • Other configurations are the same as those in the first embodiment.
  • the distance between the uppermost portion of the p-type epitaxial layer 2 and the lowermost portion of the p + -type gate region layer 7 (a) Force n-type epitaxial layer 3 and .p + -type gate region It is provided so as to be smaller than the interval of the depletion layer which is expanded by the diffusion potential at the junction with the layer 7. As a result, the channel is completely pinched off at the time of the gate OV due to the depletion layer which is expanded by the diffusion potential, so that a normally-off type can be realized.
  • the lateral JFET of the present embodiment has the same basic structure as the lateral JFET of the first embodiment, and the n-type FET in a region sandwiched between the P-type epitaxial layer 2 and the p + -type gate region layer 7. It is characterized in that one impurity implanted region 17 having substantially the same impurity concentration as the p + -type gate region layer 7 and having the same potential is provided in the epitaxial layer 3.
  • the distance (al) between the uppermost portion of the impurity-implanted region 17 and the lowermost portion of the p + -type gate region layer 7 is defined by the n-type epitaxial layer 3 and the p + -type gate region layer 7.
  • the lateral JFET of the present embodiment has the same basic structure as the lateral JFET of the third embodiment, and the n-type region in the region sandwiched between the P— type epitaxial layer 2 and the p + type gate region layer 7. It is characterized in that a plurality of impurity implantation regions 17a and 17b having substantially the same impurity concentration as p + -type gate region layer 7 and having the same potential are provided in epitaxial layer 3.
  • the spacing (al) force n-type between the bottom of the impurity implantation area 17 a of the top and the p + -type gate region layer 7 that is closest to the p + -type gate region layer 7 Epitakisharu
  • the distance between the impurity implanted regions 17 a and 17 b is smaller than twice the distance between the depletion layers that expands due to the diffusion potential at the junction between the layer 3 and the p + -type gut region layer 7.
  • Example 5 With reference to FIG. 6, the structure of the lateral JFET in this embodiment will be described.
  • the structure of each of the embodiments described above in order to increase the device withstand voltage, it is necessary to lower the impurity concentration of the n-type epitaxial layer 3 and increase the thickness in the substrate depth direction. In this case, a problem occurs that the resistance value of the n-type epitaxial layer 3 rapidly increases. In addition, when the thickness of the n-type epitaxial layer 3 in the substrate depth direction is increased, a problem that it becomes difficult to control the channel thickness occurs.
  • a p-type epitaxial layer 6 A located between the ⁇ + -type gate region layer 7 A and the n + -type drain region layer 9, The p + -type gate region layer 7A, the n-type epitaxial layer 3A, and the p-type gate layer 3A, so that the entire n-type epitaxial layer 3A in the area where the epitaxial layer 6A contacts The impurity concentration of the type epitaxial layer 6A and the thickness in the substrate depth direction are selected.
  • the p + -type gate region layer 7A is formed along the direction in which the p + -type gate region layer 7A extends (the X direction of the substrate (see FIG. 1)). It has a region 7L provided so as to reach the epitaxial layer 2 and a region 7H provided so as to reach the n-type epitaxial layer 3A.
  • the horizontal JFET according to the present invention it is possible to provide a horizontal JFET having a structure in which the on-resistance is further reduced while maintaining high withstand voltage performance.

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
PCT/JP2002/005816 2001-06-14 2002-06-11 Lateral junction type field effect transistor Ceased WO2002103807A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US10/362,345 US7023033B2 (en) 2001-06-14 2002-06-11 Lateral junction field-effect transistor
KR10-2003-7002084A KR100467421B1 (ko) 2001-06-14 2002-06-11 횡형접합형 전계 효과 트랜지스터
EP02736054.4A EP1396890B1 (en) 2001-06-14 2002-06-11 Lateral junction type field effect transistor
CA2420821A CA2420821C (en) 2001-06-14 2002-06-11 Lateral junction type field effect transistor
US11/337,143 US7528426B2 (en) 2001-06-14 2006-01-20 Lateral junction field-effect transistor

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2001-180173 2001-06-14
JP2001180173 2001-06-14
JP2001348882A JP3812421B2 (ja) 2001-06-14 2001-11-14 横型接合型電界効果トランジスタ
JP2001-348882 2001-11-14

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/337,143 Continuation US7528426B2 (en) 2001-06-14 2006-01-20 Lateral junction field-effect transistor

Publications (1)

Publication Number Publication Date
WO2002103807A1 true WO2002103807A1 (en) 2002-12-27

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PCT/JP2002/005816 Ceased WO2002103807A1 (en) 2001-06-14 2002-06-11 Lateral junction type field effect transistor

Country Status (8)

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US (2) US7023033B2 (enExample)
EP (1) EP1396890B1 (enExample)
JP (1) JP3812421B2 (enExample)
KR (1) KR100467421B1 (enExample)
CN (1) CN1238904C (enExample)
CA (1) CA2420821C (enExample)
TW (1) TW594987B (enExample)
WO (1) WO2002103807A1 (enExample)

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CA2420821C (en) 2011-08-09
US7528426B2 (en) 2009-05-05
EP1396890A1 (en) 2004-03-10
CN1496587A (zh) 2004-05-12
US20060118813A1 (en) 2006-06-08
US7023033B2 (en) 2006-04-04
JP3812421B2 (ja) 2006-08-23
TW594987B (en) 2004-06-21
EP1396890A4 (en) 2007-10-10
CA2420821A1 (en) 2002-12-27
KR100467421B1 (ko) 2005-01-27
CN1238904C (zh) 2006-01-25
US20030168704A1 (en) 2003-09-11
JP2003068762A (ja) 2003-03-07
EP1396890B1 (en) 2013-08-21
KR20030027025A (ko) 2003-04-03

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