JP7128136B2 - 接合型電界効果トランジスタ - Google Patents
接合型電界効果トランジスタ Download PDFInfo
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- JP7128136B2 JP7128136B2 JP2019042902A JP2019042902A JP7128136B2 JP 7128136 B2 JP7128136 B2 JP 7128136B2 JP 2019042902 A JP2019042902 A JP 2019042902A JP 2019042902 A JP2019042902 A JP 2019042902A JP 7128136 B2 JP7128136 B2 JP 7128136B2
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- 230000005669 field effect Effects 0.000 title claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 37
- 239000012535 impurity Substances 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 6
- 238000000638 solvent extraction Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 169
- 239000000758 substrate Substances 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Description
以下、第1の実施形態について説明する。
図1は、本実施形態に係る接合型電界効果トランジスタを示す平面図である。
図2(a)は図1のA-A’線による断面図であり、(b)は図1のB-B’線による断面図である。
図3は、図1のC-C’線による断面図である。
JFET1においては、ソースコンタクト31及びサリサイド層21を介して、ソース層15にソース電位が印加される。また、ドレインコンタクト32及びサリサイド層22を介して、ドレイン層16にドレイン電位が印加される。更に、ゲートコンタクト33及びサリサイド層23を介して、ゲート層17にゲート電位が印加される。ゲート電位は、ゲート層17の端部17aを介して、nウェル11にも印加される。
JFET1においては、チャネル層14のゲート幅方向Wの両端部がSTI12から離隔しているため、STI12の近傍においては、ソース・ドレイン電流51が流れない。これにより、ソース・ドレイン電流51のノイズを低減することができる。
次に、第2の実施形態について説明する。
図4は、本実施形態に係る接合型電界効果トランジスタを示す断面図である。
図4が示す断面は、第1の実施形態における図2(b)が示す断面に相当する。
図4に示すように、本実施形態に係るJFET2においては、ソース・ドレイン電流52がn-形層41及びn-形層42を迂回して流れる。このため、ソース・ドレイン電流52は、サリサイドブロック25及び26の近傍を流れることがない。これにより、サリサイドブロック25及び26の下面の凹凸、チャネル層14におけるサリサイドブロック25及び26近傍の結晶欠陥、及び、固定電荷等に起因して、ソース・ドレイン電流52にフリッカーノイズが発生することを抑制できる。この結果、本実施形態によれば、ソース・ドレイン電流52のノイズをより一層低減することができる。
本実施形態における上記以外の構成、動作及び効果は、前述の第1の実施形態と同様である。
10:半導体基板
11:nウェル(第1半導体層)
12:STI(素子分離絶縁体)
13:アクティブエリア
14:チャネル層(第2半導体層)
14a:下面
15:ソース層
16:ドレイン層
17:ゲート層
17a:端部
17b:下面
21、22、23:サリサイド層
25、26:サリサイドブロック
30:層間絶縁膜
31:ソースコンタクト
32:ドレインコンタクト
33:ゲートコンタクト
41:n-形層(第3半導体層)
41a:下面
42:n-形層(第4半導体層)
42a:下面
51、52:ソース・ドレイン電流
L:ゲート長方向
V:垂直方向
W:ゲート幅方向
Claims (5)
- 第1導電形の第1半導体層と、
前記第1半導体層の上層部分に設けられ、アクティブエリアを区画する素子分離絶縁体と、
前記アクティブエリア内における前記第1半導体層上に設けられ、第2導電形であり、第1方向の端部が前記素子分離絶縁体から離隔した第2半導体層と、
前記第2半導体層上に設けられ、前記第2導電形であり、不純物濃度が前記第2半導体層の不純物濃度よりも高いソース層と、
前記第2半導体層上に設けられ、前記ソース層から前記第1方向に対して交差した第2方向に離隔し、前記第2導電形であり、不純物濃度が前記第2半導体層の不純物濃度よりも高いドレイン層と、
前記第2半導体層上に設けられ、前記ソース層と前記ドレイン層との間に配置され、前記ソース層及び前記ドレイン層から離隔し、前記第1導電形であるゲート層と、
を備え、
前記ゲート層の前記第1方向における端部は前記第1半導体層に接している接合型電界効果トランジスタ。 - 前記ソース層、前記ドレイン層及び前記ゲート層は、前記第1方向に延びる請求項1記載の接合型電界効果トランジスタ。
- 前記ソース層、前記ドレイン層及び前記ゲート層の上面には、それぞれ、サリサイド層が形成された請求項1または2に記載の接合型電界効果トランジスタ。
- 前記第2半導体層上であって、前記ソース層と前記ゲート層との間に配置され、前記第1導電形であり、不純物濃度が前記ゲート層の不純物濃度よりも低い第3半導体層と、
前記第2半導体層上であって、前記ドレイン層と前記ゲート層との間に配置され、前記第1導電形であり、不純物濃度が前記ゲート層の不純物濃度よりも低い第4半導体層と、
をさらに備えた請求項1~3のいずれか1つに記載の接合型電界効果トランジスタ。 - 前記第3半導体層の下面は前記ゲート層の下面よりも上方に位置し、
前記第4半導体層の下面は前記ゲート層の下面よりも上方に位置する請求項4記載の接合型電界効果トランジスタ。
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JP2019042902A JP7128136B2 (ja) | 2019-03-08 | 2019-03-08 | 接合型電界効果トランジスタ |
CN201910500088.6A CN111668295B (zh) | 2019-03-08 | 2019-06-11 | 耦合型场效应晶体管 |
US16/548,739 US11121264B2 (en) | 2019-03-08 | 2019-08-22 | Junction field effect transistor |
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JP2019042902A JP7128136B2 (ja) | 2019-03-08 | 2019-03-08 | 接合型電界効果トランジスタ |
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JP2020145379A JP2020145379A (ja) | 2020-09-10 |
JP7128136B2 true JP7128136B2 (ja) | 2022-08-30 |
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US (1) | US11121264B2 (ja) |
JP (1) | JP7128136B2 (ja) |
CN (1) | CN111668295B (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008075488A1 (ja) | 2006-12-18 | 2008-06-26 | Sumitomo Electric Industries, Ltd. | 横型接合型電界効果トランジスタ |
WO2011155105A1 (ja) | 2010-06-07 | 2011-12-15 | パナソニック株式会社 | 半導体装置及びその製造方法 |
JP2012227489A (ja) | 2011-04-22 | 2012-11-15 | Panasonic Corp | 半導体装置およびその製造方法 |
Family Cites Families (14)
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JPS55166965A (en) | 1979-06-13 | 1980-12-26 | Nec Corp | Junction type fet |
JP2786046B2 (ja) | 1992-02-28 | 1998-08-13 | 山形日本電気株式会社 | 接合型電界効果トランジスタ |
JP3812421B2 (ja) | 2001-06-14 | 2006-08-23 | 住友電気工業株式会社 | 横型接合型電界効果トランジスタ |
US7569873B2 (en) | 2005-10-28 | 2009-08-04 | Dsm Solutions, Inc. | Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys |
US7560755B2 (en) * | 2006-06-09 | 2009-07-14 | Dsm Solutions, Inc. | Self aligned gate JFET structure and method |
US7557393B2 (en) | 2006-08-10 | 2009-07-07 | Dsm Solutions, Inc. | JFET with built in back gate in either SOI or bulk silicon |
JP2008053534A (ja) | 2006-08-25 | 2008-03-06 | Sanyo Electric Co Ltd | 接合型fetおよびその製造方法 |
JP5186096B2 (ja) | 2006-10-12 | 2013-04-17 | パナソニック株式会社 | 窒化物半導体トランジスタ及びその製造方法 |
WO2008137480A2 (en) * | 2007-05-01 | 2008-11-13 | Dsm Solutions, Inc. | Active area junction isolation structure and junction isolated transistors including igfet, jfet and mos transistors and method for making |
US8466501B2 (en) * | 2010-05-21 | 2013-06-18 | International Business Machines Corporation | Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET |
US10269658B2 (en) * | 2012-06-29 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit devices with well regions and methods for forming the same |
US20150194424A1 (en) * | 2014-01-06 | 2015-07-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
JP6671864B2 (ja) * | 2015-05-18 | 2020-03-25 | キヤノン株式会社 | 撮像装置の製造方法および撮像装置 |
US10062710B2 (en) * | 2016-05-11 | 2018-08-28 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits with deep and ultra shallow trench isolations and methods for fabricating the same |
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2019
- 2019-03-08 JP JP2019042902A patent/JP7128136B2/ja active Active
- 2019-06-11 CN CN201910500088.6A patent/CN111668295B/zh active Active
- 2019-08-22 US US16/548,739 patent/US11121264B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2008075488A1 (ja) | 2006-12-18 | 2008-06-26 | Sumitomo Electric Industries, Ltd. | 横型接合型電界効果トランジスタ |
WO2011155105A1 (ja) | 2010-06-07 | 2011-12-15 | パナソニック株式会社 | 半導体装置及びその製造方法 |
JP2012227489A (ja) | 2011-04-22 | 2012-11-15 | Panasonic Corp | 半導体装置およびその製造方法 |
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CN111668295A (zh) | 2020-09-15 |
JP2020145379A (ja) | 2020-09-10 |
US20200287057A1 (en) | 2020-09-10 |
CN111668295B (zh) | 2023-11-21 |
US11121264B2 (en) | 2021-09-14 |
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