US8828805B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
US8828805B2
US8828805B2 US13/368,560 US201213368560A US8828805B2 US 8828805 B2 US8828805 B2 US 8828805B2 US 201213368560 A US201213368560 A US 201213368560A US 8828805 B2 US8828805 B2 US 8828805B2
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pad
semiconductor chip
bonding pads
group
chip
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US20120238056A1 (en
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Masato Numazaki
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Renesas Electronics Corp
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Renesas Electronics Corp
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Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NUMAZAKI, MASATO
Publication of US20120238056A1 publication Critical patent/US20120238056A1/en
Priority to US14/449,231 priority Critical patent/US9236333B2/en
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Priority to US14/972,369 priority patent/US9564388B2/en
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF ADDRESS Assignors: RENESAS ELECTRONICS CORPORATION
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to manufacturing technologies of semiconductor devices and in particular to a technology effectively applicable to a semiconductor device formed by planarly arranging multiple semiconductor chips.
  • Patent Document 1 discloses the structure of a semiconductor integrated circuit device (semiconductor device) formed by planarly arranging multiple semiconductor chips.
  • the structure disclosed in Patent Document 1 is such that: in wire-bonded semiconductor chips A and B, the thickness of the semiconductor chip A on the ball bond side is made larger than the thickness of the semiconductor chip B on the stitch bond side.
  • Patent Document 1 In recent years, various types of semiconductor devices with multiple semiconductor chips incorporated therein have been developed. Among them, there are semiconductor devices in which multiple semiconductor chips are mounted and placed (plane configuration) over a single placement portion (die pad) as in, for example, Patent Document 1.
  • the present inventors considered further reducing the outer dimensions of such a semiconductor device.
  • the following measure could be used: the distance between semiconductor chips adjoining to each other is reduced and the outer dimensions of the chip placement portion are thereby reduced.
  • Patent Document 1 it is necessary to accurately carry out alignment so that a semiconductor chip mounted first does not overlap with an area (chip placement area) for a semiconductor chip mounted later.
  • FIG. 27 is a plan view illustrating the structure of a semiconductor device (semiconductor package 50 ) in a comparative example investigated by the present inventors for the purpose of comparison.
  • the semiconductor package 50 two semiconductor chips 51 , 52 are mounted side by side and mounted over one die pad (chip placement portion) 53 with a plane configuration.
  • Multiple leads 54 are arranged around the two semiconductor chips 51 , 52 and each of the semiconductor chips 51 , 52 are electrically connected with multiple leads 54 via a conductive wire 56 .
  • the die pad 53 is supported by suspending leads 55 and the die pad 53 , the semiconductor chips 51 , 52 , and part of the wires 56 and the leads 54 are sealed with a sealing body 57 formed of resin.
  • a slit (through hole) 53 a is provided between the chip placement areas adjoining to each other of the die pad 53 and the respective chip placement areas are discriminated (recognized) using this slit 53 a as a marker.
  • the present inventors examined a structure in which semiconductor chips are aligned using a technique other than slit and the distance between the semiconductor chips adjoining to each other is made smaller (for example, than in Patent Document 1). As a result, the present inventors found a problem that a void (resin unfilled failure) was produced between the semiconductor chips adjoining to each other at a resin sealing step (molding step) after the semiconductor chips were mounted.
  • the cause of this problem may be attributed to that at the resin sealing step, resin was supplied from the side of one semiconductor chip toward the side of the other semiconductor chip and the resin was not sufficiently filled between the semiconductor chips.
  • the invention was made in consideration of the above problem and it is an object thereof to provide a technology with which the formation of a void can be suppressed.
  • a manufacturing method of a semiconductor device in a representative embodiment includes the steps of: (a) providing a lead frame including a die pad comprised of a quadrangle having a pair of first sides opposed to each other and a pair of second sides intersecting with the first sides and opposed to each other, a first lead group arranged along one of the two first sides of the die pad in the plan view, a second lead group arranged along the other of the two first sides of the die pad in the plan view, and suspending leads connecting to the second sides of the die pad; (b) mounting a first semiconductor chip having a first front surface, multiple first bonding pads formed on the first front surface, and a first back surface opposite to the first front surface, in a first area of the die pad and placing a second semiconductor chip having a second front surface, multiple second bonding pads formed on the second front surface, and a second back surface opposite to the second front surface, in a second area of the die pad positioned next to the first area in the plan view; (c) respectively electrically connecting multiple external bonding pads of the
  • the second area is positioned between the first area and the other of the two second sides of the die pad in the plan view.
  • the internal bonding pads of the first semiconductor chip include a first pad group and a second pad group.
  • the internal bonding pads of the second semiconductor chip include a third pad group and a fourth pad group.
  • the internal wires include multiple first internal wires for electrically connecting the first pad group with the third pad group and multiple second internal wires for electrically connecting the second pad group with the fourth pad group.
  • the distance between the first pad group and the second pad group is longer than the distance between the third pad group and the fourth pad group; and the distance between the first pad group and the second pad group is longer than the length equivalent to multiple ones of the internal bonding pads.
  • the formation of a void can be suppressed in the assembly of a semiconductor device.
  • FIG. 1 is a plan view illustrating an example of the structure of a semiconductor device in an embodiment of the invention with a sealing body seen through;
  • FIG. 2 is a sectional view illustrating an example of the structure obtained by cutting the semiconductor device along line A-A of FIG. 1 ;
  • FIG. 3 is a sectional view illustrating an example of the structure obtained by cutting the semiconductor device along line B-B of FIG. 1 ;
  • FIG. 4 is a sectional view illustrating an example of the structure obtained by cutting the semiconductor device along line C-C of FIG. 1 ;
  • FIG. 5 is a circuit block diagram illustrating an example of the system configuration of the semiconductor device in FIG. 1 ;
  • FIG. 6 is a manufacturing flowchart illustrating an example of the assembling procedure for the semiconductor device in FIG. 1 ;
  • FIG. 7 is an enlarged partial plan view illustrating an example of the structure of a lead frame used in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 8 is an enlarged partial plan view illustrating an example of the structure obtained after first die bonding in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 9 is an enlarged partial plan view illustrating an example of the structure obtained after second die bonding in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 10 is partial sectional views illustrating an example of procedures for joining chips together via a wire in wire bonding in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 11 is partial sectional views illustrating an example of procedures for joining the chips together via the wire in wire bonding in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 12 is an enlarged partial plan view illustrating an example of the structure obtained after wire bonding in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 13 is a partial sectional view illustrating an example of the structure obtained when dies are clamped in molding in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 14 is a plan view illustrating an example of the state of resin filling during molding (through molding) in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 15 is a partial sectional view illustrating an example of the state of resin filling illustrated in FIG. 14 ;
  • FIG. 16 is a plan view illustrating an example of the state of resin filling during molding (through molding) in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 17 is a partial sectional view illustrating an example of the state of resin filling illustrated in FIG. 16 ;
  • FIG. 18 is a plan view illustrating an example of the state of resin filling during molding (through molding) in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 19 is a partial sectional view illustrating an example of the state of resin filling illustrated in FIG. 18 ;
  • FIG. 20 is a plan view illustrating an example of the structure obtained when resin filling is completed in molding (through molding) in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 21 is a partial sectional view illustrating an example of the structure obtained when resin filling is completed illustrated in FIG. 20 ;
  • FIG. 22 is a plan view illustrating the structure of a semiconductor device in a first modification to the embodiment of the invention with a sealing body seen through;
  • FIG. 23 is a plan view illustrating the structure of a semiconductor device in a second modification to the embodiment of the invention with a sealing body seen through;
  • FIG. 24 is a sectional view illustrating an example of the structure obtained by cutting the semiconductor device along line A-A of FIG. 23 ;
  • FIG. 25 is a sectional view illustrating an example of the structure obtained by cutting the semiconductor device along line B-B of FIG. 23 ;
  • FIG. 26 is a sectional view illustrating an example of the structure obtained by cutting the semiconductor device along line C-C of FIG. 23 ;
  • FIG. 27 is a plan view illustrating the structure of a semiconductor device in a comparative example with a sealing body seen through;
  • FIG. 28 is a plan view obtained by combining only portions required for the description of the circuit block diagram in FIG. 5 among the portions in the plan view in FIG. 1 .
  • FIG. 1 is a plan view illustrating an example of the structure of a semiconductor device in the embodiment of the invention with a sealing body seen through;
  • FIG. 2 is a sectional view illustrating an example of the structure obtained by cutting the semiconductor device along line A-A of FIG. 1 ;
  • FIG. 3 is a sectional view illustrating an example of the structure obtained by cutting the semiconductor device along line B-B of FIG. 1 ;
  • FIG. 4 is a sectional view illustrating an example of the structure obtained by cutting the semiconductor device along line C-C of FIG. 1 ;
  • FIG. 5 is a circuit block diagram illustrating an example of the system configuration of the semiconductor device in FIG. 1 .
  • the semiconductor device in this embodiment illustrated in FIG. 1 to FIG. 4 is a resin-sealed package.
  • two semiconductor chips first semiconductor chip, second semiconductor chip
  • die pad chip placement portion, also referred to as tab
  • the following package will be taken as an example of the above semiconductor device: a thin SOP (Small Outline Package) 6 in which multiple leads are exposed (protruded) from each of two side surfaces 4 a arranged opposite to each other among the sides of a sealing body 4 whose planar shape is a quadrangle.
  • the portions exposed (protruded) from the sealing body 4 are outer leads (outer portions) 3 c and they are so formed that they are bent in a gull wing shape outside the sealing body 4 .
  • the SOP includes: a die pad 3 a (also referred to as tab), or a plate-like chip placement portion whose planar shape is a quadrangle, illustrated in FIG. 1 ; an MCU (Micro Control Unit) chip 1 as a first semiconductor chip and an AFE (Analog Front End) chip 2 as a second semiconductor chip mounted side by side over the die pad 3 a ; multiple inner leads (inner portions) 3 b electrically connected with the respective semiconductor chips; and multiple outer leads 3 c respectively formed integrally with the inner leads 3 b.
  • MCU Micro Control Unit
  • AFE Analog Front End
  • Each of the MCU chip 1 and the AFE chip 2 is electrically connected with inner leads 3 b via a wire 5 as a conductive thin wire.
  • the die pad 3 a has a planar shape of a quadrangle (rectangle in this embodiment) including: a pair of first sides (long sides) 3 aa , 3 ab opposed to each other and a pair of second sides (short sides) 3 ac , 3 ad intersecting with the first sides 3 aa , 3 ab and opposed to each other.
  • a cutout portion (notch 3 e ) is formed in each long side. For this reason, though the planar shape of the die pad 3 a is accurately polygonal, the size (dimensions) of each of these cutout portions (notches 3 e ) is small for the die pad 3 a .
  • the shape of the die pad is defined as quadrangular despite the provision of these cutout portions (notches 3 e ).
  • Each of one second side 3 ac and the other second side 3 ad is coupled (formed integrally) with two suspending leads 3 d . Therefore, the die pad 3 a is supported by the four suspending leads 3 d .
  • each suspending lead is large in width or thickness or high in strength, only one suspending lead 3 d may be coupled to each second side as described later.
  • the MCU chip 1 , AFE chip 2 , die pad 3 a , inner leads 3 b and suspending leads 3 d , and wires 5 are sealed with a sealing body 4 formed of sealing resin.
  • the sealing body 4 is rectangular in planar shape.
  • each of the four suspending leads 3 d supporting the die pad 3 a is bent (tab descending processing) so that the height of the die pad 3 a is reduced.
  • most of the inner leads 3 b are arranged along the first sides 3 aa , 3 ab , or the long sides of the rectangular die pad 3 a , opposed to each other. More specific description will be given.
  • a first lead group 3 ba or a group of the leads arranged in positions corresponding to the first side 3 aa of the die pad 3 a among the inner leads 3 b , is arranged opposite to the first side 3 aa ; meanwhile, a second lead group 3 bb , or a group of the leads arranged in positions corresponding to the first side 3 ab of the die pad 3 a , is arranged opposite to the first side 3 ab.
  • the inner leads 3 b (the respective inner portions of the leads) making up the first lead group 3 ba and the second lead group 3 bb are bent as follows: they are bent from the outer leads 3 c (the respective outer portions of the leads) toward the die pad 3 a in the plan view. This makes it possible to wire each wire 5 so that they are substantially linearly extended in the direction in which the inner leads 3 b are extended in the plan view and reduce the wire length of each wire 5 .
  • the inner leads 3 b may be so formed that they are identical in length and linearly extended (not bent).
  • some of the bonding pads of the AFE chip 2 are also arranged on the right side 2 n as viewed in FIG. 1 .
  • some leads in the first lead group 3 ba and the second lead group 3 bb of the inner leads 3 b are so extended that the following is implemented: their tips go around toward the short sides (for example, the second side 3 ad ) of the die pad 3 a .
  • the following measure need not be taken when multiple bonding pads are arranged on three sides ( 2 j , 2 k , 2 m as viewed in FIG. 1 in this example): the tips of inner leads 3 b need not be arranged in positions corresponding to a short side of the die pad 3 a.
  • the outer leads 3 c formed integrally with the inner leads 3 b are protruded from the side surfaces 4 a of the sealing body 4 on both sides and bent and formed in a gull wing shape.
  • the MCU chip 1 and the AFE chip 2 are each bonded to the die pad 3 a by paste adhesive, such as silver paste. However, they may be bonded via a film-like adhesive, such as DAF (Die Attach Film).
  • paste adhesive such as silver paste.
  • DAF Die Attach Film
  • the MCU chip 1 is mounted in a first area 3 ae of the die pad 3 a illustrated in FIG. 7 and the AFE chip 2 is mounted in a second area 3 af positioned next to the first area 3 ae in the plan view.
  • the second side 3 ac of the two second sides 3 ac , 3 ad of the die pad 3 a will be taken as one side and the second side 3 ad will be taken as the other side.
  • the second area 3 af is positioned between the first area 3 ae and the other second side 3 ad of the die pad 3 a in the plan view.
  • a notch (cutout portion) 3 e is formed in the first side 3 aa and the first side 3 ab between the first area 3 ae and the second area 3 af in FIG. 7 in the die pad 3 a.
  • notches 3 e are used as a marker when each chip placement area (first area 3 ae , second area 3 af ) is discriminated (recognized) at the die bonding step, described later, of placing the MCU chip 1 and the AFE chip 2 over the die pad 3 a.
  • the notches 3 e as markers for the chip placement areas should be provided as close to each semiconductor chip as possible because the accuracy of position recognition can be enhanced. Therefore, it is very effective to provide the markers in the die pad 3 a .
  • the markers need not be cutouts and they could be formed in such a shape that they are protruded from the die pad 3 a .
  • a lead frame is processed by etching, it can be more easily processed when the distance between the die pad 3 a and the tip of each inner lead is identical (uniform) from inner lead 3 b to inner lead 3 b . Therefore, it is desirable that a notch 3 e should be used as a marker in terms of lead frame processing as well.
  • the distance between the MCU chip 1 and the AFE chip 2 can be made shorter than the distance between the chips in the following cases: cases where slits (through holes) 53 a are provided as in the semiconductor package 50 in the comparative example in FIG. 27 .
  • the distance (spacing) between the chips can be set to less than 0.8 mm, preferably, 0.3 to 0.4 mm or so.
  • This distance of 0.3 to 0.4 mm is smaller than or substantially identical with, for example, the lead width of each outer lead (outer portion) 3 c protruded (exposed) from the sealing body 4 .
  • the portion (inner lead, inner portion) sealed with the sealing body 4 of each lead is bent for the reduction of wire length or in accordance with the direction of extension of each wire 5 , the following takes place: it is narrower than the width of its portion (outer lead, outer portion) 3 c protruded (exposed) from the sealing body 4 .
  • the outer leads 3 c are taken as a target for comparison.
  • the distance between the two chips can be shortened as compared with the above-mentioned cases where slits 53 a are used. This makes it possible to shorten the first sides 3 aa , 3 ab as the long sides of the die pad 3 a and reduce the size of the die pad 3 a.
  • the long sides of the sealing body 4 can also be shortened and thus reduction of the size of the SOP 6 (semiconductor device) can be achieved.
  • the MCU chip 1 is a semiconductor chip in which integrated circuits, such as CPU (Central Processing Unit), memory, an input/output circuit, and a timer circuit, are formed. As illustrated in FIG. 4 , the MCU chip 1 has a front surface (first front surface, main surface) 1 a and a back surface (first back surface) 1 b located on the opposite side to the front surface 1 a . As illustrated in FIG. 1 , multiple bonding pads (first bonding pads, electrode pads) 1 c are formed on the front surface 1 a.
  • CPU Central Processing Unit
  • the AFE chip 2 is a semiconductor chip including an analog circuit portion used before analog/digital conversion. As illustrated in FIG. 4 , similarly to the MCU chip 1 , the AFE chip 2 has a front surface (second front surface, main surface) 2 a and a back surface (second back surface) 2 b located on the opposite side to the front surface 2 a . As illustrated in FIG. 1 , multiple bonding pads (second bonding pads, electrode pads) 2 c are formed on the front surface 2 a.
  • the types of the multiple bonding pads 1 c , 2 c provided in the MCU chip 1 and the AFE chip 2 illustrated in FIG. 1 are classified as follows: the pads electrically connected to the inner leads 3 b connecting to the outer leads 3 c via a wire 5 are classified as external; and the pads electrically connected between the MCU chip 1 and the AFE chip 2 via a wire 5 are classified as internal.
  • multiple external bonding pads 1 ca among the bonding pads 1 c of the MCU chip 1 and multiple inner leads 3 b in the first lead group 3 ba are electrically connected with each other via multiple external wires 5 a.
  • multiple external wires 5 a multiple external bonding pads 1 ca among the bonding pads 1 c of the MCU chip 1 and multiple inner leads 3 b in the second lead group 3 bb located on the opposite side to the first lead group 3 ba.
  • multiple external bonding pads 2 ca among the bonding pads 2 c of the AFE chip 2 and multiple inner leads 3 b in the first lead group 3 ba are electrically connected with each other via multiple external wires 5 a.
  • multiple external wires 5 a multiple external bonding pads 2 ca among the bonding pads 2 c of the AFE chip 2 and multiple inner leads 3 b in the second lead group 3 bb located on the opposite side to the first lead group 3 ba.
  • the multiple internal bonding pads 1 cb among the bonding pads 1 c and the multiple internal bonding pads 2 cb among the bonding pads 2 c are respectively electrically connected with each other via multiple internal wires 5 b.
  • multiple bonding pads 1 c electrically connected with inner leads 3 b in the first lead group 3 ba are arranged along the following side in the front surface 1 a of the MCU chip 1 : the side 1 j of the MCU chip 1 close to the first side 3 a of the die pad 3 a .
  • multiple bonding pads 1 c electrically connected with inner leads 3 b in the second lead group 3 b are arranged along the side 1 k of the MCU chip 1 close to the first side 3 ab of the die pad 3 a.
  • multiple bonding pads 2 c electrically connected with inner leads 3 b in the first lead group 3 ba are arranged along the following side in the front surface 2 a of the AFE chip 2 : the side 2 j of the AFE chip 2 close to the first side 3 a of the die pad 3 a .
  • multiple bonding pads 2 c electrically connected with inner leads 3 b in the second lead group 3 b are arranged along the side 2 k of the AFE chip 2 close to the first side 3 ab of the die pad 3 a.
  • the bonding pads 1 c , 2 c electrically connecting the two chips with each other are arranged along the respective sides 1 m , 2 m opposed to each other between the chips.
  • FIG. 5 illustrates an example of a circuit block diagram of the system configuration of the SOP 6 and a battery pack 8 is taken as an example of a peripheral circuit.
  • the SOP 6 is electrically connected with a lithium-ion battery cell 7 a , a control FET (Field Effect Transistor) 7 b , and the like and they make up the battery pack 8 .
  • a control FET Field Effect Transistor
  • a digital internal interface circuit 1 d In the MCU chip 1 embedded in the battery pack 8 , the following are formed: a digital internal interface circuit 1 d , a digital external interface circuit 1 e , an analog internal interface circuit 1 f , an analog external interface circuit 1 g , a signal processing circuit (other circuit) 1 h , and the like.
  • a digital internal interface circuit 2 d a digital external interface circuit 2 e , an analog internal interface circuit 2 f , an analog external interface circuit 2 g , a signal processing circuit (other circuit) 2 h , and the like.
  • a digital signal supplied from an external source is supplied to the digital external interface circuit 1 e of the MCU chip 1 through a lead and a bonding pad. Then it is supplied to the digital internal interface circuit 1 d by way of the signal processing circuit 1 h formed in the MCU chip 1 . Thereafter, the digital signal is transferred to the digital internal interface circuit of the AFE chip 2 through a bonding pad and a wire.
  • the digital signal processed at the AFE chip 2 is returned to the digital internal interface circuit 1 d of the MCU chip 1 through a wire and a bonding pad.
  • operations driving
  • a digital signal transferred to the digital internal interface circuit 2 d of the AFE chip 2 is converted into an analog signal at the signal processing circuit 2 h of the AFE chip 2 .
  • it is supplied to the lithium-ion battery cell 7 a as external equipment by way of the analog external interface circuit 2 g of the AFE chip 2 .
  • an analog signal is transferred to the analog internal interface circuit 1 f of the MCU chip 1 by way of the analog internal interface circuit 2 f of the AFE chip 2 , a wire, and a bonding pad.
  • not only the MCU chip 1 but also the AFE chip 2 is provided with the following external bonding pads: multiple external bonding pads 2 ca ( 2 c ) for directly communicating signals with an external source through wires 5 , inner leads 3 b , and outer leads 3 c .
  • these external bonding pads 2 ca are arranged along the side 2 j of the AFE chip 2 close to the first side 3 a of the die pad 3 a and the side 2 k close to the first side 3 ab located opposite thereto.
  • the internal bonding pads 1 cb of the MCU chip 1 are divided into the following groups: a first pad group 1 cc electrically connected with the digital internal interface circuit 1 d of the MCU chip 1 and a second pad group 1 cd electrically connected with the analog internal interface circuit 1 f of the MCU chip 1 .
  • the external bonding pads 1 ca of the MCU chip 1 the external bonding pads 1 ca arranged on the upper side of the MCU chip 1 in FIG. 1 are electrically connected with the digital external interface circuit 1 e of the MCU chip 1 ; and the external bonding pads 1 ca arranged on the lower side of the MCU chip 1 in FIG. 1 are electrically connected with the analog external interface circuit 1 g of the MCU chip 1 .
  • the internal bonding pads 2 cb of the AFE chip 2 are divided into the following groups: a third pad group 2 cc electrically connected with the digital internal interface circuit 2 d of the AFE chip 2 and a fourth pad group 2 cd electrically connected with the analog internal interface circuit 2 f of the AFE chip 2 .
  • the internal wires 5 b coupling both the chips together are divided into the following wires: multiple internal digital wires 5 c respectively electrically connecting together the bonding pads 1 c in the first pad group 1 cc and the bonding pads 2 c in the third pad group 2 cc ; and multiple internal analog wires 5 d respectively electrically connecting together the bonding pads 1 c in the second pad group 1 cd and the bonding pads 2 c in the fourth pad group 2 cd.
  • the distance L between the first pad group 1 cc and the second pad group 1 cd is larger than the distance M between the third pad group 2 cc and the fourth pad group 2 cd (L>M).
  • the outer dimensions of the respective bonding pads 1 c , 2 c in the first pad group 1 cc , second pad group 1 cd , third pad group 2 cc , and fourth pad group 2 cd are substantially identical.
  • the distance L between the first pad group 1 cc and the second pad group 1 cd is larger than or equal to the length equivalent to multiple ones of the bonding pads. In detail, the distance L is larger than or substantially equal to the length equivalent to, for example, five bonding pads.
  • each bonding pad is a quadrangle having sides aligned with the sides 1 m , 2 m and their outer dimensions are, for example, 75 ⁇ m ⁇ 75 ⁇ m. The reason why the distance L is larger than the length equivalent to five bonding pads will be described in detail later.
  • the signal processing circuit 1 h is arranged between the first pad group 1 cc and the second pad group 1 d in the plan view; and the size of the signal processing circuit 1 h (width in the direction along the side 1 m ) is substantially equivalent to five bonding pads 1 c .
  • This makes it easier for resin supplied from a gate to enter an opening (resin entering path) formed by the first pad group 1 cc and the second pad group 1 cd at a molding step.
  • resin entering path formed by the first pad group 1 cc and the second pad group 1 cd at a molding step.
  • the distance L between the first pad group 1 cc and the second pad group 1 cd is enlarged, the opening through which resin enters can be widened.
  • this distance L is too large, it is difficult to place the first pad group 1 cc and the second pad group 1 cd along an identical side.
  • it is desirable to calculate the distance based on the following: the length (2.7 mm in this embodiment) of the side 1 m of the MCU chip used in this embodiment; the outer dimensions (75 ⁇ m square) of each bonding pad; and the number of the bonding pads arranged on the side 1 m .
  • the distance may be of the length equivalent to at least, for example, three bonding pads 1 c as long as only the quality of filling of resin is taken into account.
  • the size of the signal processing circuit 1 h arranged between the first pad group 1 cc and the second pad group 1 d must be smaller than or substantially equal to the distance.
  • the MCU chip 1 is smaller than the AFE chip 2 in chip size in the plan view.
  • the MCU chip 1 is 2.1 mm ⁇ 2.7 mm in dimensions while the AFE chip 2 is 2.7 mm ⁇ 2.7 mm in dimensions.
  • the pitch of the bonding pads 1 c of the MCU chip 1 is narrower than the pitch of the bonding pads 2 c of the AFE chip 2 .
  • the pad pitch of the MCU chip 1 is 80 ⁇ m while the pad pitch of the AFE chip 2 is 130 ⁇ m.
  • the MCU chip 1 is higher than the AFE chip 2 in the degree of integration. As illustrated in FIG. 4 , however, the thickness of the MCU chip 1 is larger than the thickness of the AFE chip 2 .
  • the thickness of the MCU chip 1 is 0.3 mm while the thickness of the AFE chip 2 is 0.2 mm.
  • the digital interface circuits (digital external interface circuits 1 e , 2 e , digital internal interface circuits 1 d , 2 d ) produce noise.
  • the analog interface circuits (analog external interface circuits 1 g , 2 g , analog internal interface circuits 1 f , 2 f ) can be caused to malfunction by the influence of this noise.
  • the distance between the digital interface circuits and the analog interface circuits is widened.
  • the propagation of noise can be suppressed by widening this distance to some extent.
  • the degree of integration of the MCU chip 1 is higher than the degree of integration of the AFE chip 2 as mentioned above.
  • FIG. 28 is a plan view in which only items related to each circuit illustrated in FIG. 5 are extracted from FIG. 1 and the circuit block diagram illustrated in FIG. 5 is combined with each chip (MCU chip 1 , AFE chip 2 ).
  • Each bonding pad 1 c in this embodiment is actually laid out in the positions shown in FIG. 1 .
  • the bonding pads 1 c are shown in positions different from those in the layout in FIG. 1 to make it easy to find, for example, the following: the external bonding pads 1 ca and which circuit (the digital and analog external interface circuits 1 e , 1 g in this example) among the multiple circuits corresponds to these external bonding pads 1 ca .
  • the cutout portions (notches 3 e ) formed in the die pad 3 a and the planar shape of each lead 3 ba , 3 b are unnecessary for the description here and they are not shown in FIG. 28 .
  • the MCU chip 1 is higher than the AFE chip 2 in the degree of integration; therefore, the signal processing circuit 1 h is arranged to the vicinity of the 1 m opposed to the AFE chip 2 among the sides of the MCU chip 1 .
  • a bonding pad is not arranged over each circuit.
  • the first pad group 1 cc is away from the second pad group 1 cd by an amount equivalent to the distance L in FIG. 1 .
  • the AFE chip 2 is lower than the MCU chip 1 in the degree of integration; therefore, the signal processing circuit 2 h can be brought away from the side 2 m opposed to the MCU chip 1 among the sides of the AFE chip 2 .
  • MCU chips have been increasingly shrunk and the MCU chip 1 is high in the degree of integration of circuitry. Therefore, there is no margin in the arrangement of each circuit area and the signal processing circuit 1 h is arranged in proximity to the side 1 m close to the AFE chip 2 between the digital interface circuits and the analog interface circuits. That is, the signal processing circuit 1 h is arranged between the following groups in the plan view (not shown): the first pad group 1 cc electrically connected with the digital internal interface circuit 1 d of the MCU chip 1 and the second pad group 1 cd electrically connected with the analog internal interface circuit if of the MCU chip 1 . Therefore, a pad group (bonding pads) cannot be arranged in this area.
  • the signal processing circuit (other circuit) 2 h is arranged in an area other than the area between the digital interface circuits and the analog interface circuits.
  • the digital interface circuits and the analog interface circuits can be arranged with the area between them narrowed. As a result, it is possible to narrow the distance M between the third pad group 2 cc and the fourth pad group 2 cd illustrated in FIG. 1 .
  • the area for the signal processing circuit 1 h is located in the area between the digital interface circuits and the analog interface circuits. Therefore, the distance L between the first pad group 1 cc and the second pad group 1 cd illustrated in FIG. 1 is enlarged (L>M).
  • the area for the digital interface circuits and the area for the analog interface circuits can be separated from each other and thus it is possible to take measures against noise produced at the digital interface circuits.
  • the circuits directly linked with an external source are arranged as follows: they are arranged on the side 1 j of the MCU chip 1 close to the first side 3 a of the die pad 3 a and the side 1 k close to the first side 3 ab located opposite thereto.
  • the circuits linked with the AFE chip 2 are arranged close to the side 1 m located in the position corresponding to the AFE chip 2 .
  • the following measure is taken also with respect to the digital interface circuits and the analog interface circuits for noise suppression: they are divided and respectively arranged on the side 1 j close to the first side 3 a of the die pad 3 a and on the side 1 k close to the first side 3 ab located opposite thereto.
  • the three-side pad arrangement is adopted as illustrated in FIG. 1 . That is, the external bonding pads 1 ca are divided and arranged on the side 1 j of the MCU chip 1 close to the first side 3 a of the die pad 3 a and the side 1 k close to the first side 3 ab located opposite thereto; and all the internal bonding pads 1 cb linked with the AFE chip 2 are collectively arranged along the side 1 m of the MCU chip 1 located in the position corresponding to the AFE chip 2 .
  • the arrangement of the bonding pads 1 c of the MCU chip 1 is the three-side pad arrangement, in which the bonding pads 1 c are arranged along three sides (sides 1 j , 1 k , 1 m ) of the front surface 1 a thereof. Therefore, an inner lead 3 b is not arranged in a position corresponding to the second side 3 ac of the die pad 3 a (the side 1 n of the MCU chip 1 ).
  • a pad is not arranged on the side 1 n and the three-side pad arrangement is adopted. As a result, it is possible to delete unnecessary leads to shorten the long sides of the sealing body 4 and achieve reduction of the size of the SOP 6 .
  • a semiconductor chip 51 is of the four-side pad arrangement like the semiconductor package 50 in the comparative example in FIG. 27 , leads 54 are also arranged in positions corresponding to a short side of the die pad 53 and this makes it difficult to shorten the long sides of the sealing body 57 .
  • the three-side pad arrangement is adopted for the MCU chip 1 and thus it is possible to shorten the long sides of the sealing body 4 to achieve reduction of the size of the SOP 6 .
  • the following measure is taken in the AFE chip 2 : two bonding pads 2 c are formed also on the side 2 n of the front surface 2 a located in the position corresponding to the second side 3 ad of the die pad 3 a . Therefore, it is of the four-side pad arrangement. As the result of the provision of these two bonding pads 2 c , the two inner leads 3 b coupled to these bonding pads 2 c are linear and longer than the other inner leads 3 b.
  • the AFE chip 2 may also be of the three-side pad arrangement like the MCU chip 1 , needless to add.
  • FIG. 6 is a manufacturing flowchart illustrating an example of an assembling procedure for the semiconductor device in FIG. 1 ;
  • FIG. 7 is an enlarged partial plan view illustrating an example of the structure of a lead frame used in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 8 is an enlarged partial plan view illustrating an example of the structure obtained after first die bonding in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 9 is an enlarged partial plan view illustrating an example of the structure obtained after second die bonding in the assembly of the semiconductor device in FIG. 1 .
  • FIG. 10 is partial sectional views illustrating an example of procedures for joining chips together via a wire in wire bonding in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 10 is partial sectional views illustrating an example of procedures for joining chips together via a wire in wire bonding in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 10 is partial sectional views illustrating an example of procedures for joining chips together via a wire in wire bonding in
  • FIG. 11 is partial sectional views illustrating an example of procedures for joining the chips together via the wire in wire bonding in the assembly of the semiconductor device in FIG. 1 ; and FIG. 12 is an enlarged partial plan view illustrating an example of the structure obtained after wire bonding in the assembly of the semiconductor device in FIG. 1 .
  • FIG. 13 a partial sectional view illustrating an example of the structure obtained when dies are clamped in molding in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 14 is a plan view illustrating an example of the state of resin filling during molding in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 15 is a partial sectional view illustrating an example of the state of resin filling illustrated in FIG. 14 ;
  • FIG. 16 is a plan view illustrating an example of the state of resin filling during molding in the assembly of the semiconductor device in FIG. 1 ; and FIG. 17 is a partial sectional view illustrating an example of the state of resin filling illustrated in FIG. 16 .
  • FIG. 18 is a plan view illustrating an example of the state of resin filling during molding in the assembly of the semiconductor device in FIG. 1 ;
  • FIG. 19 is a partial sectional view illustrating an example of the state of resin filling illustrated in FIG. 18 ;
  • FIG. 20 is a plan view illustrating an example of the structure obtained when resin filling is completed in molding in the assembly of the semiconductor device in FIG. 1 ; and
  • FIG. 21 is a partial sectional view illustrating an example of the structure obtained when resin filling is completed illustrated in FIG. 20 .
  • a lead frame 3 as illustrated in FIG. 7 is provided.
  • a matrix frame in which multiple device areas 3 g are formed in a matrix configuration will be taken as an example of the lead frame 3 .
  • each device area 3 g the following are formed: a die pad 3 a whose planar shape is formed of a rectangle, one of quadrangles, having a pair of first sides 3 aa , 3 ab and a pair of second sides 3 ac , 3 ad intersecting with the first sides 3 aa , 3 ab ; multiple inner leads 3 b and outer leads 3 c arranged along one first side 3 aa of the two first sides 3 aa , 3 ab of the die pad 3 a in the plan view; multiple inner leads 3 b and outer leads 3 c arranged along the other first side 3 ab of the two first sides 3 aa , 3 ab of the die pad 3 a in the plan view; and four suspending leads 3 d connecting to the second sides 3 ac , 3 ad of the die pad 3 a.
  • an aggregate of the inner leads 3 b and outer leads 3 c arranged along the first side 3 aa of the die pad 3 a is taken as the first lead group 3 ba ; and an aggregate of the inner leads 3 b and outer leads 3 c arranged along the first side 3 ab of the die pad 3 a is taken as the second lead group 3 bb.
  • each device area 3 g the tips of each outer lead 3 c and each suspending lead 3 d are supported by a frame portion 3 h such as an inner frame and an outer frame. Between outer leads 3 c adjoining to each other, a tie bar 3 f is formed for the prevention of outflow of molding resin.
  • each rectangular (quadrangular) die pad 3 a the following are formed: the first area 3 ae for placing an MCU chip 1 ; and the second area 3 af for placing an AFE chip 2 positioned next to the first area 3 ae in the plan view.
  • the notch 3 e as a cutout portion is formed in the first sides 3 aa , 3 ab between the first area 3 ae and the second area 3 af.
  • the planar shape of the die pad 3 a in this embodiment is quadrangular, more precisely, rectangular. However, it is not limited to this and it may be square, circular, or the like as long as the MCU chip 1 and the AFE chip 2 can be mounted with a plane configuration.
  • each device area 3 g a first lead group 3 ba as an aggregate of the multiple inner leads 3 b and outer leads 3 c on one side; a second lead group 3 bb as an aggregate of the multiple inner leads 3 b and outer leads 3 c on the opposite side to the first lead group 3 ba ; a die pad 3 a arranged between the first lead group 3 ba and the second lead group 3 bb in the plan view; and multiple (four) suspending leads 3 d supporting the die pad 3 a , positioned between the first lead group 3 ba and the second lead group 3 bb in the plan view.
  • the MCU chip 1 and the AFE chip 2 are provided. Specifically, the non-defective MCU chip 1 is acquired by the dicing of Step S 1 shown in FIG. 6 and the non-defective AFE chip 2 is acquired by the dicing of Step S 2 .
  • Step S 3 - 1 first die bonding of Step S 3 - 1 and second die bonding of Step S 3 - 2 are carried out.
  • a collet for sucking is used to suck (hold) each semiconductor chip and die bonding is carried out.
  • the notches 3 e as the cutout portions formed in the first sides 3 aa , 3 ab of the die pad 3 a are recognized to discriminate the first area 3 ae and the second area 3 af from each other.
  • paste die bond material is applied to the first area 3 ae and the second area 3 af of the die pad 3 a and the semiconductor chips are mounted thereover.
  • a film-like adhesive (DAF) may be used as the die bond material.
  • the thicker MCU chip 1 is sucked and held using, for example, a rubber collet and it is mounted over the first area 3 ae in FIG. 7 .
  • the MCU chip 1 is mounted over the die pad 3 a first as illustrated in FIG. 8 .
  • the thinner AFE chip 2 is similarly sucked and held by the rubber collet and mounted over the second area 3 af in FIG. 7 .
  • the placement of the AFE chip 2 is completed as illustrated in FIG. 9 .
  • sucking collet need not be a rubber collet.
  • an inverted pyramidal collet that holds the peripheral portion of each semiconductor chip may be used.
  • the thinner AFE chip 2 is die-bonded first and then the thicker MCU chip 1 is die-bonded.
  • the reason for this is as described below.
  • the inverted pyramidal collet holds the peripheral portion of each semiconductor chip. Therefore, if a thicker chip is die-bonded first, the inverted pyramidal collet hits the thicker chip when a thinner chip is die-bonded. To prevent this problem, the thinner chip is die-bonded first.
  • Step S 4 in FIG. 6 After the completion of die bonding, the wire bonding as Step S 4 in FIG. 6 is carried out.
  • bonding pads and inner leads are respectively electrically connected with each other via multiple external wires 5 a as follows: of the bonding pads 1 c of the MCU chip 1 , the external bonding pads Ica and the inner leads 3 b corresponding thereto in the first lead group 3 ba and the second lead group 3 bb ; and of the bonding pads 2 c of the AFE chip 2 , the external bonding pads 2 ca and the inner leads 3 b corresponding thereto in the first lead group 3 ba and the second lead group 3 bb .
  • the following bonding pads are respectively electrically connected with each other via multiple internal wires 5 b : the internal bonding pads 1 cb of the bonding pads 1 c of the MCU chip 1 and the internal bonding pads 2 cb of the bonding pads 2 c of the AFE chip 2 .
  • the reason for this is as described below.
  • the loop shape of each wire loop can be more easily formed when the wire is drawn down from the side of a chip with a narrower pad pitch to the side of a chip with a wider pad pitch.
  • the MCU chip 1 narrower in pad pitch and thicker in chip thickness is taken as the 1st bond side.
  • Step S 4 - 2 ball bonding is carried out on a bonding pad 2 c of the thinner AFE chip 2 by a capillary 9 to form a bump electrode 2 i .
  • the bump electrode 2 i is a gold bump formed of, for example, a gold wire.
  • Step S 4 - 3 the capillary 9 is positioned over a bonding pad 1 c of the MCU chip 1 . Then a wire 5 is bonded to the bonding pad 1 c by the capillary 9 to carry out first bonding.
  • Step S 4 - 4 in FIG. 11 thereafter, the capillary 9 is pulled up above the bonding pad 1 c of the MCU chip 1 . Further, the capillary 9 is gently moved down toward the bonding pad 2 c of the AFE chip 2 to loop the wire 5 .
  • Step S 4 - 5 the capillary 9 is landed on the bump electrode 2 i over the bonding pad 2 c of the AFE chip 2 .
  • the wire 5 is thereby bonded to the bump electrode 2 i to carry out 2nd bonding.
  • Step S 4 - 6 this completes the wire bonding in which a wire is drawn down from the MCU chip 1 side to the AFE chip 2 side.
  • the shape of a wire loop can be stabilized by carrying out wire bonding from the higher side (MCU chip 1 ) to the lower side (AFE chip 2 ) as mentioned above.
  • the bump electrode 2 i is formed beforehand on the 2nd bond side (AFE chip 2 side). In other words, therefore, the order of bonding is as described below. First bonding is carried out on the AFE chip 2 side and subsequently, 2nd bonding is carried out on the MCU chip 1 . Thereafter, 3rd bonding is carried out on the AFE chip 2 side.
  • the distance L between the first pad group 1 cc and the second pad group 1 cd is larger than the distance M between the third pad group 2 cc and the fourth pad group 2 cd (L>M).
  • the internal wire 5 b group made up of the internal wires 5 b is open toward the second side 3 ac of the die pad 3 a.
  • the pitch of the bonding pads 2 c of the AFE chip 2 is narrower than the pitch of the bonding pads 1 c of the MCU chip 1 , the following procedure may be taken: the AFE chip 2 side is taken as first bond side and a gold bump is formed beforehand over a bonding pad 1 c of the MCU chip 1 ; and then wire bonding in which a wire is drawn up is carried out with the MCU chip 1 side taken as second bond side.
  • Wire bonding between chips is carried out as mentioned above. Further, the following processing is carried out as illustrated in FIG. 12 : each bonding pad 1 c of the MCU chip 1 and each inner lead 3 b are joined together via a wire 5 and each bonding pad 2 c of the AFE chip 2 and each inner lead 3 b are joined together via a wire 5 . The wire bonding step is thereby completed.
  • Step S 5 in FIG. 6 is carried out.
  • a through gate molding method is used. Detailed description will be given to this through molding.
  • molding dies 11 as illustrated in FIG. 13 are provided.
  • the molding dies 11 in this embodiment of the multiple cavities 12 a , 13 a thereof, cavities adjoining to each other are connected with each other via gates 12 b , 13 b and air vents 12 c , 13 c provided between the cavities adjoining to each other.
  • the cavity is a space portion formed when an upper die 12 and a lower die 13 are mated with each other.
  • Molding resin 10 is supplied into first cavities 12 a , 13 a through the gates 12 b , 13 c connecting to the first cavities 12 a , 13 a .
  • This molding resin is supplied into second cavities 12 a , 13 a arranged next to the first cavities 12 a , 13 a through a flow path provided between the first cavities 12 a , 13 a and the second cavities 12 a , 13 a .
  • this flow path is made up of gates 12 b , 13 c and air vents 12 c , 13 c .
  • the gates are formed in each of the upper die 12 and the lower die 13 ; however, the invention is not limited to this and gates may be formed in only either of them. However, it is desirable to form them in each of the upper die 12 and the lower die 13 in consideration of enhancement of the quality of filling of the resin 10 .
  • the air vents may also be formed in only either of the upper die 12 and the lower die 13 similarly to the gates.
  • the molding dies 11 for through molding include a pair of the upper die 12 and the lower die 13 .
  • the respective gates 12 b , 13 b , cavities 12 a , 13 a , and air vents 12 c , 13 c are so arranged that they communicate with one another and are positioned on a substantially straight line.
  • the resin 10 can pass through them at a stroke.
  • the gates 12 b ( 13 b ) are arranged in the area between the first lead group 3 ba and the second lead group 3 bb in the lead frame 3 illustrated in FIG. 7 . That is, the gates 12 b ( 13 b ) are arranged in positions in the lead frame 3 corresponding to the short sides (second sides 3 ac ) of each die pad 3 a whose planar shape is rectangular, equivalent to the short sides of the sealing body 4 illustrated in FIG. 1 in the plan view.
  • the lead width width of each inner lead 3 b
  • the lead spacing spacing between inner leads 3 b adjoining to each other
  • the width of each gate 12 b ( 13 b ) is 1.2 mm. Therefore, since the gate width is larger than the lead spacing, the gate 12 b ( 13 b ) cannot be arranged between inner leads 3 b .
  • each gate 12 b ( 13 b ) cannot be arranged in a position corresponding to the long sides on which the inner leads 3 b of the die pad 3 a are arranged and thus it is arranged between two suspending leads 3 d on the short sides (second sides 3 ac ) of the die pad 3 a .
  • each gate 12 b ( 13 b ) is arranged at a place in the lead frame 3 substantially equivalent to the center of each short side of the sealing body 4 in the plan view.
  • the lead frame 3 is set over the lower die 13 as illustrated in FIG. 13 so that each die pad 3 a of the wire-bonded lead frame 3 comes over a cavity 13 a.
  • the lead frame 3 is so arranged that the following is implemented with respect to the gate 13 b side and the air vent 13 c side in the direction of a flow of the resin in each cavity 13 a : the thicker MCU chip 1 comes to the gate 13 b side and the thinner AFE chip 2 comes to the air vent 13 c side.
  • the upper die 12 and the lower die 13 are clamped together to cover the MCU chip 1 and the AFE chip 2 with a cavity 12 a in the upper die 12 .
  • the molding dies 11 are brought into a predetermined high-temperature state and resin 10 is supplied through the gates 12 b , 13 b in FIG. 13 as illustrated in FIG. 14 and FIG. 15 . More specifically, resin 10 is so supplied that it flows from the side of one second side 3 ac of the two second sides (short sides) 3 ac , 3 ad of the rectangular die pad 3 a illustrated in FIG. 12 to the side of the other second side 3 ad.
  • resin 10 is so supplied that it flows from the thicker chip (MCU chip 1 ) side to the thinner chip (AFE chip 2 ) side.
  • each die pad 3 a When the planar shape of each die pad 3 a is circular, resin 10 is supplied to the side of one suspending leads 3 d located in positions corresponding to the MCU chip 1 to the side of the other suspending leads 3 d located in positions corresponding to the AFE chip 2 .
  • the supplied resin 10 flows toward the AFE chip 2 substantially along the rows of leads and gradually fills the areas above the MCU chip 1 and below the back surface of the die pad 3 a as illustrated in FIG. 16 and FIG. 17 .
  • the resin 10 covering the MCU chip 1 flows between the first pad group 1 cc and the second pad group 1 cd of the MCU chip 1 illustrated in FIG. 1 and fills the area between the MCU chip 1 and the AFE chip 2 .
  • the distance L between the first pad group 1 cc and the second pad group 1 cd is larger than the distance M between the third pad group 2 cc and the fourth pad group 2 cd (L>M).
  • the internal wire 5 b group made up of the multiple internal wires 5 b is so shaped that the following is implemented: it is open toward the second side 3 ac side (gate 12 b side) of the die pad 3 a and is narrowed as it goes toward the second side 3 ad side (air vent 12 c side).
  • the portion of the resin 10 flowing in proximity to the center over the chip inevitably behaves as follow: it goes through the opening between the first pad group 1 cc and the second pad group 1 cd and flows into the area between the MCU chip 1 and the AFE chip 2 and fills this area.
  • the resin 10 further flows toward the air vent 12 c ( 13 c ) along the rows of leads and gradually fills the areas above the AFE chip 2 and below the back surface of the die pad 3 a as illustrated in FIG. 18 and the FIG. 19 .
  • the resin enters the air vents 12 c , 13 c.
  • the resin 10 that entered the air vents 12 c , 13 c further flows into the next cavities 12 a , 13 a through the gates 12 b , 13 b of the next cavities 12 a , 13 a . It similarly fills the cavities 12 a , 13 a as illustrated in FIG. 20 and FIG. 21 .
  • the die pad 3 a , inner leads 3 b , MCU chip 1 , AFE chip 2 , external wires 5 a ( 5 ), and internal wires 5 b ( 5 ) are sealed with the resin 10 in each set of the cavities 12 a , 13 a.
  • the SOP 6 in this embodiment has two suspending leads 3 d on each side of the rectangular die pad 3 a .
  • the gates 12 b ( 13 b ) of the molding dies 11 are arranged at a place of the lead frame 3 substantially equivalent to the center of a short side of the sealing body 4 in the plan view. That is, the gates 12 b ( 13 b ) of the molding dies 11 are arranged between two suspending leads 3 d .
  • the suspending leads 3 d are arranged on both sides of the gates 12 b ( 13 b ) provided (in a substantially central part) between the first lead group 3 ba and the second lead group 3 bb in the plan view.
  • the strength for supporting the die pad 3 a can be enhanced. That is, while resin 10 is supplied into the cavities (space portions formed when the upper die and the lower die are mated together) 12 a , 13 a , inclination of the die pad 3 a can be suppressed.
  • one thick suspending lead 55 is arranged in the center of one short side of the rectangular die pad 53 .
  • the gate position in molding is shifted from the center of the short side of the die pad 53 and thus variation is prone to occur during resin filling.
  • resin 10 can be filled with the same resin pressure on the multiple external wires 5 a ( 5 ); therefore, it is possible to suppress variation during resin filling and reduce a wire sweep
  • the thicker MCU chip 1 side is taken as upstream side and the thinner AFE chip 2 side is taken as downstream side with respect to the flow of resin 10 .
  • the flow rate of resin is reduced and the resin is gelated more on the side closer to a gate than on the side farther from the gate with respect to the flow of resin in molding. Therefore, the resin is hardened and this disturbs the flow and makes a void prone to be formed.
  • the thicker MCU chip 1 is positioned on the upstream side and the thinner AFE chip 2 is positioned on the downstream side with respect to the flow of resin 10 as mentioned above.
  • the resin 10 is passed through the narrower area above the thicker MCU chip 1 when the flow rate of the resin 10 is high and the resin 10 is passed through the wider area above the thinner AFE chip 2 when the flow of the resin 10 is decelerated.
  • This enhances the fluidity of the flow of resin 10 over the chips.
  • the distance L between the first pad group 1 cc and second pad group 1 cd formed in the thicker MCU chip 1 is larger than the following distance: the distance M between the third pad group 2 cc and fourth pad group 2 cd formed in the AFE chip 2 thinner than the MCU chip 1 .
  • resin is supplied from the MCU chip 1 side to the AFE chip 2 side. As a result, the quality of filling of resin in the area between chips adjoining to each other can be further enhanced.
  • the internal wire 5 b group arising from wire bonding between chips is so shaped that it is open toward the gate 12 b . This makes it possible to enhance ease of entry of the resin 10 with enhanced fluidity into between chips and as a result, it is possible to suppress (reduce) the formation of a void in the area between chips.
  • the inner leads 3 b making up the first lead group 3 ba and the second lead group 3 b are bent from the outer leads 3 c thereof toward the die pad 3 a in the plan view.
  • each of the four suspending leads 3 d supporting the die pad 3 a is bent so that the height position of the die pad 3 a is lowered (tab descending processing) as illustrated in FIG. 4 .
  • This makes it possible to make the height equal and enhance bondability at the time of wire bonding. Further, it is possible to well balance the flow of resin 10 between above the chips and below the die pad during molding and enhance moldability.
  • Step S 6 in FIG. 6 After the completion of molding, marking of Step S 6 in FIG. 6 is carried out. At this step, a predetermined mark is put on the upper surface of the sealing body 4 by laser or the like.
  • Step S 7 the tie bar cutting shown as Step S 7 is carried out.
  • the tie bars 3 f between the outer leads 3 c adjoining to each other in the molded lead frame 3 illustrated in FIG. 7 are cut and the outer leads 3 c adjoining to each other are thereby insulated from each other.
  • Step S 8 the cutting and forming shown as Step S 8 is carried out.
  • the tips of each outer lead 3 c and each suspending lead 3 d are cut off from the frame portion 3 h and each outer lead 3 c is bent and formed into a gull wing shape.
  • FIG. 22 is a plan view illustrating the structure of a semiconductor device in a first modification to the embodiment of the invention with a sealing body seen through
  • FIG. 23 is a plan view illustrating the structure of a semiconductor device in a second modification to the embodiment of the invention with a sealing body seen through
  • FIG. 24 is a sectional view illustrating an example of the structure obtained by cutting the second modification along line A-A of FIG. 23
  • FIG. 25 is a sectional view illustrating an example of the structure obtained by cutting the second modification along line B-B of FIG. 23
  • FIG. 26 is a sectional view illustrating an example of the structure obtained by cutting the second modification along line C-C of FIG. 23 .
  • the semiconductor device in the first modification illustrated in FIG. 22 is an SOP 14 having substantially the same structure as the SOP 6 illustrated in FIG. 1 . It is different from the SOP 6 in that: the multiple inner leads 3 b in either or both of the first lead group 3 ba and the second lead group 3 bb include an oddly-shaped lead 3 bc different in shape from the other inner leads 3 b in the plan view. More specific description will be given.
  • the cutout portions (notches 3 e ) formed in the die pad 3 a are used to discriminate (recognize) the placement area for each chip.
  • the invention is not limited to this and the oddly-shaped leads 3 bc may be used in place of the cutout portions (notches 3 e ) to discriminate (recognize) the placement area for each chip.
  • the oddly-shaped leads are obtained by making the shape of an inner lead 3 b positioned in the area between the MCU chip 1 and the AFE chip 2 or in proximity thereto in the plan view different from the other inner leads 3 b . This is done by, for example, varying the thickness or the like thereof. In this modification, the odd shape may be obtained by, for example, widening or narrowing the lead width of the lead.
  • the semiconductor device in the second modification illustrated in FIG. 23 to FIG. 26 is the following SON: an SON (Small Outline Non-leaded package) 15 in which outer portions 3 k as parts of multiple leads 3 i are exposed from the lower surface 4 b of the sealing body 4 as illustrated in FIG. 24 and FIG. 25 .
  • the semiconductor device in this embodiment can also be applied to an SON 15 .
  • each lead 3 i is made up of an inner portion 3 j buried in the sealing body 4 and an outer portion 3 k exposed from the sealing body 4 .
  • the outer portions 3 k of the leads 3 i in the first lead group 3 ba and the outer portions 3 k of the leads 3 i in the second lead group 3 bb are exposed from the lower surface 4 b of the sealing body 4 formed by the molding step.
  • the die pad 3 a is also exposed in the lower surface 4 b of the sealing body 4 as illustrated in FIG. 24 to FIG. 26 . That is, the SON 15 is of a tab exposed structure and the height of each lead 3 i and the height of the die pad 3 a are identical with each other.
  • the MCU chip 1 and the AFE chip 2 are mounted in a semiconductor device (SOP 6 ) has been taken as an example.
  • the semiconductor device may be of, for example, an SIP (System In Package) type in which a memory chip and a microcomputer chip (control chip) for controlling this memory chip are mounted.
  • the invention can be utilized to assemble an electronic device formed by planarly arranging multiple semiconductor chips.

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8987063B2 (en) * 2011-02-14 2015-03-24 Renesas Electronics Corporation Manufacturing method of semiconductor device
US9991227B2 (en) 2014-05-07 2018-06-05 Mediatek Inc. Bonding pad arrangement design for multi-die semiconductor package structure

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6076068B2 (ja) * 2012-12-17 2017-02-08 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JP6129659B2 (ja) * 2013-06-25 2017-05-17 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6100648B2 (ja) 2013-08-28 2017-03-22 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP6420617B2 (ja) * 2014-09-30 2018-11-07 ルネサスエレクトロニクス株式会社 半導体装置
US10074624B2 (en) * 2015-08-07 2018-09-11 Analog Devices, Inc. Bond pads with differently sized openings
ITUB20155696A1 (it) 2015-11-18 2017-05-18 St Microelectronics Srl Dispositivo a semiconduttore, corrispondenti procedimenti di produzione ed uso e corrispondente apparecchiatura
CN106816424A (zh) * 2015-12-01 2017-06-09 安世有限公司 电子元件及其制造方法、用于该电子元件的引线框架
US9627331B1 (en) 2015-12-30 2017-04-18 Texas Instruments Incorporated Method of making a wire support leadframe for a semiconductor device
JP2018107416A (ja) * 2016-12-28 2018-07-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2018137342A (ja) 2017-02-22 2018-08-30 株式会社村田製作所 半導体装置及びその製造方法
EP3575262B1 (en) * 2018-05-22 2021-04-14 Murata Manufacturing Co., Ltd. Reducing crosstalk in a mixed-signal multi-chip mems device package
US20210043466A1 (en) 2019-08-06 2021-02-11 Texas Instruments Incorporated Universal semiconductor package molds
CN116825745B (zh) * 2023-08-31 2023-12-08 中科华艺(天津)科技有限公司 一种双芯片结构的mtcmos封装结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583511B2 (en) * 2001-05-17 2003-06-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a method of producing the same
JP2004356382A (ja) 2003-05-29 2004-12-16 Renesas Technology Corp 半導体集積回路装置
US20090057851A1 (en) * 2007-09-03 2009-03-05 Nec Electronics Corporation Method of manufacturing semiconductor device
JP2010177510A (ja) 2009-01-30 2010-08-12 Renesas Electronics Corp 半導体装置およびその製造方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2708191B2 (ja) * 1988-09-20 1998-02-04 株式会社日立製作所 半導体装置
JP2929547B2 (ja) * 1989-12-28 1999-08-03 株式会社日立製作所 樹脂封止型半導体装置の製造方法
JPH09237800A (ja) * 1996-02-29 1997-09-09 Toshiba Corp 半導体装置
JP3234153B2 (ja) 1996-04-19 2001-12-04 株式会社東芝 半導体装置
JPH11261012A (ja) * 1998-03-13 1999-09-24 Nec Corp 半導体集積回路装置
JP2003179193A (ja) * 2001-12-12 2003-06-27 Matsushita Electric Ind Co Ltd リードフレームおよびその製造方法ならびに樹脂封止型半導体装置およびその製造方法ならびに樹脂封止型半導体装置の検査方法
JP4095827B2 (ja) * 2002-05-10 2008-06-04 株式会社ルネサステクノロジ 半導体装置
JP3851845B2 (ja) * 2002-06-06 2006-11-29 株式会社ルネサステクノロジ 半導体装置
JP2007103423A (ja) * 2005-09-30 2007-04-19 Renesas Technology Corp 半導体装置及びその製造方法
CN101317267B (zh) * 2005-09-30 2010-09-08 Nxp股份有限公司 基于引线框架中的精密间距布线的系统封装(sip)器件
JP4607773B2 (ja) * 2006-01-19 2011-01-05 富士フイルム株式会社 撮像素子および撮像システム
JP4726640B2 (ja) * 2006-01-20 2011-07-20 ルネサスエレクトロニクス株式会社 半導体装置
KR100905779B1 (ko) * 2007-08-20 2009-07-02 주식회사 하이닉스반도체 반도체 패키지
JP4957513B2 (ja) * 2007-11-05 2012-06-20 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
JP5183186B2 (ja) * 2007-12-14 2013-04-17 ルネサスエレクトロニクス株式会社 半導体装置
JP5361426B2 (ja) * 2009-02-05 2013-12-04 株式会社東芝 半導体デバイス
JP5160498B2 (ja) * 2009-05-20 2013-03-13 ルネサスエレクトロニクス株式会社 半導体装置
TWI506710B (zh) * 2009-09-09 2015-11-01 Renesas Electronics Corp 半導體裝置之製造方法
JP5425584B2 (ja) * 2009-10-15 2014-02-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2011112411A (ja) * 2009-11-25 2011-06-09 Elpida Memory Inc 半導体装置
JP2011222738A (ja) * 2010-04-09 2011-11-04 Renesas Electronics Corp 半導体装置の製造方法
JP5503466B2 (ja) * 2010-08-31 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583511B2 (en) * 2001-05-17 2003-06-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a method of producing the same
JP2004356382A (ja) 2003-05-29 2004-12-16 Renesas Technology Corp 半導体集積回路装置
US20090057851A1 (en) * 2007-09-03 2009-03-05 Nec Electronics Corporation Method of manufacturing semiconductor device
JP2010177510A (ja) 2009-01-30 2010-08-12 Renesas Electronics Corp 半導体装置およびその製造方法
US8466540B2 (en) 2009-01-30 2013-06-18 Renesas Electronics Corporation Semiconductor device and manufacturing method therefor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP Office Action in JP App. No. 2011-056073, dated Jun. 3, 2014.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8987063B2 (en) * 2011-02-14 2015-03-24 Renesas Electronics Corporation Manufacturing method of semiconductor device
US9991227B2 (en) 2014-05-07 2018-06-05 Mediatek Inc. Bonding pad arrangement design for multi-die semiconductor package structure

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US20160104664A1 (en) 2016-04-14
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