TWI776134B - 利用負電壓來操作之磁阻式隨機存取記憶體的記憶胞及記憶胞陣列 - Google Patents
利用負電壓來操作之磁阻式隨機存取記憶體的記憶胞及記憶胞陣列 Download PDFInfo
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Abstract
一種磁阻式隨機存取記憶體的記憶胞,其包括一PMOS電晶體與一儲存元件。PMOS電晶體的第一端連接至記憶胞的第一端點,PMOS電晶體的控制端連接至記憶胞的第二端點。儲存元件的第一端連接至PMOS電晶體的第二端,儲存元件的第二端連接至記憶胞的第三端點。於進行一寫入動作時,記憶胞的第一端點接收一第一電壓,記憶胞的第三端點接收第二電壓,記憶胞的第二端點接收控制電壓,使得記憶胞成為第一儲存狀態。第一電壓大於第二電壓,第二電壓大於控制電壓。
Description
本發明是有關於一種非揮發性記憶體,且特別是有關於一種利用負電壓來操作的磁阻式隨機存取記憶體(Magnetoresistive Random Access Memory,以下簡稱MRAM)。
請參照第1圖,其所繪示為習知MRAM記憶胞示意圖。MRAM記憶胞110包括一開關電晶體Ms與一儲存元件120,其中儲存元件120又被稱為磁穿隧接面(Magnetic Tunnel Junction,簡稱MTJ)。
MRAM記憶胞110具有三個端點A、B、S。開關電晶體Ms的第一端連接至端點A,開關電晶體Ms的第二端連接至節點a,開關電晶體Ms的控制端連接至端點S。其中,開端電晶體Ms為NMOS電晶體,開關電晶體Ms的閘極即為控制端。
儲存元件120包括堆疊的(stacked)一固定層(pin layer)122、一阻絕層(isolation layer)124與一自由層(free layer)126。儲存元件120的固定層122連接至節點a,儲存元件120的自由層126連接至端點B。
基本上,當固定層122與自由層126的磁化方向不同時,儲存元件120具有較大的阻抗值(例如5.2K歐姆),可視為MRAM記憶胞110的第一儲存狀態,又稱為高阻抗狀態(high impedance state)。當固定層122與自由層126的磁化方向相同時,儲存元件120具有較小的阻抗值(impedance)(例如3.2K歐姆),可視為MRAM記憶胞110的第二儲存狀態,又稱為低阻抗狀態(low impedance state)。再者,提供儲存元件120不同方向的電流與電壓時,即可控制MRAM記憶胞110為第一儲存狀態或者第二儲存狀態。
當然,在第1圖中的MRAM記憶胞110中,也可以將儲存元件120的固定層122連接至端點B,儲存元件120的自由層126連接至節點a。
請參照第2A圖,其所繪示為MRAM記憶胞進行寫入動作(write operation)成為第一儲存狀態的偏壓示意圖。如第2A圖所示,提供第一電壓VDD至端點A並提供第二電壓VSS至端點B。舉例來說,第一電壓VDD為1.1V,第二電壓VSS為接地電壓(0V)。
接著,提供控制電壓(Vctrl)至端點S用以開啟(turn on)開關電晶體Ms。因此,MRAM記憶胞110內產生電流I由端點A流經節點a至端點B,使得MRAM記憶胞110成為第一儲存狀態。
當然,MRAM記憶胞110也可以進行寫入動作成為第二儲存狀態。亦即,提供第一電壓VDD至端點B,並提供第二電壓VSS至端點A。當開關電晶體Ms開啟時,則電流由端點B流經節點a至端點A,使得MRAM記憶胞110成為第二儲存狀態。
基本上,為了將MRAM記憶胞110變更為第一儲存狀態,儲存元件120的二端所接收的第一電壓差(first voltage difference)至少要0.55V以上時才能夠改變狀態。亦即,控制MRAM記憶胞110為第一儲存狀態時,端點B為第二電壓VSS(0V)且節點a的電壓Va要高於0.55V。另外,為了將MRAM記憶胞110變更為第二儲存狀態,儲存元件120的二端所接收的第二電壓差(second voltage difference)至少要0.45V以上時才能夠改變狀態。也就是說,控制MRAM記憶胞110為第二儲存狀態時,端點B為第一電壓VDD(1.1V),且節點a的電壓Va要低於0.65V。
如上所述,開關電晶體Ms為NMOS電晶體,所以開關電晶體Ms的基體(body)會連接至最低的電壓,亦即第二電壓VSS。再者,利用第一電壓VDD作為控制電壓Vctrl即可開啟開關電晶體Ms。
然而,在MRAM記憶胞110中,開關電晶體Ms的基體(body)與第二端(亦即節點a)的電壓差異,會使得開關電晶體Ms遭遇到嚴重的基體效應(body effect)以及源極退化(source degeneration),使得開關電晶體Ms的電阻很大,並使得MRAM記憶胞110在寫入動作(write operation)時,節點a的電壓Va無法到達0.55V。在此情況下,幾乎不可能讓MRAM記憶胞110轉變成為第一儲存狀態。
為了要降低電晶體Ms的電阻,所以需要提高端點S的控制電壓Vctrl,才能使得節點a的電壓Va到達0.55V。例如,將端點S的控制電壓Vctrl由第一電壓VDD(1.1V)提高至1.5V。
另外,為了讓開關電晶體Ms能夠符合安全工作區的規範(Safe Operating Area criteria,簡稱SOA規範)。當開關電晶體Ms控制端的控制電壓Vctrl提高後,也需要將開關電晶體Ms的尺寸(size)變大。因此,MRAM記憶胞110的陣列尺寸(array size)也會變大。
請參照第2B圖,其所繪示為MRAM記憶胞中節點a的電壓Va與開關電晶體Ms的尺寸關係示意圖。舉例來說,開關電晶體Ms的基本尺寸為210nm×50nm時,代表M=1。同理,M=2代表開關電晶體Ms具有2倍基本尺寸,並依此類推。
由第2B圖可知,當開關電晶體Ms的尺寸為8倍基本尺寸以上時,提供1.5V的控制電壓Vctrl才可使節點a的電壓Va到達0.55V,並控制MRAM記憶胞110成為第一儲存狀態。
換句話說,當開關電晶體Ms的尺寸小於8倍基本尺寸時,就算提供1.5V的控制電壓Vctrl,節點a的電壓Va仍無法到達0.55V。所以MRAM記憶胞110無法轉變為第一儲存狀態。
由以上的說明可知,習知MRAM記憶胞110中,由於開關電晶體Ms的尺寸無法縮小,所以將無法有效地提升MRAM的儲存密度且無法降低MRAM的製造成本。
另外,上述的偏壓方式也會造成其他的影響,說明如下。
請參照第3圖,其所繪示為習知MRAM記憶胞陣列實際運作的偏壓示意圖。MRAM記憶胞陣列包括一列多個MRAM記憶胞210、310連接至字元線WL。其中,MRAM記憶胞210包括開關電晶體Ms1與儲存元件220。MRAM記憶胞310包括開關電晶體Ms2與儲存元件320。MRAM記憶胞210、310的構造相同於第1圖,此處不再贅述。
如第3圖所示,MRAM記憶胞210的端點S1與MRAM記憶胞310的端點S2連接至字元線WL,且字元線WL連接至一電荷泵(charge pump)330,用以提供控制電壓Vctrl。舉例來說,電荷泵330可將第一電壓VDD(1.1V)提升至控制電壓Vctrl(1.5V)。
以下的說明在寫入動作(write operation)時,控制MRAM記憶胞210為第一儲存狀態且控制MRAM記憶胞310為第二儲存狀態。再者,相同列上的其他記憶胞也可以利用相同的方式來控制其狀態,此處不再贅述。
如第3圖所示,MRAM記憶胞210的端點A1接收第一電壓VDD,端點B1接收第二電壓VSS。並且,MRAM記憶胞310的端點A2接收第二電壓VSS,端點B2接收第一電壓VDD。
當字元線WL接收控制電壓Vctrl而開啟開關電晶體Ms1、Ms2時,MRAM記憶胞210內部產生電流I1由端點A1經過節點a1流至端點B1,使得MRAM記憶胞210成為第一儲存狀態;並且MRAM記憶胞310內部產生電流I2由端點B2經過節點a2流至端點A2,使得MRAM記憶胞310成為第二儲存狀態。
然而,在上述的寫入動作(write operation)時,由於控制電壓Vctrl為1.5V,端點A2接收第二電壓VSS(0V),將造成開關電晶體Ms2的閘極與源極之間的電壓差過大,使得開關電晶體Ms2超出安全工作區的規範(簡稱SOA規範),並造成開關電晶體Ms2損壞。
為了要改善上述狀況,於寫入動作(write operation)並將MRAM記憶胞310控制為第二儲存狀態時,需要將端點A2接收的電壓由第二電壓VSS(0V)提升至一第三電壓,例如0.4V。如此,才可確保開關電晶體Ms2的閘極與源極之間的電壓差符合全工作區的規範(簡稱SOA規範)。
明顯地,習知MRAM記憶胞進行寫入動作(write operation)時,根據MRAM記憶胞所要形成的狀態,需要提供控制電壓Vctrl(1.5V)、第一電壓VDD(1.1V)、第二電壓VSS(0V)以及第三電壓(0.4V)。如此,習知MRAM記憶胞陣列才可以正常運作。
本發明係有關於一種磁阻式隨機存取記憶體的一記憶胞,該記憶胞包括:一PMOS電晶體,其中該PMOS電晶體的一第一端連接至該記憶胞的一第一端點,該PMOS電晶體的一控制端連接至該記憶胞的一第二端點;以及一儲存元件,其中該儲存元件的一第一端連接至該PMOS電晶體的一第二端,該儲存元件的一第二端連接至該記憶胞的一第三端點;其中,於進行一寫入動作時,該記憶胞的該第一端點接收一第一電壓,該記憶胞的該第三端點接收一第二電壓,
該記憶胞的該第二端點接收一控制電壓,使得該記憶胞成為一第一儲存狀態;其中,該第一電壓大於該第二電壓,該第二電壓大於該控制電壓。
本發明係有關於一種磁阻式隨機存取記憶體的一記憶胞陣列,該記憶胞陣列包括:一第一記憶胞,包括一第一PMOS電晶體與一第一儲存元件;以及一第二記憶胞,包括一第二PMOS電晶體與一第二儲存元件;其中,該第一PMOS電晶體的一第一端連接至該第一記憶胞的一第一端點,該第一PMOS電晶體的一控制端連接至一字元線,該第一儲存元件的一第一端連接至該第一PMOS電晶體的一第二端,該第一儲存元件的一第二端連接至該第一記憶胞的一第二端點;其中,該第二PMOS電晶體的一第一端連接至該第二記憶胞的一第一端點,該第二PMOS電晶體的一控制端連接至該字元線,該第二儲存元件的一第一端連接至該第二PMOS電晶體的一第二端,該第二儲存元件的一第二端連接至該第二記憶胞的一第二端點;其中,於進行一寫入動作時,該字元線接收一控制電壓,該第一儲存元件的二端接收一第一電壓差,該第二儲存元件的二端接收一第二電壓差,使得該第一記憶胞成為一第一儲存狀態,且該第二記憶胞成為一第二儲存狀態。
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式詳細說明如下:
110,210,310,410,510,610:MRAM記憶胞
120,220,320,420,520,620:儲存元件
122,422:固定層
124,424:阻絕層
126,426:自由層
330:電荷泵
630:負向電荷泵
第1圖為習知MRAM記憶胞示意圖。
第2A圖為MRAM記憶胞進行寫入動作成為第一儲存狀態的偏壓示意圖。
第2B圖為MRAM記憶胞中節點a的電壓Va與開關電晶體Ms的尺寸關係示意圖。
第3圖為習知MRAM記憶胞陣列實際運作的偏壓示意圖。
第4圖為本發明MRAM記憶胞示意圖。
第5A圖為MRAM記憶胞進行寫入動作成為第一儲存狀態的偏壓示意圖。
第5B圖為提供0V的控制電壓Vctrl時,MRAM記憶胞中節點a的電壓Va與開關電晶體Ms的尺寸關係示意圖。
第5C圖為提供-0.4V的控制電壓Vctrl時,MRAM記憶胞中節點a的電壓Va與開關電晶體Ms的尺寸關係示意圖。
第6圖為本發明MRAM記憶胞陣列實際運作的偏壓示意圖。
請參照第4圖,其所繪示為本發明MRAM記憶胞示意圖。MRAM記憶胞410包括一開關電晶體Ms與一儲存元件420。
MRAM記憶胞410具有三個端點A、B、S。開關電晶體Ms的第一端連接至端點A,開關電晶體Ms的第二端連接至節點a,
開關電晶體Ms的控制端連接至端點S。其中,開關電晶體Ms為PMOS電晶體,開關電晶體Ms的閘極即為控制端。
儲存元件420包括堆疊的一固定層422、一阻絕層424與一自由層426。儲存元件420的固定層422連接至節點a,儲存元件420的自由層426連接至端點B。
基本上,當固定層422與自由層426的磁化方向不同時,儲存元件420具有較大的阻抗值(例如5.2K歐姆),可視為MRAM記憶胞410的第一儲存狀態,又稱為高阻抗狀態(high impedance state)。當固定層422與自由層426的磁化方向相同時,儲存元件420具有較小的阻抗值(impedance)(例如3.2K歐姆),可視為MRAM記憶胞410的第二儲存狀態,又稱為低阻抗狀態(low impedance state)。再者,提供儲存元件420不同方向的電流與電壓時,即可控制MRAM記憶胞410為第一儲存狀態或者第二儲存狀態。
當然,在本發明的MRAM記憶胞410中,也可以將儲存元件420的固定層422連接至端點B,儲存元件420的自由層426連接至節點a。
請參照第5A圖,其所繪示為MRAM記憶胞進行寫入動作(write operation)成為第一儲存狀態的偏壓示意圖。如第5A圖所示,提供第一電壓VDD至端點A並提供第二電壓VSS至端點B。舉例來說,第一電壓VDD為1.1V,第二電壓VSS為接地電壓(0V)。另外,由於開關電晶體Ms為PMOS電晶體,所以開關電晶體Ms的基體(body)會連接至最高的電壓,亦即第一電壓VDD。
接著,提供控制電壓(Vctrl)至端點S用以開啟(turn on)開關電晶體Ms。因此,MRAM記憶胞410內產生電流I由端點A流經節點a至端點B,使得MRAM記憶胞410成為第一儲存狀態。
當然,MRAM記憶胞410也可以進行寫入動作成為第二儲存狀態。亦即,提供第一電壓VDD至端點B,並提供第二電壓VSS至端點A。當開關電晶體Ms開啟時,則電流由端點B流經節點a至端點A,使得MRAM記憶胞410成為第二儲存狀態。
為了將MRAM記憶胞410變更為第一儲存狀態,儲存元件420的二端所接收的第一電壓差至少要0.55V以上時才能夠改變狀態。亦即,控制MRAM記憶胞410為第一儲存狀態時,端點B為第二電壓VSS(0V)且節點a的電壓Va要高於0.55V。另外,為了將MRAM記憶胞410變更為第二儲存狀態,儲存元件420的二端所接收的第二電壓差至少要0.45V以上時才能夠改變狀態。也就是說,控制MRAM記憶胞410為第二儲存狀態時,端點B為第一電壓VDD(1.1V),且節點a的電壓Va要低於0.65V。
在本發明的實施例中,開關電晶體Ms的基體(body)與第一端(亦即端點A)皆連接至第一電壓VDD,所以開關電晶體Ms不會發生基體效應(body effect)。因此,本發明MRAM記憶胞410的開關電晶體Ms於寫入運作時具有較小的電阻。
請參照第5B圖,其所繪示為提供0V的控制電壓Vctrl時,MRAM記憶胞中節點a的電壓Va與開關電晶體Ms的尺寸關係示意圖。舉例來說,開關電晶體Ms的基本尺寸為210nm×50nm時,代表
M=1。同理,M=2代表開關電晶體Ms具有2倍基本尺寸,並依此類推。
由第5B圖可知,當開關電晶體Ms的尺寸為8倍基本尺寸以上時,提供0V的控制電壓Vctrl即可使節點a的電壓Va到達0.55V,並控制MRAM記憶胞410成為第一儲存狀態。
另外,除了0V的控制電壓Vctrl之外,本發明可以調整控制電壓Vctrl為小於0V,用以進一步減少開關電晶體Ms的尺寸。請參照第5C圖,其所繪示為提供-0.4V的控制電壓Vctrl時,MRAM記憶胞中節點a的電壓Va與開關電晶體Ms的尺寸關係示意圖。
由第5C圖可知,當開關電晶體Ms的尺寸為4倍基本尺寸以上時,提供-0.4V的控制電壓Vctrl即可使節點a的電壓Va到達0.55V,並控制MRAM記憶胞410成為第一儲存狀態。
由以上的說明可知,利用較小尺寸的PMOS電晶體作為開關電晶體Ms,並搭配負值的控制電壓Vctrl,可以有效地降低開關電晶體的電阻,並成功地控制MRAM記憶胞410成為第一儲存狀態。
請參照第6圖,其所繪示為本發明MRAM記憶胞陣列實際運作的偏壓示意圖。MRAM記憶胞陣列包括一列多個MRAM記憶胞510、610連接至字元線WL。其中,MRAM記憶胞510包括開關電晶體Ms1與儲存元件520。MRAM記憶胞610包括開關電晶體Ms2與儲存元件620。MRAM記憶胞510、610的構造相同於第4圖,此處不再贅述。
如第6圖所示,MRAM記憶胞510的端點S1與MRAM記憶胞610的端點S2連接至字元線WL,且字元線WL連接至一負向電荷泵(negative charge pump)630,用以提供負電壓值的控制電壓Vctrl。舉例來說,負向電荷泵630可將第二電壓VSS(0V)降低至控制電壓Vctrl(-0.4V)。
以下的說明在寫入動作(write operation)時,控制MRAM記憶胞510為第一儲存狀態且控制MRAM記憶胞610為第二儲存狀態。再者,相同列上的其他記憶胞也可以利用相同的方式來控制其狀態,此處不再贅述。
如第6圖所示,MRAM記憶胞510的端點A1接收第一電壓VDD,端點B1接收第二電壓VSS。並且,MRAM記憶胞610的端點A2接收第二電壓VSS,端點B2接收第一電壓VDD。
當字元線WL接收負電壓值的控制電壓Vctrl而開啟開關電晶體Ms1、Ms2時,MRAM記憶胞510內部產生電流I1由端點A1經過節點a1流至端點B1,使得MRAM記憶胞510成為第一儲存狀態。再者,MRAM記憶胞610內部產生電流I2由端點B2經過節點a2流至端點A2,使得MRAM記憶胞610成為第二儲存狀態。
再者,在上述的偏壓中,開關電晶體Ms的基體(body)係連接至第一電壓VDD。然而,本發明並不限定於此。在實際的運用上,可以在適當的時機將開關電晶體的基體(body)係連接至其他電壓(例如一第四電壓,且該第四電壓相同於節點a的電壓Va)。或者,在其他的實施例中,如果需要讓開關電晶體Ms1符合安全工作區的規範
(簡稱SOA規範)時,MRAM記憶胞510端點A1所接收的電壓可以稍微低於第一電壓VDD。
由以上的說明可知,本發明提出一種利用負電壓來操作的MRAM。MRAM中包括一MRAM記憶胞陣列,連接至一字元線WL。再者,MRAM記憶胞410中包括一開關電晶體Ms與一儲存元件420,且開關電晶體Ms為PMOS電晶體。
於寫入動作時,提供負值的控制電壓Vctrl至字元線,並且選擇性地將第一電壓VDD與第二電壓VSS提供至MRAM記憶胞410的二端點A、B,即可控制MRAM記憶胞410成為第一儲存狀態或者第二儲存狀態。其中,第一電壓VDD大於第二電壓VSS,且第二電壓VSS大於控制電壓Vctrl。
由於開關電晶體的尺寸降低,因此將可有效地提升MRAM的儲存密度並降低MRAM的製造成本。
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
410:MRAM記憶胞
420:儲存元件
422:固定層
424:阻絕層
426:自由層
Claims (13)
- 一種磁阻式隨機存取記憶體的一記憶胞,該記憶胞包括:一PMOS電晶體,其中該PMOS電晶體的一第一端連接至該記憶胞的一第一端點,該PMOS電晶體的一控制端連接至該記憶胞的一第二端點;以及一儲存元件,其中該儲存元件的一第一端連接至該PMOS電晶體的一第二端,該儲存元件的一第二端連接至該記憶胞的一第三端點;其中,於進行一寫入動作時,該記憶胞的該第一端點接收一第一電壓,該記憶胞的該第三端點接收一第二電壓,該記憶胞的該第二端點接收一控制電壓,使得該記憶胞成為一第一儲存狀態;其中,該PMOS電晶體的一基體接收一節點電壓,且該節點電壓相同於該儲存元件的該第一端之電壓;其中,該第一電壓大於該第二電壓,該第二電壓大於等於該控制電壓。
- 如請求項1所述之記憶胞,其中於進行該寫入動作時,該記憶胞的該第一端點接收該第二電壓,該記憶胞的該第三端點接收該第一電壓,該記憶胞的該第二端點接收該控制電壓,使得該記憶胞成為一第二儲存狀態。
- 如請求項2所述之記憶胞,其中該第一電壓為一正值電壓,該第二電壓為一接地電壓,該控制電壓為一負值電壓。
- 如請求項1所述之記憶胞,其中該儲存元件包括堆疊的一固定層、一阻絕層與一自由層,且該固定層連接至該PMOS電晶體的該第二端,該自由層連接至該記憶胞的該第三端點。
- 如請求項1所述之記憶胞,其中該儲存元件包括堆疊的一固定層、一阻絕層與一自由層,且該自由層連接至該PMOS電晶體的該第二端,該固定層連接至該記憶胞的該第三端點。
- 一種磁阻式隨機存取記憶體的一記憶胞,該記憶胞包括:一PMOS電晶體,其中該PMOS電晶體的一第一端連接至該記憶胞的一第一端點,該PMOS電晶體的一控制端連接至該記憶胞的一第二端點;以及一儲存元件,其中該儲存元件的一第一端連接至該PMOS電晶體的一第二端,該儲存元件的一第二端連接至該記憶胞的一第三端點;其中,於進行一寫入動作時,該記憶胞的該第一端點接收一第一電壓,該記憶胞的該第三端點接收一第二電壓,該記憶胞的該第二端點接收一控制電壓,該PMOS電晶體的一基體接收一第三電壓,使得該記憶胞成為一第一儲存狀態,且使得該PMOS電晶體符合一安全工作區的規範;其中,該第三電壓大於該第一電壓,該第一電壓大於該第二電壓,該第二電壓大於該控制電壓。
- 如請求項6所述之記憶胞,其中利用一負向電荷泵,將該第二電壓降低至該控制電壓。
- 一種磁阻式隨機存取記憶體的一記憶胞陣列,該記憶胞陣列包括:一第一記憶胞,包括一第一PMOS電晶體與一第一儲存元件;以及一第二記憶胞,包括一第二PMOS電晶體與一第二儲存元件;其中,該第一PMOS電晶體的一第一端連接至該第一記憶胞的一第一端點, 該第一PMOS電晶體的一控制端連接至一字元線,該第一儲存元件的一第一端連接至該第一PMOS電晶體的一第二端,該第一儲存元件的一第二端連接至該第一記憶胞的一第二端點;其中,該第二PMOS電晶體的一第一端連接至該第二記憶胞的一第一端點,該第二PMOS電晶體的一控制端連接至該字元線,該第二儲存元件的一第一端連接至該第二PMOS電晶體的一第二端,該第二儲存元件的一第二端連接至該第二記憶胞的一第二端點;其中,該第一PMOS電晶體的一基體接收一第一節點電壓,且該第一節點電壓相同於該第一儲存元件的該第一端之電壓,該第二PMOS電晶體的一基體接收一第二節點電壓,且該第二節點電壓相同於該第二儲存元件的該第一端之電壓;其中,於進行一寫入動作時,該字元線接收一控制電壓,該第一儲存元件的二端接收一第一電壓差,該第二儲存元件的二端接收一第二電壓差,使得該第一記憶胞成為一第一儲存狀態,且該第二記憶胞成為一第二儲存狀態。
- 如請求項8所述之記憶胞陣列,其中於進行一寫入動作時,該第一記憶胞的該第一端點接收一第一電壓,該第一記憶胞的該第二端點接收一第二電壓,該第二記憶胞的該第一端點接收該第二電壓,該第二記憶胞的該第二端點接收該第一電壓,該第一電壓大於該第二電壓,且該第二電壓大於等於該控制電壓。
- 如請求項9所述之記憶胞陣列,其中該第一電壓為一正值電壓,該第二電壓為一接地電壓,該控制電壓為一負值電壓。
- 如請求項9所述之記憶胞陣列,其中該第一儲存元件包括堆疊的一固定層、一阻絕層與一自由層,且該固定層連接至該第一PMOS電晶體的該第二端,該自由層連接至該第一記憶胞的該第二端點。
- 如請求項9所述之記憶胞陣列,其中該第一儲存元件包括堆疊的一固定層、一阻絕層與一自由層,且該自由層連接至該第一PMOS電晶體的該第二端,該固定層連接至該第一記憶胞的該第二端點。
- 如請求項9所述之記憶胞陣列,其中利用一負向電荷泵,將該第二電壓降低至該控制電壓。
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