TWI675480B - 異質接面場效電晶體及其製造方法 - Google Patents
異質接面場效電晶體及其製造方法 Download PDFInfo
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Abstract
一種製造異質接面場效電晶體的方法,該異質接面場效電晶體包含由數個疊置層所構成的半導體構造,該方法包含:-在基材層(1)上設置緩衝層(2)、通道層(3)和阻障層(4),該等層係由具有Ga(1-p-q)Al(p)In(q)N型的六角形結晶構造的材料製成;-在沉積於該阻障層上的介電質遮蔽層(5)中形成開口;-利用高溫磊晶來在由被形成在該遮蔽層中的開口所界定的成長區上,成長半導體材料(6、6’),該半導體材料具有六角形結晶構造,即Ga(1-x’-y’)Al(x’)In(y’)N,且摻雜鍺;及-在利用磊晶所沉積的該材料上沉積源極或汲極接觸電極(15、16),且在該成長區外部的位置沉積閘極(13)。
Description
本發明涉及一種異質接面場效電晶體或高電子遷移率電晶體(high-electron mobility transistor;HEMT),其包含由沉積在基材上的數個疊置層所構成的半導體構造,該等疊置層係由具有Ga(1-p-q)Al(p)In(q)N型的六角形結晶構造的半導體材料組成,其中p和q可以在0(含)與1(含)之間的範圍內,p+q的總和係小於或等於1,且一對{p、q}係每層都不一樣的。該基材的材料可以是例如GaN、AlN、SiC、Si、鑽石或藍寶石。
此電晶體將可用於單石型微波積體電路(MMIC)或其他電路。
HEMT(也稱為HFET(異質構造場效電晶體)或MODFET(調變摻雜型場效電晶體))一般包含:-通道層,係由第一半導體材料(例如GaN)製成;-阻障層,係在該通道層上,由具有比該第一材料還寬的帶隙(bandgap)及比該第一材料還低電子親和力的半導體材料(例如,AlN或AlGaN)製成;-閘極,係與該阻障層形成蕭特基接面(Schottky junction):及-源極和汲極,係在該閘極的兩側。
已知在沉積該等源極和汲極之前,在與這些電極相應的位置利用磊晶成長來沉積摻雜Si原子的GaN層。此經摻雜的GaN的層使得可以用較小的尺寸設計電晶體。使用遮蔽層來界定這些位置。
文獻K.Shinohara等的「具有fT260GHz之側向放大的GaN DH-HEMT之電子速度提升(Electron Velocity Enhancement in Laterally Scaled GaN DH-HEMTs with fT of 260GHz)」(IEEE電子裝置期刊第32卷第8期,2011年8月)、和T.Fujiwara的「具有強化模式運作的低歐姆接觸電阻m-面AlGaN/GaN異質接面場效電晶體(Low Ohmic Contact Resistance m-Plane AlGaN/GaN Heterojunction Field-Effect Transistors with Enhancement-Mode Operations)」(應用物理快訊3(2010))記載在GaN基材上製造數個HEMT的方法的兩個例子,其包含局部化磊晶成長經摻雜矽的層的步驟。
在本案主張優先權用的法國專利申請案所建立的初步檢索報告中所引用的文獻US 2005/0258451,記載了藉由沉積摻雜矽、鍺或氧的GaN層所得到的HEMT,尤其是在足以阻止朝向與該等汲極和源極相應的位置的質量傳遞(mass transport)之低溫下進行。即使提到了在數個可行方案當中選擇了摻雜鍺,但在磊晶沉積經摻雜矽的GaN的情況下選擇低溫以防止與質量傳遞有關的缺點,即形態問題的風險,尤其是SiN沉澱、不均勻的GaN層高度和不佳的可再現性。因為缺
少了質量傳遞,因此GaN係以相對薄的厚度沉積以防止了其延伸超出介電質層。
需要一種相對簡便的方法,其可以改善局部化的磊晶層的邊緣的界定。
提供一種製造異質接面場效電晶體的方法,該異質接面場效電晶體包含由數個疊置層所構成的半導體構造,該方法包含:a)在基材上設置:緩衝層,係由具有六角形結晶構造的半導體材料,即Ga(1-x-y)Al(x)In(y)N組成,其中x和y係在0(含)與1(含)之間的範圍內,x+y的總和係小於或等於1;通道層,係在該緩衝層上,此通道層係由具有六角形結晶構造的材料,即Ga(1-z-w)Al(z)In(w)N組成,其中z和w可以在0(含)與1(含)之間的範圍內,z+w的總和係小於或等於1,z和w當中至少一個係分別與x或y不同;及阻障層,係在此通道層上,此阻障層係由具有六角形結晶構造的材料,即Ga(1-z’-w’)Al(z’)In(w’)N組成,其中z’和w’可以在0(含)與1(含)之間的範圍內,z’+w’的總和係小於或等於1,z’和w’當中至少一個係分別與z或w不同;b)將由介電質(dielectric)製成的遮蔽層沉積在該阻障層上;c)在該遮蔽層中形成開口;
d)利用高溫磊晶來在與被形成在該遮蔽層中的該開口的位置相應的成長區上成長半導體材料,該半導體材料具有六角形結晶構造,即Ga(1-x’-y’)Al(x’)In(y’)N,且摻雜鍺,其中x’和y’係在0(含)與1(含)之間的範圍內,x’+y’的總和係小於或等於1;e)將源極或汲極接觸電極沉積在於步驟d)中利用磊晶所沉積的該材料上;及f)將閘極沉積在該成長區外部的位置。
應瞭解的是,用語「高溫」和「高的溫度」意指溫度高到足以使具有六角形結晶構造(Ga(1-x’-y’)Al(x’)In(y’)N)且摻雜鍺的半導體材料因質量傳遞而朝向該成長區遷移以至於步驟d)是有選擇性的。此溫度,例如,可以是在700℃與1200℃之間且嚴格來說,較佳為高於960℃且低於或等於1150℃,且更佳為在970℃與1150℃之間。
此方法可以使利用磊晶所沉積的材料的層獲得輪廓比先前技術還清晰的邊緣,此方法在這些邊緣接著可以在製造方法的其他步驟中作為對準記號(alignment marks)的方面上可以是有優勢的。
於是,此方法可使該閘極精確地與該歐姆源極接點和/或該歐姆汲極接點貼近地對齊,藉此可以得到較低的串聯電阻並增進了該等電晶體的增益(gain)。
已確認了藉由應用此方法,便可得到一種產品,其中摻雜鍺的材料具有被充分界定的結晶構造而使由此所得到的該成長層的側面邊緣是稍微傾斜的,且
因此相對遠離該遮蔽層的大致垂直的邊緣。因此,如文獻US 2005/0258451所述,此方法可以避免在步驟d)之前需要用另一個遮罩來保護該介電質遮蔽層,並因此避免了在步驟d)之後需要移除此遮罩。
另外,利用上述的方法,可以在沒有使該方法變得更久或更複雜的風險下,沉積成長材料以形成相對厚的,尤其是比該遮蔽層還厚的成長層。因此,該遮蔽層可以具有相對小的厚度,例如在0.1nm與100nm之間,較佳為在0.5nm與10nm之間,更佳為在1nm與7nm之間而例如為5nm。
因此,此方法可製造一種異質接面場效電晶體,該電晶體包含由數個疊置層所構成的半導體構造,該等半導體層基本上係由III-V材料組成,來自週期表第V欄的原子係氮原子,而來自此表第III欄的原子係選自鎵、鋁和銦。
尤其是,基材的材料,例如可以是GaN、AlN、SiC、Si、鑽石或藍寶石。
x’和y’當中至少一個可以分別與z’或w’不同,即,x’具有與z’不同的值和/或y’具有與w’不同的值。換言之,該成長層的材料可以與該阻障層的材料不同。
該通道層的材料係與該緩衝層的材料不同,即,z具有與x不同的值和/或w具有與y不同的值。
該阻障層的材料係與該通道層的材料不同,即,z’具有與z不同的值和/或w’具有與w不同的值。
另外,挑選該阻障層和通道層的材料以製造出HEMT。該阻障層的材料的帶隙(bandgap)係比該通道層的材料的帶隙還寬,而該阻障層的材料的電子親和力係比該通道層的材料的電子親和力還低,使得二維電子氣形成在該通道層中。因此,挑選該通道層和阻障層的材料以促使電子累積在這兩層之間的界面。該閘極可以接著與此阻障層形成蕭特基接面。
緩衝層、通道層和阻障層的材料可以是未摻雜的,或甚至是摻雜的。
該構造可以包含一個以上的緩衝層,即,如其本身所知的,緩衝厚度可以是多層。同樣地,該構造可以包含一個以上的通道層和一個以上的阻障層。
應瞭解的是,用語「摻雜鍺」和「經摻雜鍺的」意指磊晶材料每立方公分包含的鍺原子數量係大於或等於1018。
較佳但不限於,可以將該遮蔽層完全從與此層相應的位置移除,或是僅從此位置的一部分確實地移除。可以在該成長步驟d)之後和在沉積該閘極之前實施此移除步驟。
在步驟c)中,在該遮蔽層中的開口可以藉由以蝕刻移除該遮蔽層的材料來形成。
較佳但不限於,可以準備將此開口延伸而使該阻障層在該開口的位置具有較小的厚度或者零厚度。在後者的情況下,係將該阻障層之與此位置相應的部分移除。
較佳但不限於,該方法可以為了將在該遮蔽層中所形成的該開口的位置中的材料移除而包含在該磊晶成長步驟d)之前的蝕刻步驟,以便移除該阻障層之與此位置相應的部分。
局部地移除該阻障層使得形成該源極-汲極電流的電子不必克服與該阻障層相應的位能障壁(potential barrier),因此在該閘極相對於該源極為最大正偏壓的情況下,大大減少產生源極-汲極電流所需的該汲極-源極電壓Vds。此舉減少了在使用該電晶體的期間其所散發的熱量,並因此增加了包含這種電晶體的放大器的功率效率。由於不必克服該阻障層,因而可以挑選如下的阻障層:經最佳化而即使當該阻障層的厚度係相對小的,例如約1-10nm,例如4nm時,仍帶來相對低的反蕭特基漏電流、和相對強的靜電極化。因為這個小的厚度,因此本質互導(intrinsic transconductance)係相對高的,以致於該電晶體的截止頻率可以是相對高的。因為該強靜電極化,因此該通道層中的電子濃度係相對高的,藉此該電晶體可以得到相對高的每單位長度的最大電流。這種具有高位能障壁和強靜電極化的阻障層,例如,可以在由GaN製成的通道層上、在具有與GaN類似的基本結晶胞元尺寸的緩衝層上,由材料AlN形成。
較佳為,可以準備例如藉由蝕刻來將此開口延伸,以致於該通道層在該開口的位置具有較小的厚度、或是零厚度。例如,可以藉由例如將在此區域的該通道層的厚度減少(即,該開口係界定在該通道層中),
或者甚至是藉由移除該通道層之與此位置相應的部分(即,該開口穿過該通道層以便到達該緩衝層或該基材),來執行該蝕刻步驟以將在步驟c)中所形成的該開口延伸直到該通道層。
該磊晶材料可以僅摻雜鍺,或確實地還包含其他摻雜劑原子,例如矽原子,所有這些其他摻雜劑之每立方公分的原子數係小於或等於鍺之每立方公分的原子數。換言之,以該等摻雜劑的數量計,鍺相當於至少50%,較佳為至少80%,且較佳為趨近100%。
較佳但不限於,該方法可以包括前分離步驟以便在該電晶體的周圍形成非導電區。依此方式,確保了在該電晶體的運作期間,在該源極與汲極之間流動的電子確實地穿過受該閘極電壓控制的該通道層。可以採用習知的方法,例如蝕刻該等活性層或植入離子。這對任何場效電晶體而言是習知的方法並為本發明所屬技術領域中具有通常知識者所知悉的。
較佳但不限於,在步驟d)中,可以準備採用金屬有機氣相磊晶(MOVPE)技術,或者甚至是金屬有機氣相沉積(MOCVD)技術。此技術在該方法可以接著予以相對簡單地工業化的方面上可以是相對有優勢的。
當然,本發明不限於選擇在步驟d)所採用的磊晶技術。例如,可以準備採用分子束磊晶(MBE)技術或可以利用磊晶來成長III-V材料的任何其他技術,其中來自週期表第V欄的原子係氮原子,而來自此表第III欄的原子係選自鎵、鋁和銦。
較佳但不限於,在步驟e)中沉積複數個金屬層,例如:-連結層(tie layer),係將例如鈦沉積在該磊晶材料上;-阻障層,係將例如鉑沉積在該連結層上;及-導電層,係將例如金沉積在該阻障層上。
或者是,可以由例如鎢的單一層形成該接觸電極。
較佳但不限於,沉積該接觸電極的步驟e)可以在沒有進行熔合退火(alloying anneal)下實施。
此接觸電極可以包含源極。
在此步驟中,可以準備進一步沉積汲極。
另外,提供一種異質接面場效電晶體,其包含由數個疊置層所構成的半導體構造,在基材上依堆積順序包含:-緩衝層,係由具有六角形結晶構造的半導體材料,即Ga(1-x-y)Al(x)In(y)N組成,其中x和y係在0(含)與1(含)之間的範圍內,x+y的總和係小於或等於1;-通道層,此通道層係由具有六角形結晶構造的材料,即Ga(1-z-w)Al(z)In(w)N組成,其中z和w可以在0(含)與1(含)之間的範圍內,z+w的總和係小於或等於1,z係與x不同和/或w係與y不同;及-阻障層,此阻障層係由具有六角形結晶構造的材料,即Ga(1-z’-w’)Al(z’)In(w’)N組成,其中z’和w’可以在0(含)與1(含)之間的範圍內,z’+w’的總和係小於或等於1,z’係與z不同和/或w’係與w不同;
-成長材料的層(被稱為磊晶層),係利用高溫磊晶來沉積在與被形成在介電質遮蔽層中的開口的位置相應的成長區上,此成長材料係由摻雜鍺的Ga(1-x’-y’)Al(x’)In(y’)N組成且具有六角形結晶構造,其中x’和y’係在0(含)與1(含)之間的範圍內,x’+y’的總和係小於或等於1;及-源極或汲極接觸電極,係在該成長材料的層上;及閘極,係在該成長區外部的位置。
此HEMT的成長材料的層的邊緣可以被相對銳利地界定。尤其是,這些邊緣可以具有相對於垂直線的斜度,斜度可以是在5°與60°之間而通常為約45°。
另外,提供一種積體電路,其包含如上所述的電晶體。
尤其是,此電路可以是單石型微波積體電路(MMIC)。
在本專利申請案中,用語「在...上」應當同時解釋為意指「直接在...上」及「間接在...上」,即,沉積在另一層上的層可以與此另一層接觸,或者它們確實由一個或多個中間層所分隔開。
參照圖式以更清楚地瞭解本發明,該等圖式以範例的形式圖示了非限定性實施形態。
1‧‧‧基材層
2‧‧‧緩衝層
3‧‧‧通道層
4、8、11‧‧‧阻障層
5‧‧‧遮蔽層
5A、5B‧‧‧部分
6、6’‧‧‧成長材料
7、10‧‧‧連結層
9、12‧‧‧導電層
13‧‧‧閘極
14‧‧‧區
15、16‧‧‧接觸電極
61‧‧‧壁
第1至5圖係根據本發明的一個實施形態的一個範例的一個例示性電晶體在製造期間的橫截面簡化示意圖。
第6圖係根據本發明的一個實施形態的一個例示性電晶體的橫截面簡化示意圖。
相同的元件符號在各圖之間用於表示相同或類似的元件。
參照第1圖,準備在由例如矽組成的基材1上疊置具有六角形結晶構造的數個半導體層,該等層係由III-V材料組成,其中來自週期表第V欄的原子係氮原子而來自此表第III欄的原子係選自鎵、鋁和銦。
此疊置(superposition)包含:-緩衝層2,係例如由未摻雜的Ga0.9Al0.1N組成;-通道層3,係例如由未摻雜的GaN組成;-阻障層4,係例如由未摻雜的AlN組成;及-介電質遮蔽層5,係例如由SiN組成。
在第1圖中,以本身已知的方式實施並涉及額外的遮蔽層(未圖示,因為在該蝕刻後被移除了)的蝕刻步驟,係用於在該遮蔽層5中形成數個開口,以致於那裡僅留下此層5的中央部分。
參照第2圖,使用以本身已知的方式實施的蝕刻步驟以移除與被形成在該遮蔽層5中的數個開口同水平的材料,以便移除該阻障層4之與這些位置相應的部分。因此,只有該阻障層4之與該層5的中央部分的位置相應的部分保留下來。由此所界定的該等開口現在朝厚度方向上延伸直到該通道層3。
參照第3圖,使用MOVPE技術在與該遮蔽層5中的該等開口相應的位置上成長經摻雜鍺的成長材料6、6’。該成長材料具有六角形結晶構造且由用鍺摻雜為N+的GaN組成。
選擇鍺,可以在該等部分6、6’與5之間得到被相對銳利地界定的界面。
此步驟係在高溫下實施,以便得到實質的質量傳遞。例如,該等晶種(seed)可以輕易地遷移越過約10μm的距離。在汲極與源極位置之間的距離通常小於一μm的情形下,可以理解到確保了選擇性。除此之外已形成在該層5上的晶種的材料因擴散在該層5表面上方朝向該等層6、6’傳遞,在熱力學上更利於進行合併(incorporation)。此高溫方法可以限制且較佳地防止了在該層5的表面上形成晶種。
由於該成長材料係摻雜鍺,因此機械應力係比經摻雜Si的材料還低,且沒有觀察到容易在摻雜矽的情況下所遭遇的形態問題。該等成長層6、6’的厚度在整個晶圓上是相對均勻的。相對清楚地界定出該等區6、6’的邊緣。再現性也是令人滿意的。
這些局部化磊晶區6、6’的高度摻雜是有優勢的,因為這樣可以避開為了產生具有與該等電極的低接觸電阻之好的歐姆接觸所需的熔合(alloying),且因此形態的改良和較佳的控制可以使尺寸更進一步地減少。
為了進行這個處理,可以在該局部化磊晶步驟中執行下述條件:
-載氣(vector gas):H2和/或N2和/或其他惰性氣體;-溫度在700℃與1150℃之間,而較佳為在1000℃與1150℃;-反應物:三甲基鎵(和/或其他的Ga有機金屬物)和NH3(和/或其他提供N的分子,如肼(hydrazine)、胺等);-摻雜劑氣體:GeH4(和/或有機-鍺化合物或鍺的鹵化物)。
選擇該等反應物和摻雜劑的比例以便得到每立方公分含有1018個以上鍺原子(例如每立方公分含有1020或1021個鍺原子)的材料,接下來,如本身已知的,將接點15、16沉積在這些成長材料的層6、6’上。更精確地說,每個接點15、16包含:-連結層7、10,係將例如鈦的層沉積在該磊晶材料上;-阻障層8、11,係將例如鉑的層沉積在該相應的連結層7、10上;及-導電層9、12,係將例如金的層沉積在該相應的阻障層8、11上。
或許注意到,沉積該等源極和汲極接點15、16而沒有退火。
接下來,參照第5圖,蝕刻該遮蔽層5的一個部分,從而只有此遮蔽層SiN的兩個部分5A、5B留下來,且在由此所界定的新開口中沉積金屬閘極接點13。
或者是,當然能夠準備在沉積該閘極接點之前完全移除該遮蔽層5。
再者,或者是,也可以在適當的地方留下全部或是一些該SiN遮蔽層5,而在其上沉積該閘極。
如本身已知的,此閘極接點也可以由複數個層(連結層、阻障層和導電層)所構成,未圖示。例如,能夠準備鎳連結層和金導電層。
由此所得到的該電晶體可以含有相對高品質的經摻雜鍺的部分6、6’。
選擇該等通道層和阻障層3、4的材料以形成二維電子氣(如第5圖中標示14的區所示)。用鍺摻雜該等層6、6’可以在該等層6、3、4與6’、3、4之間得到被相對銳利地界定的接面,這有助於改善該電晶體的性能。
此電晶體可以生產出具有較高性能的MMIC電路。
參照第6圖,所顯示的HEMT係在由此所界定的該開口延伸直到該緩衝層2的條件下藉由蝕刻特定位置的材料來得到,該等位置係由與第1至4圖中的元件符號5相應的該介電質遮蔽層所界定。換言之,該開口延伸穿過該通道層3。
接著,在高溫下沉積該磊晶成長材料。
如此圖所明確顯示的,由此所得到的該等成長層6、6’具有數個稍微傾斜的壁61,該等壁61係設置成相對於該遮蔽層後退。
該等層6、6’可以具有使得它們在高度上延伸超過該遮蔽層的厚度而沒有遮住後者的風險。
因此,可以選擇在該方法一開始就沉積相對薄的遮蔽層。
Claims (8)
- 一種製造異質接面場效電晶體的方法,該異質接面場效電晶體包含由數個疊置層所構成的半導體構造,該方法包含:a)在基材層(1)上設置:緩衝層(2),係由具有六角形結晶構造的半導體材料,即Ga(1-x-y)Al(x)In(y)N組成,其中x和y係在0(含)與1(含)之間的範圍內,x+y的總和係小於或等於1;通道層(3),係在該緩衝層上,此通道層係由具有六角形結晶構造的材料,即Ga(1-z-w)Al(z)In(w)N組成,其中z和w可以在0(含)與1(含)之間的範圍內,z+w的總和係小於或等於1,z和w當中至少一個係分別與x或y不同;及阻障層(4),係在此通道層上,此阻障層係由具有六角形結晶構造的材料,即Ga(1-z’-w’)Al(z’)In(w’)N組成,其中z’和w’可以在0(含)與1(含)之間的範圍內,z’+w’的總和係小於或等於1,z’和w’當中至少一個係分別與z或w不同;b)將介電質遮蔽層(5)沉積在該阻障層上;c)在該介電質遮蔽層中形成開口;d)利用高溫磊晶來在由被形成在該遮蔽層中的該開口所界定的成長區上成長半導體材料(6、6’),該半導體材料具有六角形結晶構造,即Ga(1-x’-y’)Al(x’)In(y’)N,且摻雜鍺,其中x’和y’係在0(含)與1(含)之間的範圍內,x’+y’的總和係小於或等於1, 其中磊晶之溫度係高至足以使具有Ga(1-x’-y’)Al(x’)In(y’)N之六角形結晶構造且摻雜鍺的半導體材料的組成原子因質量傳遞而朝向該成長區遷移;e)將源極或汲極接觸電極(15、16)沉積在於步驟d)中利用磊晶所沉積的該材料上;及f)將閘極(13)沉積在該成長區外部的位置。
- 如請求項1的方法,其中在步驟d)中採用金屬有機氣相磊晶技術。
- 如請求項1的方法,其中在步驟d)中採用分子束磊晶技術。
- 如請求項1至3中任一項的方法,其中在步驟d)中利用磊晶所沉積的該材料係摻雜鍺的GaN。
- 如請求項1至3中任一項的方法,其中沉積該接觸電極的步驟e)係在沒有進行熔合退火(alloying anneal)下實施。
- 如請求項1至3中任一項的方法,其中步驟d)係嚴格地在高於960℃且低於或等於1150℃下實施。
- 一種異質接面場效電晶體,包含由數個疊置層所構成的半導體構造,在基材層(1)上依堆積順序包含:-緩衝層(2),係由具有六角形結晶構造的材料,即Ga(1-x-y)Al(x)In(y)N組成,其中x和y係在0(含)與1(含)之間的範圍內,x+y的總和係小於或等於1;-通道層(3),係在該緩衝層上,此通道層係由具有六角形結晶構造的材料,即Ga(1-z-w)Al(z)In(w)N組成, 其中z和w可以在0(含)與1(含)之間的範圍內,z+w的總和係小於或等於1,z和w當中至少一個係分別與x或y不同;及-阻障層(4),係在此通道層上,此阻障層係由具有六角形結晶構造的材料,即Ga(1-z’-w’)Al(z’)In(w’)N組成,其中z’和w’可以在0(含)與1(含)之間的範圍內,z’+w’的總和係小於或等於1,z’和w’當中至少一個係分別與z或w不同;-磊晶材料的層(6、6’),係利用高溫磊晶來沉積在與被形成在介電質遮蔽層(5)中的開口的位置相應的成長區上,此成長材料具有六角形結晶構造且由摻雜鍺的Ga(1-x’-y’)Al(x’)In(y’)N組成,其中x’和y’係在0(含)與1(含)之間的範圍內,x’+y’的總和係小於或等於1,且其中該磊晶的溫度係足以使該摻雜鍺的材料具有被充分界定的結晶構造,而使該成長層的側面邊緣相對於垂直方向,傾斜5°至60°之間;及-接觸電極(15、16),係在該成長材料的層上;及閘極(13),係在該成長區外部的位置。
- 一種單石型微波積體電路,包含如請求項7的電晶體。
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