RU2016140219A - Полевой транзистор с гетеропереходом - Google Patents
Полевой транзистор с гетеропереходом Download PDFInfo
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- 239000000463 material Substances 0.000 claims 13
- 239000013078 crystal Substances 0.000 claims 8
- 238000000034 method Methods 0.000 claims 7
- 230000004888 barrier function Effects 0.000 claims 5
- 238000000407 epitaxy Methods 0.000 claims 5
- 230000000873 masking effect Effects 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 4
- 230000005669 field effect Effects 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- 238000000137 annealing Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 230000004927 fusion Effects 0.000 claims 1
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000001451 molecular beam epitaxy Methods 0.000 claims 1
- 150000002902 organometallic compounds Chemical class 0.000 claims 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Claims (22)
1. Способ изготовления полевого транзистора с гетеропереходом, содержащего полупроводниковую структуру из наложенных друг на друга слоев, включающий:
a) обеспечение на слое подложки (1):
буферного слоя (2), состоящего из полупроводникового материала с гексагональной кристаллической структурой Ga(1-x-y)Al(x)In(y)N, где x и y имеют значения в интервале от 0 включительно до 1 включительно, а сумма x+y меньше или равна 1;
канального слоя (3) на буферном слое, причем этот канальный слой состоит из материала с гексагональной кристаллической структурой Ga(1-z-w)Al(z)In(w)N, где z и w могут иметь значения в интервале от 0 включительно до 1 включительно, сумма z+w меньше или равна 1, а по меньшей мере один из z и w отличается от x или y соответственно;
барьерного слоя (4) на этом канальном слое, причем этот барьерный слой состоит из материала с гексагональной кристаллической структурой Ga(1-z'-w')Al(z')In(w')N, где z' и w' могут иметь значения в интервале от 0 включительно до 1 включительно, сумма z'+w' меньше или равна 1, а по меньшей мере один из z' и w' отличается от z или w соответственно;
b) нанесение диэлектрического маскирующего слоя (5) на барьерный слой;
c) выполнение отверстия в диэлектрическом маскирующем слое;
d) выращивание эпитаксией при высокой температуре полупроводникового материала (6, 6’) с гексагональной кристаллической структурой Ga(1-x'-y')Al(x')In(y')N, легированного германием, где x' и y' имеют значения в интервале от 0 включительно до 1 включительно, а сумма x'+y' меньше или равна 1, на зоне роста, заданной выполненным в маскирующем слое отверстием;
e) нанесение контактного электрода истока или стока (15, 16) на материал, нанесенный эпитаксией на стадии d);
f) нанесение электрода затвора (13) в местоположении вне зоны роста.
2. Способ по п. 1, в котором в ходе стадии d) применяют метод эпитаксии из газовой фазы металлоорганических соединений.
3. Способ по п. 1, в котором в ходе стадии d) применяют метод молекулярно-пучковой эпитаксии.
4. Способ по любому из пп. 1-3, в котором материал, нанесенный эпитаксией на стадии d), представляет собой материал GaN, легированный германием.
5. Способ по любому из пп. 1-4, в котором стадию e) нанесения контактного электрода осуществляют без отжига для сплавления.
6. Способ по любому из пп. 1-5, в котором стадию d) осуществляют при температуре строго большей, чем 960°C, и меньшей или равной 1150°C.
7. Полевой транзистор с гетеропереходом, содержащий полупроводниковую структуру из наложенных друг на друга слоев, содержащую в порядке наслоения на слой подложки (1):
- буферный слой (2), состоящий из материала с гексагональной кристаллической структурой Ga(1-x-y)Al(x)In(y)N, где x и y имеют значения в интервале от 0 включительно до 1 включительно, а сумма x+y меньше или равна 1;
- канальный слой (3) на буферном слое, причем этот канальный слой состоит из материала с гексагональной кристаллической структурой Ga(1-z-w)Al(z)In(w)N, где z и w могут иметь значения в интервале от 0 включительно до 1 включительно, сумма z+w меньше или равна 1, а по меньшей мере один из z и w отличается от x или y соответственно;
- барьерный слой (4) на этом канальном слое, причем этот барьерный слой состоит из материала с гексагональной кристаллической структурой Ga(1-z'-w')Al(z')In(w')N, где z' и w' могут иметь значения в интервале от 0 включительно до 1 включительно, сумма z'+w' меньше или равна 1, а по меньшей мере один из z' и w' отличается от z или w соответственно;
- слой эпитаксиального материала (6, 6'), нанесенный эпитаксией при высокой температуре на зоне роста, соответствующей местоположению отверстия, выполненного в диэлектрическом маскирующем слое (5), причем этот выращенный материал обладает гексагональной кристаллической структурой и состоит из легированного германием Ga(1-x'-y')Al(x')In(y')N, где x' и y' имеют значения в интервале от 0 включительно до 1 включительно, а сумма x'+y' меньше или равна 1;
- контактный электрод (15, 16) на слое выращенного материала и электрод затвора (13) в местоположении снаружи от зоны роста.
8. Монолитная сверхвысокочастотная интегральная схема, содержащая транзистор по п. 7.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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FR1452132 | 2014-03-14 | ||
FR1452132A FR3018629B1 (fr) | 2014-03-14 | 2014-03-14 | Structure semiconductrice formant transistor hemt |
PCT/FR2015/050600 WO2015136218A1 (fr) | 2014-03-14 | 2015-03-10 | Transistor a effet de champ et a heterojonction. |
Publications (3)
Publication Number | Publication Date |
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RU2016140219A true RU2016140219A (ru) | 2018-04-17 |
RU2016140219A3 RU2016140219A3 (ru) | 2018-10-31 |
RU2686575C2 RU2686575C2 (ru) | 2019-04-29 |
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RU2016140219A RU2686575C2 (ru) | 2014-03-14 | 2015-03-10 | Полевой транзистор с гетеропереходом |
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US (1) | US10340376B2 (ru) |
EP (1) | EP3117465B1 (ru) |
JP (1) | JP6933466B2 (ru) |
KR (1) | KR102329663B1 (ru) |
ES (1) | ES2927683T3 (ru) |
FR (1) | FR3018629B1 (ru) |
PL (1) | PL3117465T3 (ru) |
RU (1) | RU2686575C2 (ru) |
TW (1) | TWI675480B (ru) |
WO (1) | WO2015136218A1 (ru) |
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JP6627408B2 (ja) * | 2015-10-21 | 2020-01-08 | 住友電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
US10388753B1 (en) * | 2017-03-31 | 2019-08-20 | National Technology & Engineering Solutions Of Sandia, Llc | Regrowth method for fabricating wide-bandgap transistors, and devices made thereby |
JP7013710B2 (ja) * | 2017-08-07 | 2022-02-01 | 住友電気工業株式会社 | 窒化物半導体トランジスタの製造方法 |
JP7099255B2 (ja) * | 2018-11-01 | 2022-07-12 | 富士通株式会社 | 化合物半導体装置、高周波増幅器及び電源装置 |
US10964803B2 (en) | 2018-11-19 | 2021-03-30 | Texas Instruments Incorporated | Gallium nitride transistor with a doped region |
JP2021144993A (ja) | 2020-03-10 | 2021-09-24 | 富士通株式会社 | 半導体装置 |
US11978790B2 (en) * | 2020-12-01 | 2024-05-07 | Texas Instruments Incorporated | Normally-on gallium nitride based transistor with p-type gate |
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JP4742399B2 (ja) * | 1999-03-12 | 2011-08-10 | 住友化学株式会社 | 3−5族化合物半導体の製造方法 |
JP2001135575A (ja) * | 1999-03-12 | 2001-05-18 | Sumitomo Chem Co Ltd | 3−5族化合物半導体 |
JP3518455B2 (ja) * | 1999-12-15 | 2004-04-12 | 日亜化学工業株式会社 | 窒化物半導体基板の作製方法 |
JP3430206B2 (ja) * | 2000-06-16 | 2003-07-28 | 学校法人 名城大学 | 半導体素子の製造方法及び半導体素子 |
US7432142B2 (en) * | 2004-05-20 | 2008-10-07 | Cree, Inc. | Methods of fabricating nitride-based transistors having regrown ohmic contact regions |
JP2006013006A (ja) * | 2004-06-23 | 2006-01-12 | Shin Etsu Handotai Co Ltd | 半導体複合基板及びそれを用いた化合物半導体素子 |
JP2008085215A (ja) * | 2006-09-28 | 2008-04-10 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2008124262A (ja) * | 2006-11-13 | 2008-05-29 | Oki Electric Ind Co Ltd | 選択再成長を用いたAlGaN/GaN−HEMTの製造方法 |
US8017933B2 (en) * | 2008-06-30 | 2011-09-13 | Intel Corporation | Compositionally-graded quantum-well channels for semiconductor devices |
JP5689869B2 (ja) * | 2009-04-08 | 2015-03-25 | エフィシエント パワー コンヴァーション コーポレーション | エンハンスメントモードGaNHEMTデバイス、及びその製造方法 |
JP5702058B2 (ja) * | 2009-08-28 | 2015-04-15 | 日本碍子株式会社 | 半導体素子用エピタキシャル基板、半導体素子、および、半導体素子用エピタキシャル基板の作製方法 |
KR101890749B1 (ko) * | 2011-10-27 | 2018-08-23 | 삼성전자주식회사 | 전극구조체, 이를 포함하는 질화갈륨계 반도체소자 및 이들의 제조방법 |
JP5881383B2 (ja) * | 2011-11-17 | 2016-03-09 | 株式会社豊田中央研究所 | 半導体装置とその製造方法 |
US10164038B2 (en) * | 2013-01-30 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of implanting dopants into a group III-nitride structure and device formed |
RU136238U1 (ru) * | 2013-07-04 | 2013-12-27 | Открытое акционерное общество "Научно-производственное предприятие "Пульсар" | Гетероструктурный модулировано-легированный полевой транзистор |
US9159822B2 (en) * | 2014-02-24 | 2015-10-13 | International Business Machines Corporation | III-V semiconductor device having self-aligned contacts |
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- 2015-03-10 KR KR1020167028540A patent/KR102329663B1/ko active IP Right Grant
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Publication number | Publication date |
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PL3117465T3 (pl) | 2022-11-28 |
US20170092751A1 (en) | 2017-03-30 |
KR20160132108A (ko) | 2016-11-16 |
FR3018629A1 (fr) | 2015-09-18 |
EP3117465A1 (fr) | 2017-01-18 |
ES2927683T3 (es) | 2022-11-10 |
EP3117465B1 (fr) | 2022-07-20 |
FR3018629B1 (fr) | 2022-10-28 |
TW201539742A (zh) | 2015-10-16 |
WO2015136218A1 (fr) | 2015-09-17 |
RU2016140219A3 (ru) | 2018-10-31 |
JP2017514316A (ja) | 2017-06-01 |
JP6933466B2 (ja) | 2021-09-08 |
US10340376B2 (en) | 2019-07-02 |
TWI675480B (zh) | 2019-10-21 |
RU2686575C2 (ru) | 2019-04-29 |
KR102329663B1 (ko) | 2021-11-22 |
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