TWI625990B - 佈線板及其製造方法 - Google Patents
佈線板及其製造方法 Download PDFInfo
- Publication number
- TWI625990B TWI625990B TW101133257A TW101133257A TWI625990B TW I625990 B TWI625990 B TW I625990B TW 101133257 A TW101133257 A TW 101133257A TW 101133257 A TW101133257 A TW 101133257A TW I625990 B TWI625990 B TW I625990B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- wiring
- insulating layer
- insulating
- contact layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
- H05K3/387—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive for electroless plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011198564A JP6081693B2 (ja) | 2011-09-12 | 2011-09-12 | 配線基板及び配線基板の製造方法 |
| JP2011-198564 | 2011-09-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201325339A TW201325339A (zh) | 2013-06-16 |
| TWI625990B true TWI625990B (zh) | 2018-06-01 |
Family
ID=47828810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW101133257A TWI625990B (zh) | 2011-09-12 | 2012-09-12 | 佈線板及其製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US9060455B2 (enExample) |
| JP (1) | JP6081693B2 (enExample) |
| KR (1) | KR101906883B1 (enExample) |
| TW (1) | TWI625990B (enExample) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11127664B2 (en) * | 2011-10-31 | 2021-09-21 | Unimicron Technology Corp. | Circuit board and manufacturing method thereof |
| JP6322885B2 (ja) * | 2012-11-01 | 2018-05-16 | 味の素株式会社 | プリント配線板の製造方法 |
| JP2015008261A (ja) * | 2013-05-28 | 2015-01-15 | 京セラサーキットソリューションズ株式会社 | 配線基板およびその製造方法 |
| US20140353019A1 (en) * | 2013-05-30 | 2014-12-04 | Deepak ARORA | Formation of dielectric with smooth surface |
| JP6158676B2 (ja) * | 2013-10-15 | 2017-07-05 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
| JP6375121B2 (ja) * | 2014-02-27 | 2018-08-15 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
| JP6341714B2 (ja) | 2014-03-25 | 2018-06-13 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
| JP6133227B2 (ja) * | 2014-03-27 | 2017-05-24 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
| US9736939B2 (en) | 2014-09-19 | 2017-08-15 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board and method of manufacturing printed circuit board |
| US9899248B2 (en) * | 2014-12-03 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor packages having through package vias |
| US10325853B2 (en) | 2014-12-03 | 2019-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor packages having through package vias |
| JP6447075B2 (ja) * | 2014-12-10 | 2019-01-09 | 凸版印刷株式会社 | 配線基板、半導体装置及び半導体装置の製造方法 |
| JP2016219478A (ja) * | 2015-05-15 | 2016-12-22 | イビデン株式会社 | 配線基板及びその製造方法 |
| JP2017152536A (ja) * | 2016-02-24 | 2017-08-31 | イビデン株式会社 | プリント配線板及びその製造方法 |
| US10037961B2 (en) * | 2016-05-17 | 2018-07-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out package and method of fabricating the same |
| US10801137B2 (en) | 2016-07-21 | 2020-10-13 | International Business Machines Corporation | Glass cloth including attached fibers |
| JP2018032659A (ja) * | 2016-08-22 | 2018-03-01 | イビデン株式会社 | プリント配線板およびプリント配線板の製造方法 |
| JP2019121771A (ja) * | 2018-01-11 | 2019-07-22 | イビデン株式会社 | プリント配線板 |
| TWI713842B (zh) | 2018-05-10 | 2020-12-21 | 恆勁科技股份有限公司 | 覆晶封裝基板之製法及其結構 |
| JP7359531B2 (ja) * | 2018-06-07 | 2023-10-11 | 新光電気工業株式会社 | 配線基板、配線基板の製造方法及び半導体パッケージの製造方法 |
| KR20220015011A (ko) * | 2020-07-30 | 2022-02-08 | 삼성전기주식회사 | 인쇄회로기판 및 전자부품 내장기판 |
| GB202018676D0 (en) * | 2020-11-27 | 2021-01-13 | Graphcore Ltd | Controlling warpage of a substrate for mounting a semiconductor die |
| CN114597193A (zh) * | 2020-12-07 | 2022-06-07 | 群创光电股份有限公司 | 电子装置的重布线层结构及其制作方法 |
| TWI812977B (zh) * | 2021-07-16 | 2023-08-21 | 欣興電子股份有限公司 | 電路板強化結構及其製作方法 |
| JP7743265B2 (ja) * | 2021-10-26 | 2025-09-24 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
| CN117812852A (zh) * | 2022-09-23 | 2024-04-02 | 鹏鼎控股(深圳)股份有限公司 | 多层线路板的制造方法 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1756654A (zh) * | 2002-12-27 | 2006-04-05 | 日本电气株式会社 | 薄片材料及布线板 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1696714B1 (en) * | 1996-12-13 | 2009-12-02 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| TW410534B (en) * | 1997-07-16 | 2000-11-01 | Matsushita Electric Industrial Co Ltd | Wiring board and production process for the same |
| WO2000045430A1 (en) * | 1999-01-29 | 2000-08-03 | Matsushita Electric Industrial Co., Ltd. | Electronic parts mounting method and device therefor |
| JP3371894B2 (ja) * | 1999-09-17 | 2003-01-27 | ソニーケミカル株式会社 | 接続材料 |
| JP4486196B2 (ja) * | 1999-12-08 | 2010-06-23 | イビデン株式会社 | 多層プリント配線板用片面回路基板およびその製造方法 |
| JP2001230551A (ja) * | 2000-02-14 | 2001-08-24 | Ibiden Co Ltd | プリント配線板並びに多層プリント配線板及びその製造方法 |
| JP4444435B2 (ja) * | 2000-03-06 | 2010-03-31 | ソニーケミカル&インフォメーションデバイス株式会社 | プリント配線基板及びプリント配線基板の製造方法 |
| JP2002064270A (ja) * | 2000-08-17 | 2002-02-28 | Matsushita Electric Ind Co Ltd | 回路基板とその製造方法 |
| JP2003332734A (ja) * | 2002-05-14 | 2003-11-21 | Mitsubishi Gas Chem Co Inc | アディティブ法プリント配線板の製造方法。 |
| JP4072176B2 (ja) | 2005-08-29 | 2008-04-09 | 新光電気工業株式会社 | 多層配線基板の製造方法 |
| US7523545B2 (en) * | 2006-04-19 | 2009-04-28 | Dynamic Details, Inc. | Methods of manufacturing printed circuit boards with stacked micro vias |
| JP5092662B2 (ja) * | 2007-10-03 | 2012-12-05 | 凸版印刷株式会社 | 印刷配線板の製造方法 |
| JP2009170753A (ja) * | 2008-01-18 | 2009-07-30 | Panasonic Corp | 多層プリント配線板とこれを用いた実装体 |
| JP5295596B2 (ja) | 2008-03-19 | 2013-09-18 | 新光電気工業株式会社 | 多層配線基板およびその製造方法 |
| JP2010129942A (ja) * | 2008-12-01 | 2010-06-10 | Fujitsu Ltd | 回路基板及びその製造方法並びに半導体装置及びその製造方法 |
| JP2011051247A (ja) * | 2009-09-02 | 2011-03-17 | Hitachi Chem Co Ltd | 熱硬化性樹脂組成物層付き金属箔、金属張積層板及びプリント配線板 |
| JP5482083B2 (ja) * | 2009-10-14 | 2014-04-23 | 日立化成株式会社 | 配線板用積層板及びその製造方法、プライマー層用樹脂フィルム、多層配線板及びその製造方法 |
-
2011
- 2011-09-12 JP JP2011198564A patent/JP6081693B2/ja active Active
-
2012
- 2012-09-05 KR KR1020120098078A patent/KR101906883B1/ko active Active
- 2012-09-06 US US13/604,833 patent/US9060455B2/en active Active
- 2012-09-12 TW TW101133257A patent/TWI625990B/zh active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1756654A (zh) * | 2002-12-27 | 2006-04-05 | 日本电气株式会社 | 薄片材料及布线板 |
Also Published As
| Publication number | Publication date |
|---|---|
| US9060455B2 (en) | 2015-06-16 |
| TW201325339A (zh) | 2013-06-16 |
| KR101906883B1 (ko) | 2018-12-05 |
| KR20130028861A (ko) | 2013-03-20 |
| US20130062108A1 (en) | 2013-03-14 |
| JP6081693B2 (ja) | 2017-02-15 |
| JP2013062314A (ja) | 2013-04-04 |
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