JP7359531B2 - 配線基板、配線基板の製造方法及び半導体パッケージの製造方法 - Google Patents
配線基板、配線基板の製造方法及び半導体パッケージの製造方法 Download PDFInfo
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- JP7359531B2 JP7359531B2 JP2018109772A JP2018109772A JP7359531B2 JP 7359531 B2 JP7359531 B2 JP 7359531B2 JP 2018109772 A JP2018109772 A JP 2018109772A JP 2018109772 A JP2018109772 A JP 2018109772A JP 7359531 B2 JP7359531 B2 JP 7359531B2
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- H01L2924/3511—Warping
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
Description
第1の実施形態について説明する。第1の実施形態は配線基板に関する。
先ず、配線基板の構造について説明する。図4は、第1の実施形態に係る配線基板の構造を示す平面図であり、図5は、第1の実施形態に係る配線基板の構造を示す断面図である。図5は、図4中のI-I線に沿った断面図に相当する。
次に、配線基板1の製造方法について説明する。図7~図12は、第1の実施形態に係る配線基板の製造方法を示す図である。
次に、第2の実施形態について説明する。第2の実施形態は、第1の実施形態に係る配線基板1を用いた半導体パッケージの製造方法に関する。図13~図16は、第2の実施形態に係る半導体パッケージの製造方法を示す図である。
次に、第3の実施形態について説明する。第3の実施形態は、第1の実施形態に係る配線基板1を用いた半導体パッケージの製造方法に関する。図17~図20は、第2の実施形態に係る半導体パッケージの製造方法を示す図である。
次に、第4の実施形態について説明する。第4の実施形態は配線基板に関する。
先ず、配線基板の構造について説明する。図21は、第4の実施形態に係る配線基板の構造を示す断面図である。
次に、配線基板2の製造方法について説明する。図23~図25は、第4の実施形態に係る配線基板の製造方法を示す図である。
5 半導体パッケージ
100 支持体
200 配線部材
200A 第1の面
200B 第2の面
300 キャリア
301 第1の層
302 第2の層
303 第3の層
311、312、400 接着剤
500 半導体チップ
501 バンプ
502 封止樹脂
503 バンプ
Claims (7)
- 第1の面及び第2の面を備え、前記第1の面と前記第2の面との間に複数の配線層を有する配線部材と、
接着剤を介して前記第1の面に接着され、互いに熱膨張係数が異なる複数の層を有するキャリアと、
を有し、
前記複数の配線層に含まれる配線のピッチは、前記第1の面側よりも前記第2の面側で狭くなっており、
加熱されたときに前記第2の面が前記第1の面よりも大きく熱膨張し、
加熱されたときに前記配線部材が反ろうとする方向と前記キャリアが反ろうとする方向とが逆向きであり、
前記キャリアに含まれる層は、前記配線部材に近いものほど低い熱膨張係数を有することを特徴とする配線基板。 - 第1の面及び第2の面を備え、前記第1の面と前記第2の面との間に複数の配線層を有する配線部材と、
接着剤を介して前記第1の面に接着され、互いに熱膨張係数が異なる複数の層を有するキャリアと、
を有し、
前記複数の配線層に含まれる配線のピッチは、前記第1の面側よりも前記第2の面側で狭くなっており、
加熱されたときに前記第1の面が前記第2の面よりも大きく熱膨張し、
加熱されたときに前記配線部材が反ろうとする方向と前記キャリアが反ろうとする方向とが逆向きであり、
前記キャリアに含まれる層は、前記配線部材に近いものほど高い熱膨張係数を有することを特徴とする配線基板。 - 前記キャリアが有する層の数が3以上であることを特徴とする請求項1又は2に記載の配線基板。
- 支持体上に、第1の面及び第2の面を備え、前記第1の面と前記第2の面との間に複数の配線層を有する配線部材を、前記第2の面が前記支持体側となるように形成する工程と、
互いに熱膨張係数が異なる複数の層を有するキャリアを、接着剤を介して前記第1の面に接着する工程と、
前記配線部材を前記支持体から分離する工程と、
を有し、
前記複数の配線層に含まれる配線のピッチは、前記第1の面側よりも前記第2の面側で狭くなっており、
加熱されたときに前記第2の面が前記第1の面よりも大きく熱膨張し、
加熱されたときに前記配線部材が反ろうとする方向と前記キャリアが反ろうとする方向とが逆向きであり、
前記キャリアに含まれる層は、前記配線部材に近いものほど低い熱膨張係数を有することを特徴とする配線基板の製造方法。 - 支持体上に、第1の面及び第2の面を備え、前記第1の面と前記第2の面との間に複数の配線層を有する配線部材を、前記第2の面が前記支持体側となるように形成する工程と、
互いに熱膨張係数が異なる複数の層を有するキャリアを、接着剤を介して前記第1の面に接着する工程と、
前記配線部材を前記支持体から分離する工程と、
を有し、
前記複数の配線層に含まれる配線のピッチは、前記第1の面側よりも前記第2の面側で狭くなっており、
加熱されたときに前記第1の面が前記第2の面よりも大きく熱膨張し、
加熱されたときに前記配線部材が反ろうとする方向と前記キャリアが反ろうとする方向とが逆向きであり、
前記キャリアに含まれる層は、前記配線部材に近いものほど高い熱膨張係数を有することを特徴とする配線基板の製造方法。 - 請求項1乃至3のいずれか1項に記載の配線基板上に半導体チップを実装する工程と、
前記半導体チップを封止する工程と、
前記半導体チップの封止後に、前記キャリアを前記配線部材から剥離する工程と、
を有することを特徴とする半導体パッケージの製造方法。 - 前記半導体チップを実装する工程と前記半導体チップを封止する工程との間に、前記キャリアに含まれる層の一部を剥離する工程を有することを特徴とする請求項6に記載の半導体パッケージの製造方法。
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