JP6693850B2 - キャリア基材付き配線基板、キャリア基材付き配線基板の製造方法 - Google Patents
キャリア基材付き配線基板、キャリア基材付き配線基板の製造方法 Download PDFInfo
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- JP6693850B2 JP6693850B2 JP2016192806A JP2016192806A JP6693850B2 JP 6693850 B2 JP6693850 B2 JP 6693850B2 JP 2016192806 A JP2016192806 A JP 2016192806A JP 2016192806 A JP2016192806 A JP 2016192806A JP 6693850 B2 JP6693850 B2 JP 6693850B2
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- 239000000463 material Substances 0.000 title claims description 315
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 238000000034 method Methods 0.000 title claims description 12
- 239000010410 layer Substances 0.000 claims description 164
- 239000012790 adhesive layer Substances 0.000 claims description 115
- 239000000758 substrate Substances 0.000 claims description 70
- 238000007689 inspection Methods 0.000 claims description 20
- 239000000853 adhesive Substances 0.000 claims description 15
- 230000001070 adhesive effect Effects 0.000 claims description 15
- 239000000523 sample Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 description 34
- 229910000679 solder Inorganic materials 0.000 description 31
- 229920005989 resin Polymers 0.000 description 28
- 239000011347 resin Substances 0.000 description 28
- 229910052751 metal Inorganic materials 0.000 description 17
- 239000002184 metal Substances 0.000 description 17
- 239000004744 fabric Substances 0.000 description 10
- 239000007788 liquid Substances 0.000 description 9
- 229920001187 thermosetting polymer Polymers 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 238000005520 cutting process Methods 0.000 description 7
- 239000003822 epoxy resin Substances 0.000 description 7
- 239000011521 glass Substances 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229920000106 Liquid crystal polymer Polymers 0.000 description 6
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 6
- 239000011888 foil Substances 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 238000007789 sealing Methods 0.000 description 6
- 238000005452 bending Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 239000012779 reinforcing material Substances 0.000 description 5
- 239000004925 Acrylic resin Substances 0.000 description 4
- 229920000178 Acrylic resin Polymers 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229920003986 novolac Polymers 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 239000004760 aramid Substances 0.000 description 3
- 229920003235 aromatic polyamide Polymers 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 239000002335 surface treatment layer Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 239000004821 Contact adhesive Substances 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 229920006231 aramid fiber Polymers 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- -1 for example Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000002759 woven fabric Substances 0.000 description 1
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-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
- H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/202—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
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- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
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- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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Description
なお、添付図面は、便宜上、特徴を分かりやすくするために特徴となる部分を拡大して示している場合があり、各構成要素の寸法比率などが実際と同じであるとは限らない。また、断面図では、各部材の断面構造を分かりやすくするために、一部の部材のハッチングを梨地模様に代えて示し、一部の部材のハッチングを省略している。なお、本明細書において、「平面視」とは、対象物を図1等の鉛直方向(図中上下方向)から視ることを言い、「平面形状」とは、対象物を図1等の鉛直方向から視た形状のことを言う。
配線層31は、絶縁層32の上面側において、絶縁層32に埋め込まれるように形成されている。具体的には、配線層31は、配線層31の上面と絶縁層32の上面が面一となるように、絶縁層32に埋め込まれている。配線層31の上面の一部は、配線基板30に実装される半導体素子51(図9(a)参照)が接続される部品接続端子P1として利用される。絶縁層32は、配線層31の下面及び側面を覆うように形成されている。配線層33は、絶縁層32の下面に形成されている。配線層33は、絶縁層32の下面に形成された配線パターンと、絶縁層32を貫通して配線層31に接続されたビア配線とを有している。絶縁層34は、絶縁層32の下面に、配線層33を覆うように形成されている。配線層35は、絶縁層34の下面に形成されている。配線層35は、絶縁層34の下面に形成された配線パターンと、絶縁層34を貫通して配線層33に接続されたビア配線とを有している。つまり、配線基板30は、配線層31と、絶縁層32と、配線層33と、絶縁層34と、配線層35とが順次積層された構造、所謂コアレス構造を有している。
キャリア基材20は、第1キャリア基材21、第2キャリア基材22、第3キャリア基材23を有している。
以下の説明では、各製品エリアC1を枠状に囲み、複数の製品区A1を露出する開口部21Xとして説明する。
第1キャリア基材21の側面21c及び接着層25の側面25cと第2キャリア基材22の側面22c及び接着層26の側面26cとは、離間して対向するように形成されている。第1キャリア基材21の側面21c及び接着層25の側面25cと第2キャリア基材22の側面22c及び接着層26の側面26cの間には、隙間Sが形成されている。
なお、各図の説明に必要な部材について符号を付し、説明しない部材については符号を省略する場合がある。また、説明の便宜上、最終的に半導体装置の各構成要素となる部分には、最終的な構成要素の符号を付して説明する。
第3キャリア基材23は、接着層26、27を介して第2キャリア基材22の下面22b側に接着されている。具体的には、第3キャリア基材23は、上面23aと下面23bを備えている。第3キャリア基材23の上面23aは、接着層27の下面27bと接着している。また、第3キャリア基材23の下面23bは、露出している。
図4(a)に示す工程では、支持基板121と、支持基板121の両面に積層した接着層122及び金属層123とを有する支持体120を形成する。
図8(a)に示す工程では、金属層123(図7参照)を例えばエッチングにより除去し、配線層31及び絶縁層32の上面を露出する。
図9(a)に示す工程では、キャリア基材付き配線基板10の上面に半導体素子51を部品接続端子P1に実装し、半導体素子51を封止する封止樹脂52を形成する。このとき、上述の電気検査においてマーキングされていない配線基板30、つまり良品と判定された配線基板30に対して半導体素子51を実装し、マーキングされた配線基板30、つまり不良品と判定された配線基板30に対して半導体素子51を実装しない。これにより、不良品の配線基板に対して半導体素子51を実装する無駄を省くことができる。また、不良品の配線基板に実装した半導体素子51が無駄になることを防止することができる。
配線基板30は、第1キャリア基材21が貼り付けられた状態で、電気検査へ搬送される。第1キャリア基材21は、配線基板30の製品エリアC1を露出するように形成された開口部21Xを有している。従って、第1キャリア基材21を貼り付けた状態で配線基板30の電気検査を実施することができる。
(1)キャリア基材付き配線基板10は、キャリア基材20と配線基板30とを有している。配線基板30は、配線層31と、絶縁層32と、配線層33と、絶縁層34と、配線層35とが順次積層された構造、所謂コアレス構造を有している。ソルダーレジスト層36は、絶縁層34の下面に、配線層35の一部を覆うように形成されている。ソルダーレジスト層36は、配線層35の下面の一部を外部接続端子P2として露出する開口部36Xを有している。
・上記各形態において、第1キャリア基材21の開口部21Xを、図13に示すように、製品区A1毎に形成してもよい。
20 キャリア基材
21 第1キャリア基材
21X 開口部
22 第2キャリア基材
23 第3キャリア基材
25,26,27 接着層
30 配線基板
31,33,35 配線層
32,34 絶縁層
36 ソルダーレジスト層
36X 開口部
101 基板
102 接着層(第1の接着層)
111 基板
112 接着層(第2の接着層)
A1 製品区
C1 製品エリア
P1 部品接続端子
P2 外部接続端子
Claims (8)
- 配線基板と、
前記配線基板の製品エリアを露出する開口部を有し、前記配線基板の下面に接着層を介して接着された第1キャリア基材と、
第1キャリア基材の開口部内に配置され、前記配線基板の下面に接する第2キャリア基材と、
前記第1キャリア基材の前記開口部を覆い、前記第1キャリア基材及び前記第2キャリア基材と接着層を介して接着された第3キャリア基材と、を有すること、を特徴とするキャリア基材付き配線基板。 - 前記第3キャリア基材の上面の全体に接着層が形成され、
前記第1キャリア基材は、前記第3キャリア基材の上面の接着層を介して前記第3キャリア基材に接着され、
前記第2キャリア基材は、前記第2キャリア基材の下面に形成された接着層と前記第3キャリア基材の上面の接着層とを介して前記第3キャリア基材に接着されていること、を特徴とする請求項1に記載のキャリア基材付き配線基板。 - 前記第2キャリア基材は、前記第1キャリア基材と同じ厚さであり、
前記第2キャリア基材の下面の接着層の厚さは、前記第1キャリア基材を前記配線基板に接着する接着層の厚さと同じであること、を特徴とする請求項2に記載のキャリア基材付き配線基板。 - 前記第3キャリア基材を前記第1キャリア基材に接着する接着層の接着力より弱い接着力の接着層を介して前記第1キャリア基材と前記配線基板とが接着されていること、を特徴とする請求項1〜3のいずれか1項に記載のキャリア基材付き配線基板。
- 配線基板の製品エリアに対応する開口部を有する枠状の第1キャリア基材を用意する工程と、
支持体上に配線層と絶縁層とを積層して前記配線基板を形成する工程と、
前記配線基板に前記第1キャリア基材を貼り付ける工程と、
前記支持体を除去する工程と、
前記第1キャリア基材の開口部に挿通したプローブ端子を介して前記配線基板の電気検査を行う工程と、
前記第1キャリア基材の開口部内に第2キャリア基材を配置し、前記第1キャリア基材の前記開口部を覆う第3キャリア基材を前記第1キャリア基材に貼り付ける工程と、を有するキャリア基材付き配線基板の製造方法。 - 前記第1キャリア基材を用意する工程において、1枚の基板を切断加工して前記開口部を有する前記第1キャリア基材を用意するとともに、前記開口部に対応して切断した部材を前記第2キャリア基材とすること、を特徴とする請求項5に記載のキャリア基材付き配線基板の製造方法。
- 前記第1キャリア基材を用意する工程において、一面に第1の接着層が形成された1枚の基板を切断して前記開口部を有する前記第1キャリア基材を用意するとともに、前記開口部に対応して切断した部材を前記第2キャリア基材とし、
前記第1の接着層を介して前記第1キャリア基材を前記配線基板に接着し、
一面に第2の接着層が形成された第3キャリア基材に、前記第2の接着層と前記第1の接着層を介して前記第2キャリア基材を接着し、前記第3キャリア基材を前記第2の接着層を介して前記第1キャリア基材に貼り付けること、を特徴とする請求項5に記載のキャリア基材付き配線基板の製造方法。 - 前記第3キャリア基材を前記第1キャリア基材に接着する前記第2の接着層の接着力より弱い接着力の前記第1の接着層を介して前記第1キャリア基材と前記配線基板とが接着されていること、を特徴とする請求項7に記載のキャリア基材付き配線基板の製造方法。
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US15/714,391 US9905504B1 (en) | 2016-09-30 | 2017-09-25 | Carrier base material-added wiring substrate |
KR1020170124333A KR102326846B1 (ko) | 2016-09-30 | 2017-09-26 | 캐리어 기재-부가된 배선 기판 및 캐리어 기재-부가된 배선 기판의 제조 방법 |
TW106133038A TWI741035B (zh) | 2016-09-30 | 2017-09-27 | 添加載體基材的佈線基板和製造添加載體基材的佈線基板的方法 |
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