TWI741035B - 添加載體基材的佈線基板和製造添加載體基材的佈線基板的方法 - Google Patents

添加載體基材的佈線基板和製造添加載體基材的佈線基板的方法 Download PDF

Info

Publication number
TWI741035B
TWI741035B TW106133038A TW106133038A TWI741035B TW I741035 B TWI741035 B TW I741035B TW 106133038 A TW106133038 A TW 106133038A TW 106133038 A TW106133038 A TW 106133038A TW I741035 B TWI741035 B TW I741035B
Authority
TW
Taiwan
Prior art keywords
carrier substrate
substrate
wiring
adhesive layer
carrier
Prior art date
Application number
TW106133038A
Other languages
English (en)
Other versions
TW201831062A (zh
Inventor
佐藤淳史
近藤人資
深瀬克哉
Original Assignee
日商新光電氣工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商新光電氣工業股份有限公司 filed Critical 日商新光電氣工業股份有限公司
Publication of TW201831062A publication Critical patent/TW201831062A/zh
Application granted granted Critical
Publication of TWI741035B publication Critical patent/TWI741035B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H05K3/025Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/202Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

一種添加載體基材的佈線基板包括佈線基板和第一到第三載體基材。第一載體基材藉由第一黏合層黏合至佈線基板的下表面,第一載體基材包括開口,開口將佈線基板的產品區的開口露出。第二載體基材配置於第一載體基材的開口中,並且與佈線基板的下表面接觸。第三載體基材藉由第二黏合層黏合至第一載體基材與第二載體基材。第三載體基材覆蓋第一載體基材的開口。第二黏合層完全形成在第三載體基材的上表面。

Description

添加載體基材的佈線基板和製造添加載體基材的佈線基板的 方法
本發明涉及一種添加載體基材的佈線基板和一種製造添加載體基材的佈線基板的方法。
佈線基板上裝設的半導體元件密度逐漸增加。現今需要更薄的佈線基板和密度更高的佈線圖案。已經有一種無芯佈線基板可滿足這種需求。無芯基板小於高剛性芯基板並且厚度比層間絕緣層厚。這種佈線基板在製造和組裝程序中容易產生變形而難以處理。 日本特開專利公開號2003-347459、2016-048768、以及2003-309215描述在佈線基板黏合於剛性試驗基板的狀態下,佈線基板的製造和組裝過程。
在組裝步驟中,半導體裝置裝設在佈線基板上,該佈線基板黏合至試驗基板,佈線基板的變形可能造成連接失敗、損傷或類似的狀況。因此,在組裝步驟中需要降低這種佈線基板的變形狀況。
一個實施例是添加載體基材的佈線基板,其包括佈線基板、第一載體基材、第二載體基材、以及第三載體基材。第一載體基材藉由第一黏合層黏合至佈線基板的下表面。第一載體基材包括開口將佈線基板的產品區露出。第二載體基材接觸佈線基板的下表面。第三載體基材藉由第二黏合層黏合至第一載體基材與第二載體基材。第三載體基材覆蓋第一載體基材的開口。第二黏合層完全形成在第三載體基材的上表面。
另一實施例是添加載體基材的佈線基板的製造方法。該方法包括準備第一載體基材,該第一載體基材為框狀且包括開口,該開口對應於佈線基板的產品區、在支撐主體上堆疊佈線層與絕緣層以形成該佈線基板、將第一載體基材黏合至佈線基板、移除支撐主體、在佈線基板上進行電氣測試,將探針端子插入第一載體基材的開口、以及隨著將第二載體基材配置在第一載體基材的開口,將第三載體基材黏合至第一載體基材,該第三載體基材覆蓋第一載體基材的開口。
利用上述的實施例,可減少佈線基板的變形狀況。
結合附圖,通過以下舉例說明本發明原理的描述,其他實施例和其優點將變得顯而易見。
應該理解的是,前述的一般性描述和下文的詳細描述均為示例性和說明性,而非針對本發明做出限制。
參照附圖來描述實施例。在附圖中,為了簡單和清楚而示出了元件,且不一定按比例繪製。為了便於理解,在剖面圖中,可能不會示出陰影線或用陰影替換。在本說明書中,平面圖是指主體的鳥瞰圖(例如,圖1A中垂直方向的視圖),平面形狀是指在垂直方向觀看到主體的形狀。
參照圖1A,添加載體基材的佈線基板10包括載體基材20以及佈線基板30。載體基材20黏合至佈線基板30的下表面以支撐佈線基板30。
如圖1A所示,佈線基板30包括佈線層31、絕緣層32、佈線層33、絕緣層34、佈線層35、以及阻焊層36。
佈線層31形成於絕緣層32的上表面,並且嵌入絕緣層32中。在本實例中,佈線層31的上表面與絕緣層32的上表面齊平。佈線層31的上表面的一些部分用來作為部件連接端子P1,該部件連接端子P1連接至裝設在佈線基板30上的半導體元件51(參照圖9A)。絕緣層32覆蓋佈線層31的下表面和側表面。
佈線層33形成於絕緣層32的下表面。佈線層33包括形成於絕緣層32的下表面的佈線圖案,該佈線圖案藉由佈線延伸穿過絕緣層32並與佈線層31連接。絕緣層34形成於絕緣層32的下表面並覆蓋佈線層33。佈線層35形成於絕緣層34的下表面。佈線層35包括形成於絕緣層34的下表面的佈線圖案,該佈線圖案藉由佈線延伸穿過絕緣層34並與佈線層33連接。以此方式,佈線基板30具備將佈線層31、絕緣層32、佈線層33、絕緣層34、和佈線層35依序堆疊而獲得的無芯佈線基板的結構。
阻焊層36形成於絕緣層34的下表面並且部分覆蓋佈線層35。阻焊層36包括開口36X,開口36X使佈線層35的下表面的一些部分露出,用來作為外部連接端子P2。如圖1D所示,舉例來說,開口36X可排列成矩陣狀陣列。圖1D示意性示出開口36X的排列的一個實例,但並非是對於開口36X的排列的方向與數量做出限制。
舉例來說,佈線層31、33、與35是以銅(Cu)或銅合金製成。舉例來說,絕緣層32與34是以環氧樹脂、聚酰亞胺樹脂等絕緣性樹脂製成,或是在環氧樹脂或聚酰亞胺樹脂中混合二氧化矽或氧化鋁等填充劑而獲得的樹脂製成。絕緣層32與34以絕緣樹脂製成,絕緣樹脂包含增強材料。使用主要組成成分為環氧樹脂或聚酰亞胺樹脂的熱固性樹脂來浸漬增強材料,如玻璃纖維、芳族聚酰胺纖維、或液晶聚合物(LCP)纖維的平織布或不織布而獲得絕緣樹脂。或者,絕緣層32與34可由熱固性絕緣樹脂或感光性絕緣樹脂製成。
舉例來說,阻焊層36可為感光性乾膜光阻或液體光刻膠。這種光阻材料可為例如酚醛樹脂或丙烯酸樹脂。例如,在使用感光性乾膜光阻的情況下,進行熱壓接,利用乾膜將絕緣層34和佈線層35黏合。執行光刻使乾膜圖形化並形成具有開口36X的阻焊層36。 當使用液體光刻膠時,執行相同的程序來形成阻焊層36。
當需要時,表面處理層(未示出)可在從開口36X露出的佈線層35的表面上形成。表面處理層(未圖示)的實例可包括金(Au)層、鎳(Ni)/ Au層(Ni層為底層,並在Ni層上形成Au層的金屬層)、鈀(Pd)/ Au層(Ni層為底層,Ni層、Pd層、Au層依序堆疊的金屬層)。或者,經由諸如有機可焊性防腐劑(OSP)抗氧化處理過的表面處理層可形成於從開口36X露出的佈線層35的表面上。
現在將敘述載體基材20。載體基材20包括第一載體基材21、第二載體基材22、以及第三載體基材23。。
參照圖1A與1B,第一載體基材21藉由黏合層25黏合至佈線基板30的下表面,在本實例中,是黏合至阻焊層36的下表面36b。在圖1B中,為了便於理解第一載體基材21,將第二載體基材22與第三載體基材23從第一載體基材21分離出來。
參照圖2A,工作基板40是包括多個(在圖2A中為6個)產品區C1(由虛線形成的長方形)的大型基板。在稍後將敘述的片狀切割步驟中切割工作基板40,以形成數個(在圖2B中為3個)載體基材10。在本實施例中,直至片狀切割步驟前的每個製造步驟都與處於圖2A狀態中的工作基板40一起執行。如圖2C所示,舉例來說,本實施例的添加載體基材的佈線基板10為片狀基板。每個添加載體基材的佈線基板10在平面圖中為長方形。添加載體基材的佈線基板10包括多個(在圖2C中為2個)產品區C1。產品區C1彼此分離。每個產品區C1包括呈矩陣式陣列的多個產品部份A1。在每個產品部份A1上裝設半導體元件並形成封裝樹脂。之後,移除圖1A所示的載體基材20。沿著每個產品部份A1周圍延伸的實線,切割片狀基板以將圖10B中示出的多個半導體裝置(半導體封裝)獨立出來。圖1A是沿著圖2C的剖面線1a-1a的剖面示意圖。
參照圖1A與1B,第一載體基材21為框狀並包含開口21X,每個開口21X都對應於佈線基板30中的一個產品區C1。每個開口21X將與其對應的產品區C1的產品部分A1露出。因此,第一載體基材21的每個開口21X將佈線基板30的外部連接端子P2以及阻焊層36的下表面36b的一些部分露出。佈線基板30的產品部分A1是封裝佈線基板30上裝設的半導體元件並接著獨立出半導體裝置(半導體封裝)的區域。
參照圖1C,第一載體基材21包括上表面21a、下表面21b、以及側表面21c。第一載體基材21的上表面21a黏合至黏合層25。第一載體基材21的下表面21b黏合至黏合層27的上表面27a的周緣部。黏合層27的上表面27a的周緣部在佈線基板30的產品區C1外圍的區域中。
黏合層25包括上表面25a、下表面25b、以及側表面25c。在佈線基板30的產品區C1外側,黏合層25的上表面25a黏合至阻焊層36的下表面36b。黏合層25的下表面25b接觸第一載體基材21的上表面21a。黏合層25包括開口25X,每個開口25X都對應於佈線基板30中的一個產品區C1。為了簡潔起見,第一載體基材21的開口21X與黏合層25的開口25X將一起統稱為第一載體基材21的開口21X,而不會描述開口25X。
第一載體基材21的側表面21c與黏合層25的側表面25c齊平。此外,側表面21c與25c構成開口21X與25X的輪廓。換句話說,在平面圖中,第一載體基材21與黏合層25具有相同形狀。
第二載體基材22位於第一載體基材21的開口21X(第一載體基材21的開口21X與黏合層25的開口25X)之中。第二載體基材22包括上表面22a、下表面22b、以及側表面22c。在佈線基板30的產品區C1中,第二載體基材22的上表面22a直接接觸阻焊層36的下表面36b。第二載體基材22的上表面22a接觸阻焊層36的下表面36b,但第二載體基材22的上表面22a沒有黏合至下表面36b。換句話說,第二載體基材22與佈線基板30(意即,阻焊層36)之間並無存在黏合層。第二載體基材22的下表面22b黏合至黏合層26。舉例來說,第二載體基材22的厚度設定為與第一載體基材21的厚度相等。第二載體基材22藉由黏合層26與27黏合至第三載體基材23上表面23a。
黏合層26包括上表面26a、下表面26b、以及側表面26c。黏合層26的上表面26a黏合至第二載體基材22的下表面22b。第二載體基材22的下表面22b黏合至黏合層27(佈線基板30的每個產品區C1之中)的上表面27a的中間部。
第二載體基材22的側表面22c與黏合層26的側表面26c齊平。換句話說,在平面圖中,第二載體基材22與黏合層26具有相同形狀。
第一載體基材21的側表面21c與黏合層25的側表面25c間隔於且朝向第二載體基材22的側表面22c與黏合層26的側表面26c。側表面21c與25c以間隙S間隔於側表面22c與26c。
第三載體基材23覆蓋第一載體基材21的開口21X(第一載體基材21的開口21X與黏合層25的開口25X)。第三載體基材23藉由黏合層27黏合至第一載體基材21的下表面21b。此外,第三載體基材23藉由黏合層26與27黏合至第二載體基材22的下表面22b。第三載體基材23包括上表面23a、以及下表面23b。第三載體基材23的上表面23a黏合至黏合層27的下表面27b。第三載體基材23的下表面23b外露。舉例來說,第三載體基材23的厚度設定為與第一載體基材21以及第二載體基材22的厚度相等。
黏合層27包括上表面27a與下表面27b。黏合層27的上表面27a包括中間部與周緣部。在對應於佈線基板30的產品區C1的區域中,上表面27a的中間部黏合至黏合層26。在佈線基板30的產品區C1外圍的區域中,上表面27a的周緣部黏合至第一載體基材21的下表面21b。黏合層27的下表面27b黏合至第三載體基材23的上表面23a。
載體基材21可以是例如核心基板、金屬箔、或膜。核心基板的一個例子是玻璃環氧樹脂基板,其為增強材料與浸漬在增強材料中的熱固性樹脂的硬化產物的複合物。增強材料例如是玻璃布(平織玻璃布)、不織玻璃布、平織芳族聚酰胺布、不織芳族聚酰胺布,平織液晶聚合物(LCP)布、或不織LCP布。 熱固性絕緣樹脂例如是環氧樹脂、聚酰亞胺樹脂、或氰酸酯樹脂。金屬箔可由例如銅或不銹鋼製成。膜可由例如環氧樹脂、酚醛樹脂、或聚酰亞胺樹脂製成。
形成第二載體基材22的材料可從第一載體基材21的材料實例中選擇。以相同的方法,形成第三載體基材23的材料可從第一載體基材21的材料實例中選擇。舉例來說,可利用被紫外線照射後黏合力會降低的材料來形成黏合層25。以相同的方法,舉例來說,可利用被紫外線照射後黏合力會降低的材料來形成黏合層26。黏合層27的材料比起黏合層25與26具有更強的黏合力。
本實施例中,形成第二載體基材22的材料與形成第一載體基材21的材料相同。第二載體基材22與第一載體基材21的厚度相等。此外,黏合層26與黏合層25的厚度相等。
現在開始描述製造添加載體基材的佈線基板10的方法步驟。在以下的敘述中,附圖中只有將被描述到的元件才加上標號。此外,為了便於理解,附圖中使用的標號與用於半導體裝置的最終元件的標號相符合。
以下的敘述中,敘述添加載體基材的佈線基板10的製造步驟將參照沿著圖2C中剖面線1a-1a的放大剖面圖。在一些情況下,說明書中將參照圖2A示出的工作基板40。
圖3A中的步驟中,準備兩個基板101與111。基板101與111都與圖2A所示的工作基板40具有相同尺寸。黏合層102形成於基板101的上表面。舉例來說,基板101可以是例如核心基板、金屬箔、或膜。舉例來說,可利用被紫外線照射後黏合力會降低的材料來形成黏合層102。
黏合層112形成於基板111的上表面。舉例來說,基板111可以是例如核心基板、金屬箔、或膜。黏合層112的材料比起黏合層102具有更強的黏合力。
圖3B的步驟中,切割基板101以形成圖3B與11A示出的第一載體基材21(用於佈線基板30的產品區C1外圍),以及圖3B與11B示出的第二載體基材22(用於佈線基板30的產品區C1中)。圖11A至11D是圖3A至3C中第一至第三載體基材21至23的形成與使用步驟的示意平面圖。
可以藉由例如CO2 雷射器或YAG雷射器進行雷射鑽孔以切割基板101。雷射鑽孔沿著產品區C1的周緣切割基板101以獲得第一載體基材21以及第二載體基材22,該第一載體基材21包括開口21X。此外,將黏合層102與基板101一起切割以獲得黏合層25以及黏合層26,該黏合層25形成在第一載體基材21的上表面,該黏合層26形成在第二載體基材22的上表面。第一載體基材包括上表面21a、下表面21b、以及側表面21c。第一載體基材21的上表面21a黏合至黏合層25。第一載體基材21包括開口21X,該開口21X在對應於佈線基板30的產品區C1的區域中開放。
黏合層25的下表面25b黏合至第一載體基材21的上表面21a。黏合層25包括開口25X,該開口25X在對應於佈線基板30的產品區C1的區域中開放。
第一載體基材21的側表面21c與黏合層25的側表面25c齊平。側表面21c與25c構成開口21X與25X的輪廓。換句話說,第一載體基材21與黏合層25在平面圖中具有相同形狀。圖3B示出的第二載體基材22與黏合層26在圖3C中的步驟中為相互顛倒。
參照圖1A,第二載體基材22配置於第一載體基材21的開口21X中。如此一來,如圖3B所示,基板101對應於開口21而被切割分為第一載體基材21與第二載體基材22,因此該材料(基板101與黏合層102)的使用上不會有任何浪費。
圖3C與11D的步驟中,第二載體基材22黏合至圖3A與11C所示的基板111。本實例中,位於第二載體基材22的表面(圖3C中為下表面)上的黏合層26直接朝向基板111的黏合層112。接著第二載體基材22藉由黏合層26與112黏合至基板111。基板111對應於第三載體基材23,且黏合層112對應於黏合層27。在佈線基板30的產品區C1中,第二載體基材22的上表面22a直接接觸阻焊層36的下表面36b。第二載體基材22的下表面22b黏合至黏合層26。第二載體基材22藉由黏合層26與27黏合至第三載體基材23的上表面23a。
黏合層26的上表面26a黏合至第二載體基材22的下表面22b。在對應於佈線基板30的產品區C1的區域中,黏合層26的下表面26b黏合至黏合層27的上表面27a的中間部。
第二載體基材22的側表面22c與黏合層26的側表面26c齊平。換句話說,在平面圖中,第二載體基材22與黏合層26具有相同形狀。
第三載體基材23藉由黏合層26與27黏合至第二載體基材22的下表面22b。第三載體基材23的上表面23a黏合至黏合層27的下表面27b。第三載體基材23的下表面23b外露。
黏合層27的上表面27a包括中間部與周緣部。在對應於佈線基板30的產品區C1的區域中,該中間部黏合至黏合層26。在佈線基板30的產品區C1的外圍區域中,該周緣部外露。在隨後的步驟中,上表面27a的周緣部黏合至第一載體基材21的下表面21b。黏合層27的下表面27b黏合至第三載體基材23的上表面23a。
現在將描述佈線基板30的製造步驟。
在圖4A的步驟中,形成了支撐主體120。支撐主體120包括支撐基板121、黏合層122、以及金屬層123。黏合層122與金屬層123形成在支撐基板121的相反表面。
支撐基板121可為例如藉由利用環氧樹脂等浸漬玻璃布(平織布)、不織玻璃布、或芳族聚酰胺纖維製成的構件。每個黏合層122可以是金屬箔,例如銅箔、鋁箔、鎳箔、或鋅箔;陶瓷板;或其主要成分是諸如丙烯酸或聚酰亞胺的樹脂的樹脂片。每個金屬層123可為例如銅箔等。
圖4B的步驟中 在支撐主體120的每個表面的金屬層123上形成佈線基板30。佈線基板30具備佈線層31、絕緣層32、佈線層33、絕緣層34、以及阻焊層36。佈線層31、絕緣層32、佈線層33、絕緣層34、以及阻焊層36依序堆疊在金屬層123上以形成佈線基板30。
首先在每個金屬層123上形成佈線層31。使用各種類型的佈線形成程序,如半加成程序來形成佈線層31。 例如,在金屬層123的表面上的特定位置處形成具有開口的光阻層。在對應於佈線層31的一些部分,開口將金屬層123露出。光阻層可以是感光性乾膜光阻或液體光刻膠。這種光刻膠可為例如酚醛樹脂或丙烯酸樹脂。 然後,使用光阻層作為遮罩並使用金屬層123作為電鍍供電層來執行電解電鍍(電解銅電鍍),在金屬層123上形成佈線層31。然後,利用例如鹼分層液將光阻層移除。
位於金屬層123的上表面的佈線層31被熱固性環氧樹脂或之類的絕緣樹脂層覆蓋且層壓以形成絕緣層32。可以施加絕緣樹脂的液體或糊劑,如熱固性環氧樹脂,並使其硬化而形成絕緣層32。接著形成穿過絕緣層32而延伸的通孔使佈線層31的一些部分露出。可藉由例如CO2 雷射等進行雷射鑽孔以形成通孔。必要時也可進行除污程序。
接著形成佈線層33。可藉由例如半加成程序形成佈線層33。例如執行像是無電電鍍,首先在絕緣層32的上表面形成種子層。然後,在種子層上的指定位置處形成具有開口的光阻層。如上所述,光阻層可以是感光性乾膜光阻或液體光刻膠(例如酚醛樹脂或丙烯酸樹脂)。接下來使用光阻層作為遮罩,並且使用種子層作為電鍍電力供給層來執行電解電鍍(電解銅電鍍)以形成電解電鍍層。使用例如鹼性分層液移除光阻層之後,使用電解電鍍層作為蝕刻遮罩,進行蝕刻來移除不需要的種子層部分。這就形成了佈線層33。
接著,重複形成絕緣層32和形成佈線層33的相同步驟來形成絕緣層34和佈線層35。以此方式,將指定數量的佈線層和絕緣層依序交替堆疊以形成佈線結構。
然後,具有開口36X的阻焊層36形成於佈線層35與絕緣層34的上表面。舉例來說,藉由將感光性樹脂膜層壓於佈線層35和絕緣層34的上表面,或藉由在佈線層35層壓和絕緣層34的上表面施加樹脂液體或糊劑以形成阻焊層36。在光刻程序中進行曝光和顯影將樹脂圖案化,形成特定形狀。佈線層35的上表面的一些部分從開口36X露出用來作為外部連接端子P2。
圖5的步驟中,每個第一載體基材21藉由黏合層25黏合至阻焊層36的表面(圖1A中為下表面36b)。在本實例中,在產品區C1外側,第一載體基材21藉由黏合層25黏合至阻焊層36的下表面36b,因此該產品區C1位於該第一載體基材21的開口21X中,也就是說,因此第一載體基材21包圍產品區C1。
圖6的步驟中,保護膜132藉由黏合層131黏合至第一載體基材21的表面(圖1A中為下表面21b)。該保護膜132封閉第一載體基材21的開口21X。舉例來說,可利用被紫外線照射後黏合力會降低的材料來製成黏合層131。可利用對後續步驟中執行的蝕刻具有抵抗性的材料形成保護膜132。例如,保護膜132可由感光性乾膜(例如酚醛樹脂或丙烯酸樹脂)形成。
圖7的步驟中,從圖6中所示的支撐基板121分離出兩個佈線基板30。當每個佈線基板30從支撐基板121分離後,每個佈線基板30被第一載體基材21支撐。
圖8A的步驟中,藉由例如蝕刻來移除金屬層123(參照圖7),使佈線層31與絕緣層32的上表面露出。
圖8B的步驟中,執行片狀切割以形成添加載體基材的佈線基板10。接著,保護膜132被移除而露出外部連接端子P2。此外,在添加載體基材的佈線基板10所包含的佈線基板30上進行電氣檢驗。也就是說,在片狀添加載體基材的佈線基板10(參照圖2C)中的每個產品部分A1的佈線結構上進行電氣測試。
在切割圖2A所示的工作基板40之後,在片狀添加載體基材的佈線基板10上進行該電氣測試,並且形成圖2B所示的添加載體基材的佈線基板10。
參照圖8B,在片狀添加載體基材的佈線基板10上進行電氣測試。本實例中,在佈線基板30的上表面,探針端子T1接觸部件連接端子P1,且在佈線基板30的下表面,探針端子T2接觸外部連接端子P2。利用探針端子T1與T2在佈線基板30上進行各種電氣測試(開路測試,短路測試等)。
佈線基板30被載體基材21支撐。這使得利用測試裝置執行電氣測試時便於處理(支撐)佈線基板30。 載體基材21具有開口21X使佈線基板30的外部連接端子P2露出。因此,測試探針端子T2能夠容易地接觸附著於載體基材21的佈線基板30中的外部連接端子P2,而進行電氣測試。
藉由上述的電氣測試判定每個產品部分A1中的佈線基板30是否有缺陷。根據判定結果,在佈線基板30上標記。舉例來說,當確定有缺陷時,在佈線基板30上標記指定記號。
圖8C的步驟中,第二載體基材22配置於第一載體基材21的開口21X中,且第三載體基材23黏合至第一載體基材21。以此方式,佈線基板30被載體基材20支撐。本實例中,在佈線基板30的產品區C1中,第二載體基材22的上表面22a直接接觸阻焊層36的下表面36b。第二載體基材22的上表面22a接觸阻焊層36的下表面36b,而非黏合至下表面36b。換句話說,第二載體基材22與佈線基板30(意即,阻焊層36)之間並無配置黏合層。在第三載體基材23的周緣部,第一載體基材21的下表面21b黏合至黏合層27的上表面27a。
第一載體基材21的側表面21c與黏合層25的側表面25c間隔於並朝向第二載體基材22的側表面22c與黏合層26的側表面26c。側表面21c與25c以間隙S間隔於側表面22c與26c。
現在將描述使用添加載體基材的佈線基板10的半導體裝置的製造步驟。
在圖9A的步驟中,在添加載體基材的佈線基板10的上表面,半導體元件51連接到部件連接端子P1。接著形成封裝樹脂52以密封半導體元件51。此時,當佈線基板30沒有在電氣測試中被標記,也就是說,當佈線基板30已被判定為無缺陷,在佈線基板30上裝設半導體元件51。當佈線基板30已被標記,也就是說,當佈線基板30已被判定為有缺陷,就不在佈線基板30上裝設半導體元件51。因此,不需要花時間在有缺陷的佈線基板上裝設半導體元件51。這也避免半導體元件51裝設在有缺陷的佈線基板上而造成半導體元件51浪費。
封裝樹脂52覆蓋半導體元件51以及佈線基板30的上表面。舉例來說,封裝樹脂52是由熱固性環氧絕緣樹脂製成。絕緣樹脂並非必須為熱固性,也可以是感光性。
圖9B的步驟中,移除載體基材20。舉例來說,使用紫外線照射黏合層25,該黏合層25將圖9A所示的第一載體基材21黏合至佈線基板30,使黏合層25的黏性降低,並移除載體基材20。
圖10A的步驟中,凸塊61形成於外部連接端子P2上,用以將外部連接端子P2裝設於另一基板。舉例來說,凸塊61是焊料凸塊。可藉由配置在外部連接端子P2上的焊球或施加在外部連接端子P2後經過回焊程序的焊膏來形成凸塊61。
圖10B的步驟中,從圖10A的結構中獨立出半導體裝置70。使用切割刀片等圍繞著產品部分A1而切割圖10A所示的佈線基板30和封裝樹脂52,而獨立出半導體裝置70。
現在將描述添加載體基材的佈線基板10的操作。
在第一載體基材21黏合至佈線基板30的狀態下,對佈線基板30進行電氣測試。第一載體基材21包括開口21X將佈線基板30的產品區C1露出。如此一來,即使當第一載體基材21黏合至佈線基板30,電氣測試仍可在佈線基板30上進行。
如上所述,佈線基板30在運輸時會被第一載體基材21支撐。第一載體基材21限制佈線基板30的變形或其他類似狀況。如此一來,被第一載體基材21支撐的佈線基板30可被運輸至裝設有半導體元件的裝置。然而,在這種狀態下,半導體元件的裝設是很困難的。
圖12A與12B示出將半導體元件51裝設在只被第一載體基材21支撐的佈線基板30上的組裝步驟。圖12A與12B示出第一載體基材21包括開口21X,該開口21X將具有單一產品部分A1的產品區C1露出,半導體元件51被容設裝置支撐,且半導體元件51裝設於佈線基板30。此時,佈線基板30的產品區C1從第一載體基材21的開口21X露出。如此一來,當裝設半導體元件51時,施加的壓力會使佈線基板30變形。當佈線基板30變形,靠近半導體元件51的中間部的端子51a則不容易接觸到佈線基板30的部件連接端子P1。這可能會造成不良連接。此外,佈線基板30的變形可能在佈線基板30中會產生裂紋或造成佈線層的破損。
有鑑於此,在本實施例的添加載體基材的佈線基板10之中,佈線基板30被第二載體基材22與第三載體基材23支撐,該第二載體基材22位於第一載體基材21的開口21X中,且第三載體基材23被第一與第二載體基材21與22支承。因此,即使在佈線基板30上裝設半導體元件51會在佈線基板30上施加壓力,佈線基板30也能免於變形。也就是說,第二與第三載體基材22與23限制了佈線基板30的變形。如此,半導體元件51的端子51a能正確地連接至佈線基板30的部件連接端子P1,並且減少不良連接。此外,限制佈線基板30的變形可減少佈線基板30上的裂紋以及佈線破損。
本實施例的優點詳列於下述。
(1)添加載體基材的佈線基板10包括載體基材20與佈線基板30。佈線基板30具有無芯佈線基板結構,其中佈線層31、絕緣層32、佈線層33、絕緣層34、以及佈線層35依序堆疊。阻焊層36形成於絕緣層34的下表面以覆蓋佈線層35的一些部分。阻焊層36包括開口36X,該開口36X露出佈線層35的一些部分用來作為外部連接端子P2。
載體基材20包括第一載體基材21、第二載體基材22、以及第三載體基材23,該第一載體基材21黏合至佈線基板30,該第二載體基材22配置於第一載體基材21的開口21X之中,第三載體基材23黏合至第一與第二載體基材21與22。載體基材20讓處理具有無芯結構的佈線基板30變得容易。
(2)第一載體基材21包括開口21X,該開口21X露出佈線基板30的產品區C1。當對佈線基板30進行電氣測試時,測試探針端子T2插入第一載體基材21的開口21X以接觸佈線基板30的外部連接端子P2。以此方式,第一載體基材21的每個開口21X將佈線基板30的外部連接端子P2露出,並且在第一載體基材21支撐佈線基板30的狀態下,在佈線基板30上進行電氣測試。
(3)進行電氣測試之後,第二載體基材22配置於第一載體基材21的開口21X中,且第三載體基材23黏合至第一載體基材21。因此,當半導體元件51裝設在佈線基板30上,佈線基板30被第二載體基材22與第三載體基材23支撐,該第二載體基材22配置於第一載體基材21的開口21X中,該第三載體基材23被第一與第二載體基材21與22支承。因此,即使將半導體元件51裝設於佈線基板30時會在佈線基板30上施加壓力,佈線基板30的變形程度也有限。如此一來,半導體元件51可正確地連接至佈線基板30的部件連接端子P1,而減少不良連接的狀況。
(4)第二載體基材22的上表面22a直接接觸佈線基板30,而該上表面22a與該佈線基板30之間並無配置黏合層。如此一來,移除載體基材20的時候,外部連接端子P2與佈線基板30的阻焊層36上不會留著黏合層的殘餘物。
(5)第一載體基材21藉由黏合層25黏合至佈線基板30的下表面,也就是阻焊層36的下表面36b。第三載體基材23藉由黏合層27黏合至第一載體基材21。黏合層27的黏合力比黏合層25的黏合力強。如此一來,移除載體基材20的時候,第一與第三載體基材21與23會一起被移除,因為黏合層27具有較強的黏合力,讓第一載體基材21與第三載體基材23保持黏合。以此方式,容易將第一載體基材21與第三載體基材23一起移除。
(6)在佈線基板30上用於進行電氣測試的探針端子T2通過第一載體基材21的開口21X而接觸佈線基板30的外部連接端子P2,該第一載體基材21黏合至佈線基板30。當載體基材不具備開口21X時,為了在佈線基板30上進行電氣測試,必須先從佈線基板30上將載體基材移除,之後再重新將載體基材黏合至佈線基板30。本實施例中的添加載體基材的佈線基板,第一載體基材21包括開口21X。如此一來,就不需要先移除載體基材,然後再將載體基材重新黏合回去。這減少了製造步驟,並縮短了製造時間。
對於本領域的技術人員來說顯而易見的是,在不脫離本發明範圍的情況下,能夠以許多其他的具體形式利用前述實施例。特別應該理解,能以下面的形式利用前述實施例。
上述實施例中,第一載體基材21的開口21X是針對圖13所示的每個產品部分A1而形成。
上述實施例中,添加載體基材的佈線基板10中具有的產品區C1(參考圖2C)數量和每個產品區C1中具有的產品部分A1數量都可做改變。 此外,工作基板40(參考圖2A)中具有的產品區C1數量,也就是可改變從工作基板40形成而來的添加載體基材的佈線基板10的數量。
上述實施例中,佈線基板30中的絕緣層和佈線層的數量可做改變。
本文所述的所有示例和條件語言旨在用於教學目的,以幫助讀者理解本發明的原理以及發明人為了促進本領域而貢獻的概念,並且將被解釋為不限於此類特定所述實施例和條件,本說明書中這些實施例的組織也不涉及本發明的優缺點的說明。雖然已詳細描述了實施例,但是應當理解,在不脫離本發明範圍的情況下,可以進行各種改變、替換和更改。
10‧‧‧添加載體基材的佈線基板20‧‧‧載體基材21‧‧‧第一載體基材21a‧‧‧上表面21b‧‧‧下表面21c‧‧‧側表面21X‧‧‧開口22‧‧‧第二載體基材22a‧‧‧上表面22b‧‧‧下表面22c‧‧‧側表面22X‧‧‧開口23‧‧‧第三載體基材23a‧‧‧上表面23b‧‧‧下表面25‧‧‧黏合層25X‧‧‧開口26‧‧‧黏合層26a‧‧‧上表面26b‧‧‧下表面26c‧‧‧側表面26X‧‧‧開口27‧‧‧黏合層27a‧‧‧上表面27b‧‧‧下表面30‧‧‧佈線基板31‧‧‧佈線層32‧‧‧絕緣層33‧‧‧佈線層34‧‧‧絕緣層35‧‧‧佈線層36‧‧‧阻焊層36b‧‧‧下表面36X‧‧‧開口40‧‧‧工作基板51‧‧‧半導體元件52‧‧‧封裝樹脂61‧‧‧凸塊70‧‧‧半導體裝置111‧‧‧基板112‧‧‧基板120‧‧‧支撐主體121‧‧‧支撐基板122‧‧‧黏合層123‧‧‧金屬層131‧‧‧黏合層132‧‧‧保護層C1‧‧‧產品區A1‧‧‧產品部分P1‧‧‧部件連接端子P2‧‧‧外部連接端子S‧‧‧間隙T1‧‧‧探針端子T2‧‧‧探針端子
參考以下針對較佳實施例的描述以及附圖,最能理解實施例及其目的和優點,其中:
圖1A與1B是添加載體基材的佈線基板的示意剖面圖;
圖1C是圖1A的添加載體基材的佈線基板的部分放大剖面圖;
圖1D是阻焊層中開口的示意平面圖;
圖2A是工作基板的示意平面圖;
圖2B是片狀添加載體基材的佈線基板的示意平面圖;
圖2C是添加載體基材的佈線基板的產品區與產品部分的示意平面圖;
圖3A到3C是添加載體基材的佈線基板的製造步驟的示意剖面圖;
圖4A、4B、5到7、8A到8C、9A、9B、10A、與10B是添加載體基材的佈線基板的製造步驟的示意剖面圖;
圖11A到11D是載體基材的製造步驟的示意平面圖;
圖12A與12B示出容設於添加載體基材的比較實例上的半導體元件的組裝步驟的示意剖面圖;以及
圖13是另一添加載體基材的佈線基板的剖面圖。
20:載體基材
21:第一載體基材
21X:開口
22:第二載體基材
23:第三載體基材
25:黏合層
25X:開口
26:黏合層
27:黏合層
30:佈線基板
36:阻焊層
36b:下表面
A1:產品部分
P2:外部連接端子

Claims (11)

  1. 一種添加載體基材的佈線基板,包括:佈線基板;第一載體基材,該第一載體基材藉由第一黏合層黏合至該佈線基板的下表面,其中該第一載體基材包括開口,該開口使該佈線基板的產品區露出;第二載體基材,該第二載體基材配置於該第一載體基材的開口中,其中該第二載體基材接觸該佈線基板的下表面;以及第三載體基材,該第三載體基材藉由第二黏合層黏合至該第一載體基材與該第二載體基材,其中該第三載體基材覆蓋該第一載體基材的開口。
  2. 根據申請專利範圍1所述之添加載體基材的佈線基板,其中:該第二黏合層完全形成在該第三載體基材的上表面;該第二載體基材包括上表面與下表面,該下表面位於該上表面的相反側;該第二載體基材的上表面接觸該佈線基板的下表面;於該第二載體基材的下表面形成有第三黏合層;該第三黏合層黏合至該第二黏合層;以及該第二載體基材藉由該第二黏合層與該第三黏合層黏合至該第三載體基材。
  3. 根據申請專利範圍2所述之添加載體基材的佈線基板,其中;該第二載體基材的厚度與該第一載體基材的厚度相等,以及 該第三黏合層的厚度與該第一黏合層的厚度相等。
  4. 根據申請專利範圍1至3中任一所述之添加載體基材的佈線基板,其中該第一黏合層的黏合力比該第二黏合層的黏合力弱。
  5. 根據申請專利範圍1至3中任一所述之添加載體基材的佈線基板,其中:該佈線基板包括多個佈線層、多個絕緣層、以及阻焊層,其中該阻焊層堆疊在最下面一個絕緣層的下表面,該阻焊層將最下面一個佈線層部分露出作為外部連接端子;該第一載體基材藉由該第一黏合層黏合至該阻焊層的下表面;以及在該第一載體基材的開口中,該第二載體基材的上表面直接接觸該阻焊層的下表面。
  6. 根據申請專利範圍2或3所述之添加載體基材的佈線基板,其中:在平面圖中該第一載體基材與該第一黏合層具有相同形狀;以及在平面圖中該第二載體基材與該第三黏合層具有相同形狀。
  7. 根據申請專利範圍6所述之添加載體基材的佈線基板,其中:該第一載體基材的側表面與該第一黏合層的側表面間隔於且朝向該第二載體基材的側表面與該第三黏合層的側表面。
  8. 一種製造添加載體基材的佈線基板的方法,該方法包括: 準備第一載體基材,該第一載體基材為框狀且包括開口,該開口對應佈線基板的產品區;在支撐主體上堆疊佈線層與絕緣層以形成該佈線基板;將該第一載體基材黏合至該佈線基板;移除該支撐主體;藉由插入該第一載體基材的開口中的探針端子在該佈線基板上進行電氣測試;以及隨著將第二載體基材配置於該第一載體基材的開口中,將第三載體基材黏合至該第一載體基材,該第三載體基材覆蓋該第一載體基材的開口。
  9. 根據申請專利範圍8所述之方法,其中準備第一載體基材的該步驟包括切割單一基板以形成包括該開口的該第一載體基材,以及獲得由切割該單一基板而分離出來的構件,該構件與該開口符合一致而用來作為該第二載體基材。
  10. 根據申請專利範圍8所述之方法,其中:準備第一載體基材的該步驟包括準備單一基板,該單一基板包括第一黏合層,該第一黏合層形成在該單一基板的一個表面上,切割該單一基板與該第一黏合層,以獲得包括該開口的該第一載體基材,以及獲得由切割該單一基板而分離出來的構件,該構件與該開口符合一致而用來作為該第二載體基材; 將該第一載體基材黏合至該佈線基板的該步驟包括將該第一載體基材藉由該第一黏合層黏合至該佈線基板;以及該方法還包括:準備第三載體基材,該第三載體基材包括第二黏合層,該第二黏合層形成在該第三載體基材的一個表面上;將該第二載體基材藉由該第一黏合層與該第二黏合層黏合至該第三載體基材;以及將該第三載體基材藉由該第二黏合層黏合至該第一載體基材。
  11. 根據申請專利範圍10所述之方法,其中該第一黏合層的黏合力比該第二黏合層的黏合力弱。
TW106133038A 2016-09-30 2017-09-27 添加載體基材的佈線基板和製造添加載體基材的佈線基板的方法 TWI741035B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016192806A JP6693850B2 (ja) 2016-09-30 2016-09-30 キャリア基材付き配線基板、キャリア基材付き配線基板の製造方法
JP??2016-192806 2016-09-30

Publications (2)

Publication Number Publication Date
TW201831062A TW201831062A (zh) 2018-08-16
TWI741035B true TWI741035B (zh) 2021-10-01

Family

ID=61225980

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106133038A TWI741035B (zh) 2016-09-30 2017-09-27 添加載體基材的佈線基板和製造添加載體基材的佈線基板的方法

Country Status (4)

Country Link
US (1) US9905504B1 (zh)
JP (1) JP6693850B2 (zh)
KR (1) KR102326846B1 (zh)
TW (1) TWI741035B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7359531B2 (ja) * 2018-06-07 2023-10-11 新光電気工業株式会社 配線基板、配線基板の製造方法及び半導体パッケージの製造方法
CN116895636B (zh) * 2023-09-11 2024-01-12 芯爱科技(南京)有限公司 封装基板及其制法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347459A (ja) * 2002-05-27 2003-12-05 Nec Corp 半導体装置搭載基板とその製造方法およびその基板検査法、並びに半導体パッケージ
JP2004111536A (ja) * 2002-09-17 2004-04-08 Nec Electronics Corp 多層配線基板の製造方法
TWI504328B (zh) * 2008-04-02 2015-10-11 Gen Electric 製造可卸式互連結構的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02295194A (ja) * 1989-05-09 1990-12-06 Nec Corp パターンショート検査治具
JP3773896B2 (ja) 2002-02-15 2006-05-10 Necエレクトロニクス株式会社 半導体装置の製造方法
JP5025399B2 (ja) * 2007-09-27 2012-09-12 新光電気工業株式会社 配線基板及びその製造方法
US20150041205A1 (en) * 2013-08-06 2015-02-12 Kinsus Interconnect Technology Corp. Thin package structure with enhanced strength
JP2016048768A (ja) 2014-08-28 2016-04-07 日立化成株式会社 配線板及び半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347459A (ja) * 2002-05-27 2003-12-05 Nec Corp 半導体装置搭載基板とその製造方法およびその基板検査法、並びに半導体パッケージ
JP2004111536A (ja) * 2002-09-17 2004-04-08 Nec Electronics Corp 多層配線基板の製造方法
TWI504328B (zh) * 2008-04-02 2015-10-11 Gen Electric 製造可卸式互連結構的方法

Also Published As

Publication number Publication date
US9905504B1 (en) 2018-02-27
JP6693850B2 (ja) 2020-05-13
KR102326846B1 (ko) 2021-11-17
JP2018056445A (ja) 2018-04-05
KR20180036569A (ko) 2018-04-09
TW201831062A (zh) 2018-08-16

Similar Documents

Publication Publication Date Title
US7939377B1 (en) Method of manufacturing semiconductor element mounted wiring board
US6696764B2 (en) Flip chip type semiconductor device and method of manufacturing the same
KR101342031B1 (ko) 다층 배선 기판 및 그 제조 방법
TWI442860B (zh) 佈線板及其製造方法
KR20090056824A (ko) 배선 기판 및 전자 부품 장치
KR20160026710A (ko) 배선 기판 및 배선 기판의 제조 방법
JP2006049424A (ja) 電子部品内蔵基板およびその製造方法
JP2009032918A (ja) 配線基板及びその製造方法と電子部品装置及びその製造方法
US10271430B2 (en) Printed wiring board having support plate and method for manufacturing printed wiring board having support plate
KR20110002807A (ko) 반도체칩 및 포스트를 밀봉하는 밀봉층을 구비하는 반도체장치 및 반도체장치의 제조방법
US10256175B2 (en) Printed wiring board and method for manufacturing printed wiring board
WO2009020240A2 (en) Semiconductor device and method for manufacturing the same
TWI741035B (zh) 添加載體基材的佈線基板和製造添加載體基材的佈線基板的方法
TWI767939B (zh) 添加載體基材的佈線基板和製造添加載體基材的佈線基板的方法
US10874018B2 (en) Printed wiring board having embedded pads and method for manufacturing the same
JP7359531B2 (ja) 配線基板、配線基板の製造方法及び半導体パッケージの製造方法
TWI685935B (zh) 半導體裝置及其製造方法
US20180054891A1 (en) Printed wiring board and method for manufacturing printed wiring board
JP2009081367A (ja) 半導体装置およびその製造方法
JP2008141041A (ja) 多層配線基板の製造方法
JP4663172B2 (ja) 半導体装置の製造方法
JP2009043858A (ja) 半導体装置およびその製造方法
JP2019079878A (ja) プリント配線板と支持体との組立体およびその製造方法
JP2019079869A (ja) プリント配線板と支持体との組立体およびその製造方法
JP2019079874A (ja) プリント配線板と支持体との組立体およびその製造方法