TWI548055B - 堆疊封裝元件及其製作方法 - Google Patents

堆疊封裝元件及其製作方法 Download PDF

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Publication number
TWI548055B
TWI548055B TW102113900A TW102113900A TWI548055B TW I548055 B TWI548055 B TW I548055B TW 102113900 A TW102113900 A TW 102113900A TW 102113900 A TW102113900 A TW 102113900A TW I548055 B TWI548055 B TW I548055B
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Taiwan
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package
connectors
substrate
connector
idle
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TW102113900A
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English (en)
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TW201347132A (zh
Inventor
劉明凱
梁世緯
陳憲偉
吳凱強
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台灣積體電路製造股份有限公司
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Description

堆疊封裝元件及其製作方法
本發明有關於封裝元件，且特別是有關於堆疊封裝元件及其製作方法。
自積體電路(integrated circuit，IC)問世以來，由於各種電子組件(例如電晶體、二極體、電阻、電容等)的積體密度(integration density)不斷提高，半導體工業已經歷了連續的快速成長。在大多數的情況下，積體密度(integration density)的提高是因為最小特徵尺寸(minimum feature size)一再地縮小，且最小特徵尺寸的縮小可使更多的組件集成到一給定的面積中。
較小的電子組件亦對應較小的封裝體(其比之前的封裝體使用更小的面積)。小尺寸的半導體封裝包括：四方扁平封裝(quad flat pack，QFP)、球格陣列(ball grid array，BGA)、覆晶封裝(flip chips，FC)、三維積體電路(three dimensional integrated circuits，3DICs)、晶圓級封裝(wafer level packages，WLPs)、堆疊封裝(package on package，PoP)元件。由於堆疊封裝技術可將積體電路整合至小尺寸的封裝體中而達成更加密集的積體化，因此，堆疊封裝技術變得相當重要。堆疊封裝技術係應用於許多先進的手持式元件中，例如智 慧型手機。
在堆疊封裝中，可分別封裝多個半導體晶片而形成多個封裝體、或是將多個半導體晶片封裝於一封裝體中，然後，可連接多個封裝體以形成一堆疊封裝元件，如此一來，可結合位於不同封裝體中的半導體晶片以執行預定的工作。這些分開的獨立封裝體可彼此電性連接，例如，使用接觸凸塊或是其他連接件。堆疊封裝元件具有散熱與翹曲變形的問題而有待解決。
本發明一實施例提供一種堆疊封裝元件，包括：一第一封裝體，包括一第一晶片、一第一基板、以及一第一連接件，其中第一晶片配置於第一基板的一第一表面上，第一連接件連接第一基板的一第二表面；以及一第二封裝體，包括一第二晶片、一第二基板、一第二連接件、以及一閒置連接件，其中第二晶片配置於第二基板的一表面上，第二連接件與閒置連接件配置於第二基板的表面上，其中，第一連接件連接至第二連接件，閒置連接件不連接第一封裝體的任一連接件。
本發明另一實施例提供一種堆疊封裝元件的製作方法，包括：在一底封裝體的一基板的一表面上配置一堆疊封裝連接件以及一閒置連接件，其中一晶片亦配置於基板的表面上；以一封裝膠體封裝堆疊封裝連接件、閒置連接件、以及晶片；研磨封裝膠體以暴露出堆疊封裝連接件；對齊並配置一頂封裝體，以使頂封裝體的一連接件連接至底封裝體的堆疊封裝連接件，且閒置連接件並未連接頂封裝體的任一連接件；以及 迴焊堆疊封裝連接件以及頂封裝體的連接件，以於頂封裝體與底封裝體之間形成一連接結構。
本發明又一實施例提供一種堆疊封裝元件，包括：一第一封裝體，包括一第一晶片、一第一基板、以及一第一群連接件，其中第一晶片配置於第一基板的一第一表面上，第一群連接件連接第一基板的一第二表面；以及一第二封裝體，包括一第二晶片、一第二基板、一第二群連接件、以及多個閒置連接件，其中第二晶片配置於第二基板的一表面上，第二群連接件與閒置連接件配置於第二基板的表面上，其中，第一群連接件之任一係連接至第二群連接件其中之一，閒置連接件不連接第一封裝體的任一連接件。
10‧‧‧第一封裝體、頂封裝體、封裝體
20‧‧‧第二封裝體、底封裝體、封裝體
31、32、33、34、116、120、118‧‧‧連接件
35、36、401、402、403、404、501、502、503、504、601、602、701、702‧‧‧閒置連接件、閒置球、連接件
100‧‧‧堆疊封裝元件
102‧‧‧第二IC晶片、第二晶片、晶片
104‧‧‧第二基板、基板
106‧‧‧第一積體電路(IC)晶片、第一晶片
108‧‧‧第一基板、基板
110‧‧‧導電連接件
112‧‧‧導電連接件、連接件
114、230‧‧‧封裝膠體、模具
121‧‧‧穿基板導孔(TSVs)
211、212、213、214‧‧‧銲球
221、222、223、224‧‧‧連接件、銲球
301、303、305、307、309‧‧‧步驟
400‧‧‧堆疊封裝連接件
第1A~1E圖繪示本發明一實施例之一封裝堆疊元件以及其製程的剖面圖。
第2A~2E圖繪示本發明另一實施例之一封裝堆疊元件以及其製程的剖面圖與上視圖，其中第2B圖係繪示沿第2A圖之A-A線段的剖面圖，第2D-1圖係繪示沿第2C圖之A-A線段的剖面圖，第2D-2圖係繪示沿第2C圖之B-B線段的剖面圖，第2D-3圖係繪示沿第2C圖之C-C線段的剖面圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製 造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。在圖式中，實施例之形狀或是厚度可能擴大，以簡化或是突顯其特徵。再者，圖中未繪示或描述之元件，可為所屬技術領域中具有通常知識者所知的任意形式。
以下將詳細介紹一堆疊封裝元件的製作方法與結構。簡而言之，在一實施例中，一堆疊封裝元件的形成方法包括利用多個位於一底封裝體上的堆疊封裝連接件(package on package connector)連接一頂封裝體的對應連接件，以連接頂封裝體與底封裝體。堆疊封裝元件更包括多個閒置連接件(dummy connector)。閒置連接件係配置於底封裝體上且不連接任何頂封裝體的連接件。因此，閒置連接件並非用以連接。閒置連接件係用以減少封裝膠體的體積以減少元件翹曲變形。此外，閒置連接件的材質為金屬，因此，可有助於散熱以及分散應力(stress redistribution)。閒置連接件可與堆疊封裝連接件同時形成。
第1A圖繪示本發明一實施例之二獨立的封裝體10、20的剖面圖，第1B圖係繪示使封裝體10、20彼此連接而形成一堆疊封裝元件100的剖面圖，第1C圖繪示堆疊封裝元件100的製作方法。前述製程的中間步驟係繪示於第1D、1E圖中。
如第1A圖所示，一第一封裝體10可為一頂封裝體，其具有一第一基板108。一第一積體電路(IC)晶片106係藉由一組導電連接件110安裝在基板108的一表面上，該表面可為基板的頂面。多個導電通孔(through via，未繪示)可電性連接於第一晶片106與另一組導電連接件112之間，導電連接件112例如為位於基板108之一相對表面上的接墊，其中前述相對表面可為基板的底面。可在組件上形成一封裝膠體或是模具(encapsulant or mold)114以保護組件免於受到環境與外界的污染。多個連接件(例如銲球221-224)可形成在第一基板108的底面上。連接件221-224可用以連接另一封裝體，例如一底封裝體20。連接件221-224貼附至位於第一基板108的底部上的連接件112(其可為接墊)。連接件(例如112、110)的數量以及連接件(例如221-224)的數量僅用以舉例說明，並非用以限定本發明。連接件可為接墊(例如連接件112)或是銲球(例如連接件221)。只要是可提供電性連接的組件都可稱為連接件。封裝體10可具有其他數量的連接件。
第一封裝體10可封裝晶片106，封裝方法包括覆晶晶圓級封裝(WLP)技術以及打線接合技術、或是覆晶以及導線上凸塊(bump-on-trace，BOT)技術。可選擇其中一種封裝技術來形成封裝體10。基板108亦可包括重佈線層(未繪示)位於基板108的一或兩表面上及/或之中，以形成不同的引腳配置(pin configuration)以及較大的電性連接面積。基板108例如可為封裝基板、印刷電路板、高密度內連線結構、或其相似物。晶片106例如為一記憶體晶片或是一邏輯晶片。連接件 110、112可例如包括接觸墊、無鉛銲料(lead free solder)、共晶引腳(eutectic lead)、導電柱、前述之組合、及/或其相似物。若是連接件221-224為銲球，其形成方法包括進行一銲球安裝製程，接著進行一銲料回流製程(solder reflow process)。亦可採用其他方法來形成連接件221-224。
第二封裝體20(其可稱為一底封裝體)包括一第二基板104與一第二IC晶片102安裝於第二基板104的一表面上，前述表面可為第二基板104的一頂面。第二晶片102可具有邏輯功能(logic function)。基板104經由一組連接件116、120連接至晶片102。連接件116可為多個接墊，連接件120可為多個銲球，且連接件116、120共同形成多個連接結構，以連接於晶片102與基板104之間。另一組連接件118可沿著第二基板104之一相對於晶片102的表面形成，前述表面可為底面。貫穿第二基板104的多個穿基板導孔(TSVs)121可電性連接於連接件116與連接件118之間。多個連接件(例如銲球211-214)可形成在基板104的底面上。基板104亦可包括重佈線層(未繪示)位於第二基板104的一或兩表面上及/或之中，以形成不同的引腳配置(pin configuration)以及較大的電性連接面積。
在一實施例中，基板104可為任何適合的基板，例如一矽基板、一有機基板、一陶瓷基板、一介電基板、一積層基板(laminate substrate)、或其相似物。連接件116、120、118可例如包括接觸墊、無鉛銲料(lead free solder)、共晶引腳(eutectic lead)、導電柱、前述之組合、及/或其相似物。晶片102可為任何適合的積體電路晶片，前述積體電路晶片具有特 定的應用。舉例來說，晶片102可為一記憶體晶片，例如DRAM、SRAM、NVRAM、或是邏輯電路。雖然，只有晶片102繪示於第1A、1B圖中，然而，亦可有多個晶片位於基板104上。同樣地，亦可有多個晶片位於基板108上。
可電性連接第一封裝體10與第二封裝體20以形成一堆疊封裝元件100，如第1B圖所示。一組連接件(例如31-36)可形成在基板104的頂面上，晶片102亦是安裝在基板104的頂面上。連接件31-34(亦可稱為堆疊封裝連接件)係依照頂封裝體10的連接件221-224的圖案而形成，這代表堆疊封裝連接件31-34係分別對齊連接件221-224。連接件35、36為額外的連接件(有時可稱為閒置連接件)，其並未對應且亦未連接頂封裝體10的任何連接件。連接件31-34可更連接至基板104上的一些接墊，前述接墊可連接至晶片102或基板104的其他內部功能。另一方面，連接件35、36可不連接至任何其他功能或是接墊。可以封裝膠體或是模具230覆蓋所有的連接件31-36以保護組件免於受到環境或是外界的污染。之後，可研磨封裝膠體230以暴露出連接件31-34。之後，可對齊與貼附頂封裝體10，以使連接件31-34以一對一的方式連接至連接件221-224。
第1B圖所示的連接件35、36係稱為閒置連接件或是閒置球(dummy ball)。簡而言之，底封裝體的閒置連接件是一種不連接頂封裝體的任何連接件的連接件，因此，閒置連接件或是閒置球並非如同堆疊封裝連接件一般是用以連接。相反地，閒置連接件是用以減少封裝膠體的體積，以減少封裝體的翹曲變形。此外，閒置連接件的材質為金屬，故可有助於散 熱以及分散應力。
第1C圖繪示本發明一實施例之一封裝半導體元件的製作流程圖。在步驟301中，多個連接件(例如銲球)係安裝在底封裝體的一基板的一表面上，前述表面可為基板的頂面，其中一些連接件構成一圖案，前述圖案係設計如同頂封裝體的連接件圖案，前述連接件係稱為堆疊封裝連接件。一些其他的連接件為閒置連接件，其不對應頂封裝體的連接件的圖案。在步驟303中，以一封裝膠體包覆基板表面上的連接件(包括堆疊封裝連接件以及閒置連接件)，封裝膠體例如為模製材料(molding material)。在步驟305中，研磨封裝膠體以暴露出堆疊封裝連接件，以使堆疊封裝連接件可連接至頂封裝體的連接件。閒置連接件也可於此製程中被暴露出來。在步驟307中，對齊頂封裝體，以使頂封裝體的連接件配置於底封裝體的堆疊封裝連接件的頂部上並連接堆疊封裝連接件。之後，在步驟309中，迴焊(reflow)形成的封裝體，以連接堆疊封裝連接件與頂封裝體的連接件。
第1D圖繪示步驟301，可在底封裝體20的基板104的頂面上形成一組連接件(例如31-36)。連接件31-34為堆疊封裝連接件，其係依據頂封裝體10的連接件221-224的圖案而形成。連接件35、36為閒置連接件，其不對應頂封裝體10的任何連接件。連接件31-34可更連接至基板104上的一些連接件(其連接至晶片102或基板104的其他內部功能)。另一方面，連接件35、36可不連接至任何其他功能。連接件或銲球31-36可包括一材料，例如為錫、或其他適合的材料，例如銀、無鉛錫、 銅、前述之組合、或是其相似物。
第1E圖繪示步驟303，其顯示在一實施例中，在第二基板104上形成一封裝膠體230。在一實施例中，封裝膠體230為一鑄模底膠(molding underfill，MUF)，例如包括高分子、環氧樹脂、其/或其相似物。可例如利用壓模成型(compressive molding)或是轉注成型(transfer molding)的方式將封裝膠體230形成在晶片102與基板104上。封裝膠體230可接觸晶片102的頂面與邊緣。在一實施例中，封裝膠體230的頂面可與晶片102的頂面共平面。在其他實施例中，封裝膠體230的頂面可高於晶片102的頂面，以使封裝膠體230可將晶片102完全包覆於其內。
在步驟305中，可進行一研磨或是拋光製程以移除封裝膠體230之高於晶片102的頂面的部份以暴露出晶片102。亦可研磨封裝膠體230以暴露出堆疊封裝連接件31-34，以使堆疊封裝連接件31-34可連接至頂封裝體的連接件。此外，在一未繪示的實施例中，可在封裝膠體230以及連接件31-34的表面上配置一助焊劑(flux)。助焊劑可有助於清潔封裝膠體230與堆疊封裝連接件31-34的表面，藉此幫助形成電性連接於堆疊封裝連接件31-34以及連接件221-224之間。助焊劑的形成方法例如包括浸泡法(dipping operation)，其係將封裝膠體230與連接件31-34的表面浸泡入助焊劑中。
在步驟307中，對齊頂封裝體，以使頂封裝體的連接件221-224配置於底封裝體的堆疊封裝連接件31-34的頂部上。前述對齊的方法包括將頂封裝體的連接件221-224其中之 一耦接至位於底封裝體的第二基板的頂面上的連接件31-34其中之一。
然後，在步驟309中，迴焊(已形成的)封裝體，以於底封裝體的堆疊封裝連接件31-34以及頂封裝體的連接件221-224之間形成連接。在一實施例中，利用一感應迴焊製程(induction reflow process)進行前述迴焊製程。然而，在其他實施例中，亦可使用其他迴焊製程。結果形成一如第1B圖所示之堆疊封裝元件。
以相似的製程可形成更多實施例。第2A-2E圖繪示另一實施例之堆疊封裝元件的剖面圖與上視圖。第2A圖繪示頂封裝體的上視圖，第2B圖繪示頂封裝體的剖面圖。頂封裝體的封裝方法包括利用覆晶晶圓級封裝(WLP)技術以及打線接合技術、或是覆晶以及導線上凸塊(bump-on-trace，BOT)技術。可選擇其中一種封裝技術來形成頂封裝體。
第2C圖與第2E圖繪示一堆疊封裝元件的底封裝體的上視圖，第2D-1、2D-2、2D-3圖繪示底封裝體的剖面圖。底封裝體具有兩行的堆疊封裝連接件400，堆疊封裝連接件400可為球陣列並圍繞底封裝體的基板的周邊區域，而形成二個環，並對應於第2A圖之頂封裝體的連接件400。多個閒置連接件401-404、501-504、601-602可配置於底封裝體的頂面上。閒置連接件的數目僅用以舉例說明，並非用以限定本發明。或者是，亦可使用其他數量的銲球。
閒置連接件401-404排列在線段A上並且相當接近堆疊封裝連接件。第2D圖繪示四個閒置銲球401-404的剖面 圖，且在閒置銲球401-404的每一側都配置有二個堆疊封裝連接件400。連接件501-504係排列在線段B上，並且相當接近晶片102。第2D圖繪示四個閒置連接件501-504的剖面圖，其中在閒置連接件501-504的每一側都配置有二個堆疊封裝連接件400。連接件601-602係排列在線段C上，並且相當接近晶片102，且連接件601-602的剖面圖亦包括晶片102。連接件601-602的各側亦圍繞有二個堆疊封裝連接件400。
第2E圖繪示本發明一實施例之堆疊封裝元件的底封裝體的上視圖，其中形成多個閒置連接件。一些閒置連接件係配置於環狀排列的堆疊封裝連接件的周圍，另一些閒置連接件係配置於堆疊封裝連接件之間。一些閒置連接件(例如連接件701)可小於另一些閒置連接件702。
值得注意的是，前文提供多個實施例之一般性描述，且這些實施例可包括多個其他結構或是特徵。舉例來說，多個實施例可包括凸塊下金屬層(under bump metallization layers)、保護層、封裝膠體、額外的晶片及/或基板、或其相似物。此外，晶片106與晶片102的結構、配置、與位置僅用以舉例說明，因此，其他實施例可採用不同的結構、配置、與位置。
可以了解的是，前述各種步驟的順序係用以舉例說明，因此，其他實施例可採用不同的順序。實施例的範圍涵蓋各種順序的製程步驟。
之後，可採用其他一般製程來完成元件100。舉例來說，第二基板104可被貼附至另一基板，例如印刷電路板、 高密度內連線、矽基板、有機基板、陶瓷基板、介電基板、積層基板、另一半導體封裝體、或其相似物。
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧第一封裝體、頂封裝體、封裝體
20‧‧‧第二封裝體、底封裝體、封裝體
31、32、33、34、116、120、118‧‧‧連接件
35、36‧‧‧閒置連接件、閒置球、連接件
100‧‧‧堆疊封裝元件
102‧‧‧第二IC晶片、第二晶片、晶片
104‧‧‧第二基板、基板
106‧‧‧第一積體電路(IC)晶片、第一晶片
108‧‧‧第一基板、基板
110‧‧‧導電連接件
112‧‧‧導電連接件、連接件
114、230‧‧‧封裝膠體、模具
121‧‧‧穿基板導孔(TSVs)
211、212、213、214‧‧‧銲球
221、222、223、224‧‧‧連接件、銲球

Claims (10)

  1. 一種堆疊封裝元件，包括：一第一封裝體，包括一第一晶片、一第一基板、以及一第一連接件，其中該第一晶片配置於該第一基板的一第一表面上，該第一連接件連接該第一基板的一第二表面；以及一第二封裝體，包括一第二晶片、一第二基板、一第二連接件、以及一閒置連接件，其中該第二晶片配置於該第二基板的一表面上，該第二連接件與該閒置連接件配置於該第二基板的該表面上，且該第二連接件與該閒置連接件延伸穿過一封裝膠體，其中，該第一連接件連接至該第二連接件，該閒置連接件不連接該第一封裝體的任一連接件。
  2. 如申請專利範圍第1項所述之堆疊封裝元件，更包括：一第一群連接件，連接該第一基板的該第二表面；一第二群連接件，連接該第二基板的該表面；以及一第三群閒置連接件，其中該第一群連接件之任一係連接至該第二群連接件其中之一，該第三群閒置連接件並未連接該第一封裝體之任一連接件。
  3. 如申請專利範圍第1項所述之堆疊封裝元件，其中該第一連接件係連接至該第一基板的一底面，該第一晶片係配置於該第一基板的一頂面上。
  4. 如申請專利範圍第1項所述之堆疊封裝元件，其中該閒置連接件的尺寸不同於該第二連接件的尺寸。
  5. 如申請專利範圍第1項所述之堆疊封裝元件， 其中該封裝膠體覆蓋該第二晶片，且該封裝膠體介於該第二連接件、該閒置連接件和該第二晶片之間。
  6. 一種堆疊封裝元件的製作方法，包括：在一底封裝體的一基板的一表面上配置一堆疊封裝連接件以及一閒置連接件，其中一晶片亦配置於該基板的該表面上；以一封裝膠體封裝該堆疊封裝連接件、該閒置連接件、以及該晶片；研磨該封裝膠體以暴露出該堆疊封裝連接件與該閒置連接件；對齊並配置一頂封裝體，以使該頂封裝體的一連接件連接至該底封裝體的該堆疊封裝連接件，且該閒置連接件並未連接該頂封裝體的任一連接件；以及迴焊該堆疊封裝連接件以及該頂封裝體的該連接件，以於該頂封裝體與該底封裝體之間形成一連接結構。
  7. 如申請專利範圍第6項所述之堆疊封裝元件的製作方法，更包括：於該底封裝體的該基板的該表面上配置多個堆疊封裝連接件以及多個閒置連接件；以一封膠膠體封裝該些堆疊封裝連接件、該些閒置連接件、以及該晶片；研磨該封裝膠體以暴露出該些堆疊封裝連接件；對齊並配置一頂封裝體，以使該頂封裝體的多個連接件以一對一的方式連接至該底封裝體的該些堆疊封裝連接件， 且該些閒置連接件不連接該頂封裝體的任一連接件；以及迴焊該些堆疊封裝連接件以及該頂封裝體的該些連接件，以於該頂封裝體與該底封裝體之間形成多個連接結構。
  8. 一種堆疊封裝元件，包括：一第一封裝體，包括一第一晶片、一第一基板、以及一第一群連接件，其中該第一晶片配置於該第一基板的一第一表面上，該第一群連接件連接該第一基板的一第二表面；以及一第二封裝體，包括一第二晶片、一第二基板、一第二群連接件、以及多個閒置連接件，其中該第二晶片配置於該第二基板的一表面上，該第二群連接件與該些閒置連接件配置於該第二基板的該表面上，且該第二群連接件與該些閒置連接件延伸穿過一封裝膠體，其中，該第一群連接件之任一係連接至該第二群連接件其中之一，該些閒置連接件不連接該第一封裝體的任一連接件。
  9. 如申請專利範圍第8項所述之堆疊封裝元件，其中一閒置連接件的位置係接近由該第二群連接件所構成的一環狀結構的一角落、或是接近該第二晶片的一角落。
  10. 如申請專利範圍第8項所述之堆疊封裝元件，其中該些閒置連接件的尺寸彼此不同。
TW102113900A 2012-05-03 2013-04-19 堆疊封裝元件及其製作方法 TWI548055B (zh)

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