TWI536470B - 半導體裝置及形成雙凸塊底層金屬結構以用於無鉛凸塊連接之方法 - Google Patents

半導體裝置及形成雙凸塊底層金屬結構以用於無鉛凸塊連接之方法 Download PDF

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TWI536470B
TWI536470B TW100109674A TW100109674A TWI536470B TW I536470 B TWI536470 B TW I536470B TW 100109674 A TW100109674 A TW 100109674A TW 100109674 A TW100109674 A TW 100109674A TW I536470 B TWI536470 B TW I536470B
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ubm
insulating layer
bump
conductive layer
layer
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TW100109674A
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TW201203409A (en
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林立人
史帝芬Ａ 墨菲
孫偉
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史達晶片有限公司
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Description

半導體裝置及形成雙凸塊底層金屬結構以用於無鉛凸塊連接之方法 【優先權主張】
本非臨時申請案係主張2010年3月25日申請的美國臨時申請案序號61/317,664的優先權，並且根據美國專利法第120條主張前述基礎申請案的優先權。
本發明係大致有關於半導體裝置，並且更具體而言，其係有關於一種半導體裝置及形成雙凸塊底層金屬(UBM)結構以用於無鉛凸塊連接的方法。
半導體裝置常見於現代的電子產品中。半導體裝置在電性構件的數目及密度上有所不同。離散的半導體裝置一般包含一種類型的電性構件，例如，發光二極體(LED)、小信號的電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(MOSFET)。積體化半導體裝置通常包含數百個到數百萬個電性構件。積體化半導體裝置的例子包含微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池、以及數位微鏡裝置(DMD)。
半導體裝置可執行廣大範圍的功能，例如：信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、轉換太陽光成為電力、以及產生用於電視顯示器之可見的投影。半導體裝置可見於娛樂、通訊、電力轉換、網路、電腦、以及消費性產品的領域中。半導體裝置亦可見於軍事應用、航空、汽車、工業用控制器、以及辦公室設備。
半導體裝置係利用半導體材料的電氣特性。半導體材料的原子結構係容許其導電度可藉由一電場或基極電流的施加或是透過摻雜的製程來操控。摻雜係將雜質引入半導體材料中以操控及控制半導體裝置的導電度。
一半導體裝置係包含主動及被動的電氣結構。包含雙載子及場效電晶體的主動結構係控制電流的流動。藉由改變摻雜的程度以及一電場或基極電流施加的位準，電晶體不是提升就是限制電流的流動。包含電阻器、電容器及電感器的被動結構係產生執行各種電氣功能所必要的一種電壓及電流間之關係。被動及主動結構係電連接以形成電路，此係使得半導體裝置能夠執行高速的計算以及其它有用的功能。
半導體裝置一般是利用兩種複雜的製程，亦即，前端製造及後端製造來製成，每一種都牽涉到可能有數百道的步驟。前端製造係牽涉到在一半導體晶圓的表面上複數個晶粒的形成。每個晶粒通常是相同的並且包含由電連接主動及被動構件所形成的電路。後端製造係牽涉到從晶圓成品單切(singulating)個別的晶粒及封裝該晶粒以提供結構的支撐及環境的隔離。
半導體製造的一項目標是生產出更小的半導體裝置。越小的裝置通常消耗更低的電力，具有更高的效能，並且可更有效率地被生產出。此外，越小的半導體裝置具有更小的覆蓋區(footprint)，此係為更小的最終產品所期望的。更小的晶粒尺寸可藉由在前端製程中以更小及更高密度的主動及被動構件來產生晶粒的改良而達成。後端製程可藉由在電氣互連及封裝材料上的改良以產生更小的覆蓋區之半導體裝置封裝。
一種將一半導體晶粒與一印刷電路板或其它裝置互連的常見的技術係牽涉到焊料凸塊的使用。圖1係展示一習知的聚醯亞胺在UBM之上(POU)的焊料凸塊結構10。一導電層14係形成在半導體晶圓12的一主動表面之上，並且操作為一接觸墊。晶圓12係為了初始品質管制(IQC)而被檢查。一絕緣或保護(passivation)層16係形成在半導體晶圓12及導電層14之上。絕緣層16的一部份係藉由一蝕刻製程而被移除，以露出導電層14的一部份。部分形成的POU結構10係進行第一次洗滌器(scrubber)清洗。一導電層或濺鍍的UBM 18係形成在絕緣層16及導電層14之上。一鎳(Ni)UBM或導電層20係形成在導電層18之上並且保形地施加到導電層18，以運作為一用於之後形成的凸塊之凸塊墊。部分形成的POU結構10係進行第二次洗滌器清洗。一層聚醯亞胺係作用為一絕緣或保護層22，其係形成在導電層18及Ni UBM 20之上。該聚醯亞胺係在乾膜光阻(DFR)層疊之前先被塗覆、對準、顯影、固化、去渣、酸洗、以及烘烤。一在絕緣層22中的開口係形成在Ni UBM 20之上。該DFR係層疊在絕緣層22之上，並且接著進行一邊緣清洗、對準、聚對苯二甲酸乙二酯(PET)移除、顯影、第一次去渣、硬烤、以及第二次去渣。焊料材料係電鍍在Ni UBM 20之上並且在該DFR層中的一開口內。該DFR係被剝除，電漿灰係被施加，Ni UBM 20係被蝕刻，並且部分完成的POU結構10係進行一第三次洗滌器清洗。一助熔劑塗層係被施加至該電鍍焊料材料，並且該焊料材料係加以回焊(reflow)以形成球體或凸塊24，其係形成在Ni UBM 20之上並且電連接至Ni UBM 20。該裝置係進行一助熔劑清洗、凸塊量測、以及最後的目視檢查(FVI)，此係產生POU結構10。像是POU結構10的習知POU結構係包含來自凸塊24的錫(Sn)沿著Ni UBM 20的一側壁行進以和UBM的銅(Cu)反應以形成一金屬間的化合物(IMC)的風險。
圖2係展示一習知的聚醯亞胺及無鉛的凸塊結構28。一導電層32係形成在半導體晶圓30的一主動表面之上，並且操作為一接觸墊。晶圓30係為了IQC而被檢查。一絕緣或保護層34係形成在半導體晶圓30之上，並且接觸導電層32的一側壁。部分形成的凸塊結構28係進行洗滌器清洗及烘烤。一層聚醯亞胺係作用為一絕緣或保護層36，並且形成在導電層32及絕緣層34之上。該聚醯亞胺係被塗覆、對準、顯影、固化、去渣以及酸洗，以使得導電層32的一部份露出。一導電層38係形成在導電層32的一部份以及絕緣層36的一部份之上，並且保形地施加到該些部份。在一實施例中，導電層38係被濺鍍以運作為一UBM，而供之後形成的凸塊使用，並且其係包含一或多層的鈦(Ti)、Cu及Ni。該裝置接著進行洗滌器清洗，並且一DFR層係層疊在絕緣層36及導電層38之上。該DFR層係進行邊樑清洗、對準、PET移除、顯影、第一次去渣、硬烤、以及第二次去渣。焊料材料係電鍍在導電層38之上並且在該DFR層中的一開口之內。該DFR係被剝除，導電層38係被蝕刻，並且該裝置係進行第三次洗滌器清洗、第一次氮氣(N2)處理、第二次蝕刻、第四次洗滌器清洗、硬烤以及氧氣(O2)電漿處理。一助熔劑塗層係被施加至該電鍍的焊料材料，並且該焊料材料係加以回焊以形成球體或凸塊40，其係形成在導電層38之上並且電連接至導電層38。該裝置接著進行助熔劑清洗、第二次N2處理、凸塊量測、第五次洗滌器清洗以及FVI，此係產生該聚醯亞胺以及無鉛的凸塊結構28。
對於例如是圖1及2中所呈現者之利用無鉛焊料的覆晶連結而言，有關焊點可靠度的憂慮更加嚴重。無鉛焊料係包含帶有Cu及銀(Ag)的Sn基合金，其具有比傳統的共晶SnPb焊料高的熔點。該較高的溫度及較高的Sn濃度導致SnPb焊料及UBM之間更嚴重的反應，此可能導致過度的IMC形成，可能造成UBM上的抗濕潤(dewetting)並且產生弱的焊點。
對於改善無鉛凸塊連接的焊點可靠度係存在著需求。於是，在一實施例中，本發明是一種製造一半導體裝置的方法，其係包括以下步驟：提供一帶有一接觸墊的基板，在該基板及接觸墊之上形成一第一絕緣層，在該第一絕緣層之上形成一第一UBM並且電連接至該接觸墊，在該第一UBM之上形成一第二絕緣層，以及在該第二絕緣層固化之後，在該第二絕緣層之上形成一第二UBM。該第二UBM係電連接至該第一UBM以使得該第二絕緣層係在該第一及第二UBM的部份之間並且分開該些部份。該方法進一步包含以下步驟：在該第二UBM之上形成一光阻層並且移除該光阻層的一部份以在該接觸墊之上的光阻層中形成一開口，在該光阻層中的該開口之中沉積一導電的凸塊材料，移除該光阻層，移除該第二UBM的一週邊部份以使得該導電的凸塊材料突出於該第二UBM的上方，移除該第一UBM的一週邊部份以使得該第二絕緣層突出於該第一UBM的上方，以及回焊該導電的凸塊材料以形成一球狀凸塊。
在另一實施例中，本發明是一種製造一半導體裝置的方法，其係包括以下步驟：提供一帶有一接觸墊的基板，在該基板之上形成一第一UBM並且電連接至該接觸墊，在該第一UBM之上形成一絕緣層，在該絕緣層固化之後在該絕緣層之上形成一第二UBM，以及在該第二UBM之上形成一凸塊。該第二UBM係電連接至該第一UBM以使得該第二絕緣層分開該第一及第二UBM的部份。
在另一實施例中，本發明是一種製造一半導體裝置的方法，其係包括以下步驟：提供一帶有一接觸墊的基板，在該基板之上形成一第一UBM並且電連接至該接觸墊，在該第一UBM之上形成一絕緣層，在該絕緣層固化之後在該絕緣層之上形成一第二UBM，以及在該第二UBM之上形成一凸塊。
在另一實施例中，本發明是一種半導體裝置，其係包括一帶有一接觸墊的基板。一具有一區域大於該接觸墊的一區域的第一UBM係形成在該基板之上並且電連接至該接觸墊。一絕緣層係形成在該第一UBM之上。一第二UBM係形成在該絕緣層之上並且電連接至該第一UBM，以使得該絕緣層係在該第一及第二UBM的部份之間。一凸塊係形成在該第二UBM之上。
本發明在以下參考圖式的說明中係以一或多個實施例加以描述，其中相同元件符號代表相同或類似元件。儘管本發明是依據達成本發明目的之最佳模式描述，但熟習此項技術者將瞭解本發明欲涵蓋如隨附申請專利範圍所界定之可內含於本發明之精神及範疇內的替代物、修改及等效物以及如以下揭示內容及圖式所支持之其等效物。
半導體裝置一般是使用兩個複雜的製程來製造：前端製造與後端製造。前端製造係牽涉到在半導體晶圓表面上形成多個晶粒。該晶圓上之各晶粒含有主動及被動電性構件，其係電連接以形成功能電路。諸如電晶體及二極體之主動電性構件係具有控制電流流動之能力。諸如電容器、電感器、電阻器及變壓器之被動電性構件係產生執行電路功能所必要的一種電壓及電流間之關係。
被動及主動構件藉由一系列製程步驟形成於半導體晶圓表面上，包括摻雜、沉積、微影、蝕刻及平坦化。摻雜係藉由諸如離子植入或熱擴散之技術將雜質引入半導體材料中。摻雜製程改變主動裝置中半導體材料之導電度，從而將該半導體材料轉變成絕緣體、導體，或是響應於電場或基極電流而動態地改變該半導體材料之導電度。電晶體含有摻雜類型及程度不同之區域，其視需要來加以配置以使該電晶體能夠在施加電場或基極電流時促進或限制電流流動。
主動及被動構件係由具有不同電特性之材料層形成。該等層可藉由多種沉積技術形成，該些沉積技術部分是由所沉積之材料類型決定的。舉例而言，薄膜沉積可包括化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解的電鍍及無電的電鍍製程。每個層一般是經圖案化以形成主動構件、被動構件或各構件間電連接的部分。
該些層可使用微影進行圖案化，其牽涉到使光敏材料(例如光阻)沉積於待圖案化的層之上。使用光以將圖案自光罩轉印於光阻上。在一實施例中，該光阻圖案遭受光的部份係利用一溶劑加以移除，此係露出在下面待圖案化的層的部份。在另一實施例中，該光阻圖案未遭受光的部份(負光阻)係利用一溶劑加以移除，此係露出在下面待圖案化的層的部份。移除該光阻之其餘部分，留下一經圖案化的層。或者，某些類型的材料係使用諸如無電的電鍍及電解的電鍍之技術藉由使材料直接沉積於由先前沉積/蝕刻製程所形成的區域或空隙中而加以圖案化。
在現有圖案之上沉積一材料薄膜可能會放大下面的圖案且產生非均勻平坦的表面。生產較小且較密集封裝之主動及被動構件需要均勻平坦的表面。可使用平坦化以自晶圓表面移除材料且產生均勻平坦的表面。平坦化係牽涉到用拋光墊拋光晶圓的表面。在拋光期間將研磨材料及腐蝕性化學品添加至晶圓的表面。研磨劑的機械作用與化學品的腐蝕作用組合可移除任何不規則的表面構形，從而產生均勻平坦的表面。
後端製造係指將晶圓成品切割或單切成個別晶粒且接著封裝該晶粒以提供結構的支撐及環境的隔離。為了單切晶粒，沿著晶圓非功能區(稱為切割道或劃線)將晶圓劃痕並切斷。使用雷射切割工具或鋸條單切晶圓。在單切之後，將個別晶粒安裝於一封裝基板上，該封裝基板包括接腳或接觸墊以供與其他系統構件互連。接著使半導體晶粒上所形成之接觸墊連接至封裝內之接觸墊。該電連接可由焊料凸塊、柱形凸塊、導電膏或焊線(wirebond)形成。使一封裝材料或其它模製材料沉積於封裝之上以提供物理支撐及電隔離。接著將成品封裝插入一電系統中，且使半導體裝置之功能可供其他系統構件利用。
圖3係描繪具有多個安裝於其表面上之半導體封裝的晶片載體基板或PCB 52之電子裝置50。視應用而定，電子裝置50可具有一種類型之半導體封裝或多種類型之半導體封裝。不同類型之半導體封裝係為了說明之目的而展示於圖3中。
電子裝置50可以是一使用該些半導體封裝以執行一或多種電功能之獨立的系統。或者，電子裝置50可以是一較大系統之子構件。舉例而言，電子裝置50可以是行動電話、個人數位助理(PDA)、數位視訊攝影機(DVC)、或是其它電子通訊裝置的一部份。或者是，電子裝置50可以是一可插入電腦中之顯示卡、網路介面卡或其他信號處理卡。該半導體封裝可包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、RF電路、離散裝置或其他半導體晶粒或電性構件。小型化及重量減輕是這些產品能夠被市場接受所不可少的。在半導體裝置間的距離必須縮短以達到更高的密度。
在圖3中，PCB 52係提供一般的基板以供安裝在該PCB上之半導體封裝的結構支撐及電氣互連。導電的信號線路54係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或其它適合的金屬沉積製程而被形成在PCB 52的一表面之上或是在層內。信號線路54提供在半導體封裝、安裝的構件、以及其它外部的系統構件的每一個之間的電通訊。線路54亦提供電源及接地連接給每個半導體封裝。
在某些實施例中，一半導體裝置具有兩個封裝層級。第一層級的封裝是一種用於將半導體晶粒機械及電氣地附接至一中間載體的技術。第二層級的封裝係牽涉到將該中間載體機械及電氣地附接至PCB。在其它實施例中，一半導體裝置可以只有該第一層級的封裝，其中晶粒是直接機械及電氣地安裝到PCB上。
為了說明之目的，包含打線接合封裝56及覆晶58之數種類型的第一層級的封裝係被展示在PCB 52上。此外，包含球狀柵格陣列(BGA)60、凸塊晶片載體(BCC)62、雙排型封裝(DIP)64、平台柵格陣列(LGA)66、多晶片模組(MCM)68、四邊扁平無引腳封裝(QFN)70及四邊扁平封裝72之數種類型的第二層級的封裝係被展示安裝在PCB 52上。視系統需求而定，以第一及第二層級的封裝類型的任意組合來組態的半導體封裝的任何組合及其它電子構件可連接至PCB 52。在某些實施例中，電子裝置50包含單一附接的半導體封裝，而其它實施例需要多個互連的封裝。藉由在單一基板之上組合一或多個半導體封裝，製造商可將預製的構件納入電子裝置及系統中。由於半導體封裝包括複雜的功能，因此可使用較便宜構件及流線化製程來製造電子裝置。所產生的裝置不太可能發生故障且製造費用較低，從而降低消費者成本。
圖4a-4c係展示範例的半導體封裝。圖4a係描繪安裝在PCB 52上的DIP 64之進一步的細節。半導體晶粒74係包括一含有類比或數位電路的主動區域，該些類比或數位電路係被實施為形成在晶粒內之主動裝置、被動裝置、導電層及介電層並且根據該晶粒的電設計而電互連。例如，該電路可包含形成在半導體晶粒74的主動區域內之一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸墊76是一或多層的導電材料，例如鋁(Al)、Cu、Sn、Ni、金(Au)或Ag，並且電連接至形成在半導體晶粒74內之電路元件。在DIP 64的組裝期間，半導體晶粒74係利用一金矽共晶層或例如是熱環氧樹脂的黏著劑材料而被安裝至一中間載體78。封裝主體係包含一種例如是聚合物或陶瓷的絕緣封裝材料。導線80及焊線82係在半導體晶粒74及PCB 52之間提供電互連。封裝材料84係為了環境保護而沉積在該封裝之上以防止濕氣及微粒進入該封裝且污染晶粒74或焊線82。
圖4b係描繪安裝在PCB 52上之BCC 62的進一步細節。半導體晶粒88係利用一種底膠填充(underfill)或是環氧樹脂黏著材料92而被安裝在載體90之上。焊線94係在接觸墊96及98之間提供第一層級的封裝互連。模製化合物或封裝材料100係沉積在半導體晶粒88及焊線94之上以提供物理支撐及電氣隔離給該裝置。接觸墊102係利用一例如是電解的電鍍或無電的電鍍之合適的金屬沉積製程而被形成在PCB 52的一表面之上以避免氧化。接觸墊102係電連接至PCB 52中的一或多個導電信號線路54。凸塊104係形成在BCC 62的接觸墊98以及PCB 52的接觸墊102之間。
在圖4c中，半導體晶粒58係以覆晶型第一層級的封裝方式面向下安裝到中間載體106。半導體晶粒58的主動區域108係包含類比或數位電路，該些類比或數位電路係被實施為根據該晶粒的電設計所形成的主動裝置、被動裝置、導電層及介電層。例如，該電路可包含一或多個電晶體、二極體、電感器、電容器、電阻器以及主動區域108內之其它電路元件。半導體晶粒58係透過凸塊110電氣及機械地連接至載體106。
BGA 60係以BGA型第二層級的封裝方式利用凸塊112電氣及機械地連接至PCB 52。半導體晶粒58係透過凸塊110、信號線114及凸塊112電連接至PCB 52中的導電信號線路54。一種模製化合物或封裝材料116係沉積在半導體晶粒58及載體106之上以提供物理支撐及電氣隔離給該裝置。該覆晶半導體裝置係提供從半導體晶粒58上的主動裝置到PCB 52上的導電跡線之短的導電路徑，以便縮短信號傳播距離、降低電容以及改善整體電路效能。在另一實施例中，半導體晶粒58可在無中間載體106的情況下，利用覆晶型第一層級的封裝直接機械及電連接至PCB 52。
圖5a-51係相關於圖3及4a-4c來描繪一種形成一包含用於無鉛凸塊連接的雙UBM結構的半導體裝置的製程。圖5a係展示一具有一種例如是矽、鍺、砷化鎵、磷化銦或碳化矽的主體基板材料122以供結構支撐的半導體晶圓120。複數個半導體晶粒或構件124係形成在晶圓120上且藉由如上所述的切割道126分開。
圖5b係展示半導體晶圓120的一部份的橫截面圖。每個半導體晶粒124具有一背表面128以及包含類比或數位電路的主動表面130，該類比或數位電路被實施為形成在該晶粒內且根據該晶粒的電設計及功能電互連的主動裝置、被動裝置、導電層以及介電層。例如，該電路可包含一或多個電晶體、二極體以及其它形成在主動表面130內之電路元件以實施類比電路或數位電路，例如數位信號處理器(DSP)、ASIC、記憶體或是其它信號處理電路。半導體晶粒124亦可包含IPD，例如電感器、電容器及電阻器，以供RF信號處理使用。半導體晶粒124亦可以是一覆晶類型的半導體晶粒。
一導電層132係形成在主動表面130之上且在其上延伸，以使得導電層132的一頂表面產生一不平坦的表面，並且具有一相對於主動表面130之非平坦的拓撲。導電層132係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它合適的金屬沉積製程來加以形成。導電層132可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它合適的導電材料。導電層132係運作為電連接至主動表面130上的電路之接觸墊。
圖5c係展示半導體晶圓120的一部份之一放大的橫截面圖，其焦點在導電層132以及緊繞該接觸墊的一區域。晶圓120係為了IQC而被檢查。一絕緣或保護層134接著係藉由橫跨主動表面130、從導電層132的側壁向上並且橫跨該接觸墊的一頂表面延伸，以保形地施加到晶圓120及導電層132，並且依循晶圓120及導電層132的輪廓。絕緣層134係具有一在晶圓120上的高度會變化的頂表面138。形成在晶圓120之上而且在導電層132的一覆蓋區外的頂表面138的一第一部份係具有H1的高度。形成在晶圓120之上而且在導電層132之上的頂表面138的一第二部份係具有H2的高度，其中H2大於H1。該絕緣層134可以是一或多層的二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、鋯石(ZrO2)、鋁氧化物(Al2O3)、聚醯亞胺、苯環丁烯(BCB)、聚苯噁唑(PBO)、或是其它具有合適的電絕緣性質的材料。該絕緣層134係利用PVD、CVD、印刷、旋轉塗覆、帶有固化的燒結、或熱氧化來加以圖案化或是毯覆式沉積。絕緣層134的一部份係藉由一蝕刻製程而被移除，以在絕緣層134中產生露出導電層132的一部份的開口136。開口136係從絕緣層134的頂表面138延伸至絕緣層134的一底表面139。導電層132的另一部份係維持被絕緣層134覆蓋。該部分完成的雙UBM結構接著進行第一次洗滌器清洗。
在圖5d中，一導電層140係藉由利用一圖案化及金屬沉積製程(例如，印刷、PVD、CVD、濺鍍、電解的電鍍、以及無電的電鍍)形成在絕緣層134及導電層132之上並且保形地施加到絕緣層134及導電層132。在一實施例中，導電層140是藉由濺鍍形成的Ti、鈦鎢(TiW)或鉻(Cr)。或者是，導電層140可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它合適的導電材料。導電層140係依循橫跨頂表面138、在開口136內沿著絕緣層134的一側壁、以及在開口136內橫跨導電層132的頂表面之絕緣層134的輪廓。導電層140係包含一在開口136內並且在導電層132之上的區域142。區域142係實質平坦的，並且小於導電層132的一區域。導電層140係運作為用於之後形成的凸塊之一第一UBM層。該部分完成的雙UBM結構接著進行第二次洗滌器清洗。
在圖5e中，一絕緣或保護層144係利用PVD、CVD、網版印刷、旋轉塗覆、噴塗、燒結或熱氧化來加以沉積或塗覆在導電層140之上並且保形地施加到導電層140。在一實施例中，絕緣層144係包含聚醯亞胺、PBO或BCB。或者是，絕緣層144係包含一或多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似絕緣及結構性質的材料。絕緣層144的一底表面146係依循導電層140的輪廓。絕緣層144的頂表面148是平的且實質平行於主動表面130。於是，絕緣層144在底表面146及頂表面148之間量測的厚度係在晶圓120各處變化。絕緣層144係作用為一用於之後形成的第二UBM層的基底。
圖5f係展示絕緣層144被對準及顯影，並且該絕緣層的部份係被移除以在該絕緣層中產生開口152及154。開口152係形成在導電層140的區域142之上。開口152係從絕緣層144的一頂表面148、透過該絕緣層而延伸到該絕緣層的底表面146。開口152的一覆蓋區係具有一區域小於導電層140的區域142。開口152係藉由一圖案化及蝕刻絕緣層144的製程來加以形成，並且露出導電層140的一部份。導電層140的另一部份係維持被絕緣層144覆蓋。開口152係提供一用於之後形成的第二UBM層的形成之位置。開口152的側壁係實質垂直或傾斜的。
開口154係形成在導電層132的一覆蓋區之外且在具有H1高度的絕緣層134的一部份之上的絕緣層144的一周邊中。開口154係從絕緣層144的頂表面148、透過該絕緣層而延伸到該絕緣層的一底表面146。絕緣層144在開口154的一周邊內之剩餘的部份係包含一足以用於容納一個之後形成的凸塊之區域。在一實施例中，絕緣層144之剩餘的部份係具有一區域大於導電層132的該區域。
在絕緣層144被圖案化及蝕刻以產生開口152及154之後，該絕緣層係以高溫急速上升(excursion)加以固化。因為絕緣層144是在一第二UBM層的形成之前固化，因此在該高溫急速上升期間在導電層140的Ti以及之後形成的第二UBM層的Cu之間形成IMC的風險係被降低。在固化絕緣層144之後係進行一去渣處理。
在圖5g中，一導電層160係藉由利用一圖案化及金屬沉積製程(例如，印刷、PVD、CVD、濺鍍、電解的電鍍、以及無電的電鍍)以形成在絕緣層144及導電層140之上且保形地施加到絕緣層144及導電層140。在一實施例中，導電層160係包含Ti及Cu、TiW及Cu、或Cr及Cu，並且利用濺鍍或其它合適的金屬沉積製程來加以形成。或者是，導電層160可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、或其它合適的導電材料。導電層160係依循橫跨該導電層的一頂表面、沿著絕緣層144的一側壁、橫跨絕緣層144的頂表面148、沿著在絕緣層144中的開口152內之絕緣層144的一側壁、以及橫跨由開口152所露出的區域142的部份之導電層140的輪廓。導電層160係運作為用於之後形成的凸塊之一第二UBM或凸塊墊。因為導電層160係依循開口152的輪廓並且形成在絕緣層144的一頂表面148之上，因此該絕緣層係形成在導電層160及導電層140的一部份之間，並且分開該些部份。在導電層140及160之間藉由絕緣層144的分開係降低Sn-Cu IMC的形成風險。在例如是圖1中所示的POU 10之習知的POU結構中，來自凸塊24的Sn將會沿著Ni UMB 20的一側壁行進以和UBM Cu 18反應，因而產生Sn-Cu IMC。該雙UBM結構係包含導電層140、絕緣層144以及導電層160，其係降低來自之後形成的凸塊之Sn和UBM Cu反應的風險。在導電層160的形成之後，該部分完成的雙UBM結構係進行一洗滌器清洗製程。
在圖5h中，光阻166係沉積在導電層160之上。光阻166的一底表面168既覆蓋又依循導電層160的輪廓。光阻166的一頂表面170是實質平坦的。光阻166係包含具有一PET支持膜的一DFR材料。該DFR係加以層疊，進行一邊緣清洗，對準在導電層160之上，該PET支撐膜被移除，並且該DFR材料接著加以顯影。該DFR可利用一可見光雷射來加以照射，以形成一所要的圖案。該照射後的DFR材料接著受到一顯影劑，該顯影劑選擇性地溶解該光阻材料之未照射的部份，並且使得該光阻材料之照射的部份為完整的。
於是，圖5h進一步展示光阻166被圖案化及蝕刻以形成開口172。開口172係從光阻166的頂表面170、透過該光阻層延伸至該光阻層的一底表面168。開口172的一覆蓋區係具有一區域大於開口152的一區域並且小於絕緣層144之剩餘的部份。在一實施例中，開口172係包含一覆蓋區小於導電層132的一覆蓋區。開口172係露出導電層160的一部份。導電層160的另一部份係維持被光阻166覆蓋。開口172係提供一用於凸塊材料後續的沉積的位置。在開口172的形成之後，該DFR係進行第一次去渣、硬烤以及第二次去渣。
在圖5i中，一導電的凸塊材料176係利用一蒸鍍、電解的電鍍、無電的電鍍、或網版印刷的製程以沉積在開口172之內而且在導電層160之上。當網版印刷的製程被利用時，凸塊材料176在沉積時是一種膏，並且需要一回焊週期以在光阻層166被移除前固化該凸塊材料。回焊凸塊材料176係固化該膏並且避免該凸塊材料和後續的光阻層166移除一起被移除或洗去。當凸塊材料176利用一蒸鍍、電解的電鍍或無電的電鍍製程來加以沉積時，該凸塊材料係形成硬的凸塊，因而不需要該額外的回焊週期。
在一實施例中，凸塊材料176是無鉛焊料。或者是，凸塊材料176可以是具有一選配的助熔劑材料之任何金屬或其它導電材料，例如，Sn、Ni、Au、Ag、Pb、Bi、及其合金。例如，該焊料材料可以是共晶Sn/Pb、高鉛的、或是無鉛的。
在圖5j中，光阻層166係被移除。在一實施例中，該DFR層係藉由利用電漿或活性氯氣而被移除以露出凸塊材料176的側壁。光阻層166係被剝除，留下凸塊材料176在導電層160之上。
在圖5k中，導電層160係被蝕刻以移除該導電層中由凸塊材料176露出的一部份。導電層160的蝕刻亦移除該導電層在凸塊材料176下的一週邊區域中的一部份。導電層160的週邊部份的移除係形成一在凸塊材料176之下部分但非完全延伸的凹處180。因此，在凹處180的形成之後，凸塊材料176係延伸出導電層160的一末端部份並且突出於該導電層的上方。導電層160係具有一區域小於導電層132的一區域、或者是，其可具有一區域大於導電層132的一區域。類似地，導電層140係被蝕刻以移除該導電層中由絕緣層144露出的一部份。導電層140的蝕刻亦移除該導電層在絕緣層144之下的一週邊區域中的一部份。導電層140的週邊部份的移除係形成一在絕緣層144之下部分但非完全延伸的凹處182。因此，在凹處182的形成之後，絕緣層144係延伸出導電層140的一末端部份並且突出於該導電層的上方。蝕刻後的導電層140可具有一區域等於或大於導電層132的一區域。在該蝕刻之後，該部分完成的雙UBM結構係進行一洗滌器清洗製程。
在圖51中，凸塊材料176係藉由加熱該凸塊材料超過其熔點來加以回焊，以形成球體或凸塊188。凸塊材料176亦可利用一選配的助熔劑材料來加以回焊。在某些應用中，凸塊188係進行二次回焊以改善至導電層160的電接觸。凸塊188係代表一種可形成在導電層160之上的互連結構類型。該互連結構亦可以使用3-D互連、導電膏、短柱(stud)凸塊、微凸塊、或其它電互連。在凸塊188形成之後，該雙UBM結構係進行一選配的助熔劑清洗，該凸塊係被量測，並且該雙UBM結構係進行一FVI。
於是，相對於習知的聚醯亞胺及無鉛凸塊結構，該雙UBM結構係藉由在覆晶組裝及可靠度測試期間降低裂開及層狀剝落以提供一種改良的低k介電設計。再者，因為絕緣層144是在一第二UBM層的形成之前，並且在第一及第二UBM層的Ti及Cu接觸之前固化，所以在該高溫急速上升期間在該Ti及Cu之間形成IMC的風險係被降低。此外，因為導電層160係依循開口152的輪廓並且形成在絕緣層144的頂表面148之上，所以該絕緣層係形成在導電層140及160的一部份之間，並且分開該些部份。在導電層140及160之間藉由絕緣層144的分開係降低Sn-Cu IMC形成的風險。在例如是圖1中所示的POU 10之習知的POU結構中，來自凸塊24的Sn係沿著Ni UMB 20的一側壁行進以和UBM Cu 18反應，因而產生Sn-Cu IMC。最後，該所述的方法及裝置係比原本由一習知的POU凸塊結構所提供者提供一較寬的製程窗口以供大量製造(HVM)。該較寬的HVM窗口係產生自可被利用以產生該雙UBM結構而無化學損壞問題之各種的應力緩衝材料及剝除器上的增加。
類似於圖51，圖6係展示半導體晶圓196的一部份之放大的橫截面圖，其係聚焦在雙UBM結構194。一導電層198係形成在半導體晶圓196的一主動表面之上並且延伸在該主動表面之上，以使得導電層198的一頂表面產生一不平坦的表面，並且相對於半導體晶圓196具有一非平坦的拓撲。一絕緣或保護層200係形成在半導體晶圓196之上並且直接接觸導電層198的一側壁。絕緣層200不同於圖5c中的絕緣層134是在於不延伸到相鄰的導電層198之上。在圖5c中，絕緣層134確實延伸在相鄰的導電層132之上。圖6進一步展示一導電層202藉由利用一圖案化及金屬沉積製程(例如印刷、PVD、CVD、濺鍍、電解的電鍍、以及無電的電鍍)以形成在絕緣層200及導電層198之上並且保形地施加到絕緣層200及導電層198。在一實施例中，導電層202是藉由濺鍍形成的Ti，具有平拓樸的頂表面及底表面，並且運作為一第一UBM。一絕緣或保護層204係利用PVD、CVD、網版印刷、旋轉塗覆、噴塗、燒結或熱氧化以沉積在導電層202之上並且保形地施加到導電層202。在一實施例中，絕緣層204係包含聚醯亞胺、PBO、或BCB。絕緣層204係在一第二UBM層的形成之前利用一高溫急速上升來加以固化。因此，在該高溫急速上升期間，在導電層202的Ti以及之後形成的第二UBM層的Cu之間形成IMC的風險係被降低。在一實施例中，絕緣層204係具有一區域大於導電層198的一區域。導電層202係被蝕刻以形成一在絕緣層204之下部分但非完全延伸的凹處203。因此，在凹處203的形成之後，絕緣層204係延伸出導電層202的一末端部份並且突出於該導電層的上方。一導電層206係藉由利用一圖案化及金屬沉積製程以形成在絕緣層204及導電層202之上並且保形地施加到絕緣層204及導電層202。在一實施例中，導電層206是一或多層的Ti、Cu、Ni、Ti及Cu、TiW及Cu、或是Cr及Cu，並且是利用濺鍍或其它合適的金屬沉積製程來加以形成。導電層206係運作為一用於之後形成的凸塊之第二UBM或凸塊墊。絕緣層204係形成在導電層202及206的一部份之間，並且分開該些部份。在導電層202及206之間藉由絕緣層204的分開係降低形成Sn-Cu IMC的風險。導電層206係具有一區域小於導電層198的該區域、或者是，可具有一區域大於導電層198的一區域。球體或凸塊208係形成在導電層206之上並且電連接至導電層206。凸塊208係包含任何合適的導電材料，並且在一實施例中是無鉛焊料。在一實施例中，凸塊208的一覆蓋區係具有一區域大於導電層198的一區域且小於絕緣層204。
儘管本發明的一或多個實施例已詳細地解說，熟習此項技術者將會體認到可在不脫離如以下的申請專利範圍中所闡述之本發明的範疇下，對該些實施例進行修改及調適。
10．．．POU
12．．．半導體晶圓
14．．．導電層
16．．．絕緣或保護層
18．．．UBM Cu
20．．．Ni UMB
22．．．絕緣或保護層
24．．．凸塊
30．．．晶圓
32．．．導電層
34．．．絕緣或保護層
36．．．絕緣或保護層
38．．．導電層
40．．．球體或凸塊
50．．．電子元件
52．．．印刷電路板(PCB)
54．．．導電的信號線路
56．．．打線接合封裝
58．．．半導體晶粒
60．．．球狀柵格陣列(BGA)
62．．．凸塊晶片載體(BCC)
64．．．雙排型封裝(DIP)
66．．．平台柵格陣列(LGA)
68．．．多晶片模組(MCM)
70．．．四邊扁平無引腳封裝(QFN)
72．．．四邊扁平封裝
74．．．半導體晶粒
76．．．接觸墊
78．．．中間載體
80．．．導線
82．．．焊線
84．．．封裝材料
88．．．半導體晶粒
90．．．載波
92．．．底膠填充或環氧樹脂黏著材料
94．．．焊線
96、98．．．接觸墊
100．．．模製化合物或封裝材料
102．．．接觸墊
104．．．凸塊
106．．．中間載體
108．．．主動區域
110．．．凸塊
112．．．凸塊
114．．．信號線
116．．．模製化合物或封裝材料
120．．．半導體晶圓
124．．．半導體晶粒或構件
126．．．切割道
128．．．背表面
130．．．主動表面
132．．．導電層
134．．．絕緣或保護層
136．．．開口
138．．．頂表面
139．．．底表面
140．．．導電層
142．．．區域
144．．．絕緣或保護層
146．．．底表面
148．．．頂表面
152、154．．．開口
160．．．導電層
166．．．光阻
168．．．底表面
170．．．頂表面
172．．．開口
176．．．導電的凸塊材料
180．．．凹處
182．．．凹處
188．．．球體或凸塊
194．．．雙UBM結構
196．．．半導體晶圓
198．．．導電層
200．．．絕緣層
202．．．導電層
203．．．凹處
204．．．絕緣或保護層
206．．．導電層
208．．．凸塊
圖1係描繪一習知的POU結構；
圖2係描繪一習知的具有無鉛焊料的聚醯亞胺之結構；
圖3係描繪一安裝到其表面之不同類型的封裝的印刷電路板(PCB)；
圖4a-4c係描繪安裝到該PCB的代表性半導體封裝之進一步細節；
圖5a-5l係描繪一種雙UBM結構；以及圖6係描繪該雙UBM結構的一替代實施例。
120．．．半導體晶圓
132．．．導電層
134．．．絕緣或保護層
138．．．頂表面
139．．．底表面
140．．．導電層
144．．．絕緣或保護層
146．．．底表面
148．．．頂表面
160．．．導電層
180．．．凹處
182．．．凹處
188．．．球體或凸塊

Claims (15)

  1. 一種製造一半導體裝置的方法，其係包括：提供一帶有一接觸墊的基板；在該基板及接觸墊之上形成一第一絕緣層；在該第一絕緣層之上形成一第一凸塊底層金屬(UBM)並且電連接至該接觸墊；在該第一UBM之上形成一第二絕緣層；在該第二絕緣層固化之後，在該第二絕緣層之上形成一第二UBM，該第二UBM係電連接至該第一UBM以使得該第二絕緣層係在該第一及第二UBM的部份之間並且分開該些部份；在該第二UBM之上形成一光阻層，並且移除該光阻層的一部份以在該接觸墊之上的光阻層中形成一開口；在該光阻層中的該開口之中沉積一導電的凸塊材料；移除該光阻層；藉由從該導電的凸塊材料下方移除該第二UBM的一週邊部份以在該導電的凸塊材料和該第二絕緣層之間形成一第一凹處使得該導電的凸塊材料突出於該第二UBM的上方；藉由從該第二絕緣層下方移除該第一UBM的一週邊部份以在該第一絕緣層和該基板之間形成一第二凹處使得該第二絕緣層突出於該第一UBM的上方；以及回焊該導電的凸塊材料以形成一球狀凸塊。
  2. 如申請專利範圍第1項之方法，其中該第二絕緣層包 含利用一高溫急速上升加以固化的聚醯亞胺。
  3. 如申請專利範圍第1項之方法，其中該導電的凸塊材料是無鉛的。
  4. 如申請專利範圍第1項之方法，其中該第一UBM包含鈦、鈦鎢或鉻。
  5. 如申請專利範圍第1項之方法，其中該第二UBM包含鈦及銅、鈦鎢及銅、或是鉻及銅。
  6. 一種製造一半導體裝置的方法，其係包括：提供一基板，其包含形成於該基板的一表面之上的一接觸墊；在該基板之上形成一第一凸塊底層金屬(UBM)並且電連接至該接觸墊；在該第一UBM之上形成一絕緣層；在該絕緣層之上形成一第二UBM並且接觸該第一UBM且在該接觸墊之一覆蓋區域中；在形成該絕緣層之後藉由移除一部分的該第一UBM而形成一第一凹處在該絕緣層和基板之間；以及在該第二UBM之上形成一凸塊，其中該絕緣層被配置在該第一UBM和該第二UBM之間且在該凸塊的一覆蓋區中。
  7. 如申請專利範圍第6項之方法，進一步包含：利用一高溫急速上升來固化該絕緣層；以及在該高溫急速上升之後形成該第二UBM。
  8. 如申請專利範圍第6項之方法，其中該凸塊是無鉛 的。
  9. 如申請專利範圍第6項之方法，其中該第一UBM包含鈦、鈦鎢或鉻並且該第二UBM包含鈦及銅、鈦鎢及銅、或是鉻及銅。
  10. 如申請專利範圍第6項之方法，其中該第一UBM係包含一區域，其大於該接觸墊的一區域。
  11. 一種半導體裝置，其係包括：帶有一接觸墊的一基板；具有一區域大於該接觸墊的一區域之一第一凸塊底層金屬(UBM)，其係形成在該基板之上並且電連接至該接觸墊；形成在該第一UBM之上的一絕緣層；形成在該絕緣層之上並且電連接至該第一UBM的一第二UBM，以使得該絕緣層係在該第一及第二UBM的部份之間；形成在該第二UBM之上的一凸塊；以及形成在該第一UBM中的該絕緣層下方的一第一凹處。
  12. 如申請專利範圍第11項之半導體裝置，其中該絕緣層是高溫固化的聚醯亞胺。
  13. 如申請專利範圍第11項之半導體裝置，其中該凸塊是無鉛的。
  14. 如申請專利範圍第11項之半導體裝置，其中該第一UBM包含鈦、鈦鎢或鉻並且該第二UBM包含鈦及銅、鈦鎢及銅、或是鉻及銅。
  15. 如申請專利範圍第11項之半導體裝置，其中該凸塊突出於該第二UBM的上方，並且該絕緣層突出於該第一UBM的上方。
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