TWI469291B - Semiconductor substrate mounting substrate and manufacturing method thereof - Google Patents

Semiconductor substrate mounting substrate and manufacturing method thereof Download PDF

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TWI469291B
TWI469291B TW100120040A TW100120040A TWI469291B TW I469291 B TWI469291 B TW I469291B TW 100120040 A TW100120040 A TW 100120040A TW 100120040 A TW100120040 A TW 100120040A TW I469291 B TWI469291 B TW I469291B
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substrate
layer
metal
layered
semiconductor element
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TW100120040A
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TW201214645A (en
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Hidehiko Kamohar
Juntarou Mikami
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Description

半導體元件裝載用基板及其製造方法
本發明係有關於裝載(load)以鍍金屬作業所作成的端子(terminal)部門的半導體元件(semiconductor element)的基板及其製造方法。
過去，在導電性基板的一個表面上，作成特定的阻抗圖案層(resistant pattern layer)，從該阻抗圖案層顯露出來(expose)的導電性基板的表面上，超過阻抗圖案層的厚度，將導電性金屬作電沉積(electrodeposition)；上端部份邊緣部位具有突出部份的半導體元件裝載用金屬層(metal layer)和電極層(electrode layer)個別獨立，平行排列作成後，除去阻抗圖案層，在金屬層上裝載半導體元件，半導體元件上的電極和電極層藉由接合打線(bonding wire)而電力地連接；半導體元件裝載部份以樹脂封裝後，除去基板，得到金屬層和電極層個別背面露出的樹脂封裝體，這種半導體裝置的製造方法已廣為人知《例如，參照專利文獻1》。
依據專利文獻1所記載之半導體裝置的製造方法，因為突出部份是位於封裝樹脂難以進入的地方，藉由錨點作用(anchor effect)，提高金屬層與電極層和封裝樹脂的結合力，在後作業中，拉離基板之際，金屬層和電極層的必要零件不會留在基板上， 以埋入樹脂封裝體這一側的形態被複製下來，可以防止金屬層和電極層的偏移(slippage)或欠缺(lack)等結果。
又，藉由跨越金屬層及電極層的上端部份邊緣的全周圍所形成的特有的突出形狀，可以阻止通過從半導體裝置內面來的金屬層和電極層的各層與封裝樹脂的交界部分而侵入的水分，做到極優的抗潮溼性(resistance of moisture)。
但是，專利文獻1所記載的製造方法中，因為跨越阻抗圖案層實施電沉積，結果超過阻抗圖案層厚度部份的電沉積卻變成完全沒有阻抗圖案層約束(restriction)的狀態，很容易受到電流密度(electric current density)分布等的影響，保持突出部份的固定長度就有困難，也有金屬層和電極層與封裝樹脂的黏合力發生不平均的問題。又，因為金屬層和電極層的上表面也變成完全沒有約束的電沉積，上表面不是平面而是形成半球面狀，也容易發生接合打線連接不佳的問題。
再者，從前，在專利文獻1記載的半導體裝置製造方法之外，為人所知的裝載半導體元件的基板的製造方法，如：在導電性基板的一個表面上，施作特定圖案，做成阻抗圖案層，在從阻抗圖案層露出的基板的表面上，於不超越阻抗圖案層厚度的範圍內，將包含下層、中間層和上層的3層以上形成的導電性金屬鍍上(plating)後，除去阻抗圖案層，施予蝕刻(etching)處理，進行將前述中間層的寬度比前述下層和上層縮小的加工作業，藉此使其橫斷面形狀是中間層為凹狀的半導體元件裝載用金屬層 《底墊(pad)部門》與電極層《端子(terminal)部門》個別獨立、並排作成後，金屬層上裝載半導體元件，半導體元件上的電極與電極層藉由打線接合而電力地連接；半導體元件裝載部分以樹脂封裝後，除去基板，得到金屬層和電極層的各內面露出的樹脂封裝體，這種半導體元件裝載用基板的製造方法已為人所熟知《例如，參照專利文獻2》。
依據專利文獻2所記載的半導體元件裝載用基板的製造方法，因為金屬層和電極層的中間層係作成比上下層較小的形態，封裝樹脂與金屬層和電極層呈現極優的黏合性；又，因為基板上最初作成的下層以鍍金方式作成，與基板的黏合性提高，可以防止封裝樹脂在基板和下層之間回滲。
再者，因為沒有超過阻抗圖案層厚度做電鍍，金屬層和電極層的橫向大小均勻，與封裝樹脂的結合力安定且提高，電極層的上表面平坦，則打線接合性極優，可以充分對應半導體裝置的小型化或薄型化。
先前技術之文獻 專利文獻 專利文獻1
特開2002-9196號公報
專利文獻2
特開2009-135417號公報
但是，專利文獻2所記載的結構組成，由於必須將多種類導電性金屬作多層電鍍，使得該作業變的繁瑣複雜，一直留下降低成本的課題。
有鑑於前述之先前技術的問題，本發明之目的係提供一種半導體元件裝載用基板及其製造方法，係端子部門與封裝樹脂的結合力或與打線的連接性均極優，可以降低製造成本，也可以充分對應半導體裝置的小型化或薄型化的半導體元件裝載用基板及其製造方法。
依據本發明之半導體元件裝載用基板，其特徵為：具有使用相同種類的金屬或合金所構成的複數層狀的層狀部門而相鄰層金屬的平均結晶粒子直徑不同；並且，在前述層狀部門的側面，在相鄰層金屬處形成有高低差的凹下部份；至少具有端子部門。又，於本發明之半導體元件裝載用基板，前述層狀部門以3層以上構成是較合於理想的；又，於本發明之半導體元件裝載用基板，前述層狀部門中，在前述相鄰層金屬的前述相同種類的金屬或合金的平均結晶粒子直徑的差是0.5微米(μm)以上，則較合於理想。
再者，依據本發明之半導體元件裝載用基板的製造方法，包含：層狀部門形成作業、以及，高低差階梯形成作業。層狀部門形成作業，相對於具有至少含有用來形成端子部門區域的特定露出區域(exposure area)的阻抗圖案層所作成的導電性基板而言，藉由施作鍍金屬處理，保持阻抗圖案層厚度以下的厚度而作成層狀部門，係在前述導電性基板的露出區域，使用相同種類金屬或合金的相鄰層金屬的平均結晶粒子直徑不相同的複數層狀所構成的層狀部門之層狀部門形成作業；高低差階梯形成作業，相對於前述層狀部門以層狀部門形成作業為介質所形成的導電性基板而言，藉由施予蝕刻加工，於前述層狀部門側面，在相鄰層金屬處形成有高低差的凹下部份之高低差階梯形成作業。以具有層狀部門形成作業及高低差階梯形成作業為特徵。
又，本發明之半導體元件裝載用基板的製造方法，於前述層狀部門形成作業中，由於變更電流密度、施作鍍金屬處理，使前述層狀部門中相鄰層中的前述相同種類金屬或合金的平均結晶粒子直徑產生變化，則較為理想。
依據本發明，則製造成本可以降低，雖然此製造方法是簡單的程序，但是端子部門與封裝樹脂的結合性極優，在從樹脂封裝體將基板分離之際，不會留下已作成的鍍金屬層；又，端子部門與接合打線的連接性極優，可以得到很高可靠性的半導體元件裝 載用基板及其製造方法。
藉由實施例的說明，將關於本發明的作用成果加以說明。
依據本發明之半導體元件裝載用基板及其製造方法，由於係藉由將平均結晶粒子直徑不同的相同金屬或合金施行電鍍所作成的端子部門中的層狀部份，為了作成層狀部份，使用的鍍金屬液只要1種即可，鍍金屬裝置也無須準備多種，也變的容易管理。
構成此層狀部分的平均結晶粒子直徑不同的鍍金屬層，對於蝕刻液的溶解性也不同，粒子直徑較小者溶解較為快速。此因為蝕刻係沿著結晶粒邊界(Grain boundary)進入，結晶粒邊界較多的較小平均結晶粒子直徑層就會優先地(preferentially)溶解。
像這樣所得到的端子部門，其側面上相鄰金屬處就形成有高低差如階梯般的凹下部份。因此，依據本發明，如同專利文獻1之製造方法，藉由超越阻抗圖案層的厚度施行電鑄法(electrotyping)，不會形成突出部份，可以提高與封裝樹脂的結合性。又，因為沒有超越阻抗圖案層的厚度施行電鑄法，層狀部份的上表面可以平坦地作成，與接合打線的連接性也變的極優。
圖1(a)、(b)係本發明的一個實施型態相關之半導體元件裝載用基板中的端子部門的概略剖面圖。本發明的一個實施型態相關之半導體元件裝載用基板，在基板1上，最上層和最下層係由鍍 金層13所構成，在鍍金層13之間，係具有由平均結晶粒子直徑較大的鍍鎳(nickel plating)層10和平均結晶粒子直徑較小的鍍鎳層11層疊而成的層狀部份12；藉由施行蝕刻加工，層狀部份12在層疊的側面，相鄰層的金屬中，平均例子直徑較小的一方的鍍鎳層11，相對於平均例子直徑較大的鍍鎳層10，其側面形成凹下狀態的階段差。
再者，圖1(a)係做為該實例相關半導體元件裝載用基板，端子部門3的層狀部份12係由4層平均例子直徑較大的鍍鎳層10和3層平均例子直徑較小的鍍鎳層11所構成，圖1(a)係顯示該狀態之圖示；(b)係做為其他實例相關半導體元件裝載用基板，端子部門3的層狀部份12係由2層平均例子直徑較大的鍍鎳層10和1層平均例子直徑較小的鍍鎳層11所構成，(a)係顯示該狀態之圖示。
其次，在半導體裝置的製造作業中，說明本發明之半導體元件裝載用基板的製造方法的一個實施型態。圖2係一個說明圖，包含本發明的一個實施型態相關之半導體元件裝載用基板的製造方法，以剖面顯示半導體裝置的製造作業。
在本發明之半導體元件裝載用基板製造之際，其前置作業，例如，不鏽鋼製成的導電性基板1的兩面上，貼上感光性乾性被膜(Photosensitive Dry Films)作成的阻抗遮罩。然後，在基板1的一側的表面的阻抗2上，覆蓋上玻璃遮罩(glass mask)《在圖示中省略未顯示》，其上作成具有鍍金屬用露出區域的遮罩圖 案，經過施行曝光、顯影處理，具有至少包含端子部門形成用之區域的特定露出區域的阻抗圖案層2a就作成了《圖2(a)》。又，在圖2的實例中，露出區域除了端子部門形成用之區域2a1以外，還有半導體元件裝載部門《底墊部門》形成用之區域2a2。
其次，對於已作成阻抗圖案層2a的基板1，施行鍍金屬前處理作業後，在露出區域2a1、2a2上施行鍍金作業。
接著，在已施行鍍金作業的露出區域2a1、2a2上，使用相同種類金屬或合金例如鎳等，進行鍍金屬處理，作成層疊起來而相鄰層金屬的平均結晶粒子直徑不同的疊層，舉例來說，如圖1(a)、(b)所示，作成構造為複數層狀的層狀部份12，其厚度低於阻抗圖案層2a厚度。
接著，在已作成的層狀部份12上，施行鍍金作業《圖2(b)》。
其次，將形成在基板1兩面上的阻抗遮罩2a、2b剝取除去，浸泡在使鎳溶解的液體忠一定時間，藉此施行蝕刻加工處理。經過此程序，如圖2(c)所示，在基板1上製備端子部門3和半導體元件裝載部門《底墊部門》4，半導體元件裝載用基板就製作完成了。此時，如上所述，構成層狀部份12的平均結晶粒子直徑不同的鍍金屬層10、11，因為對於蝕刻液的溶解度不同，結晶粒子直徑較小的層溶解較快，在層狀部份12的側面上，在相鄰層10、11的金屬上，形成有高低差階梯的凹下部分《圖2(d)》。
如此操作，即可得到本發明之半導體元件裝載用基板。
在半導體裝置製造之際，在前述製造方法所得到之半導體元 件裝載用基板上的特定位置《圖2之實例中半導體元件裝載部門4》處，裝載半導體元件5，半導體元件5的電極和端子部門3以接合打線連接後，在基板上以打線6連接的半導體元件5和端子部門3的這一側，用樹脂7封裝起來《圖2(e)》。
其次，封裝的樹脂7硬化以後，將導電性基板1從樹脂封裝體取下；經此作業，得到端子部門3和半導體元件裝載部門4的半導體元件5這一側以樹脂封裝、而其背面露出的半導體裝置《圖2(f)》。
再者，本發明之半導體裝載用基板，如圖2所示，並未限定其構造為製備端子部門3和半導體元件裝載部門4，也適用於如圖3所示之半導體裝置之製造，僅有端子部門3而沒有半導體元件裝載部門4的構造也可以。
如圖3所示之半導體裝置製造之際，對於前述圖示未顯示之導電性基板上只有作成端子部門的本發明之半導體元件裝載用基板而言，係將半導體元件直接裝載於導電性基板的特定位置上，半導體元件的電極和端子部門以接合打線連接後，基板上以打線連接的半導體元件和端子部門這一側，用樹脂封裝起來。
然後，封裝的樹脂硬化以後，將導電性基板從樹脂封裝體取下；經此作業，得到端子部門3和以打線6連接的半導體元件5這一側以樹脂封裝、而其背面露出的半導體裝置。
【實施例1】
實施例1係具備圖1(a)所示之構造的半導體元件裝載用基板的實施例。
將板厚度為0.2毫米(mm)的不鏽鋼《SUS430》作為基板1，進行除油脂(degreasing)、酸洗(pickling；acid cleaning)處理以後，藉由貼合輪(Laminating Roll)，將厚度為0.050毫米的感光性乾膜光阻(photosensitive dry film resist)黏貼在基板1的兩面上，在基板1的一側表面的乾膜光阻上覆蓋作成鍍金屬遮罩圖案的玻璃遮罩，然後從其上方利用紫外線照射使其曝光，進行顯像處理，作成藉由乾膜光阻的特定圖案所形成的阻抗遮罩2a，而基板1的背面側的表面上，作成全面覆蓋的阻抗遮罩2b《圖2(a)》。
其次，相對於從基板1的阻抗遮罩2a露出的區域2a1、2a2，施行鍍金屬前處理後，實施厚度為1微米(μm)之鍍金，接著，於其上，使用氨基磺酸鎳(nickel aminosulfonate；nickel sulfaminate)浴實施鍍鎳，在電流密度為15安培/平方分米(A/dm2)，形成平均結晶粒子直徑為0.8微米的鍍鎳層10，其厚度為5微米；接著，在電流密度為5安培/平方分米，形成平均結晶粒子直徑為0.3微米的鍍鎳層11，其厚度為5微米。更進一步，在其上同樣地實施，平均結晶粒子直徑為0.8微米的鍍鎳層10和平均結晶粒子直徑為0.3微米的鍍鎳層11交互地層疊起來，作成層疊部門12，在其上實施3微米厚度的鍍金作業。經由此作業，作成平均結晶粒子直徑為0.8微米的鍍鎳層10有4層、平均結晶 粒子直徑為0.3微米的鍍鎳層11有3層、最上層和最下層為鍍金層13，構成端子部門3《圖2(b)》。
其次，剝除在基板1的兩面上所作成的阻抗遮罩2a1、2a2《圖2(c)》，使用可溶解鎳的溶液《例如，MEC公司製造之NH-1860系列》，在室溫下，藉由0.5分鐘、1.5分鐘、2.5分鐘、3.5分鐘的時間作浸泡處理，端子部門3側面的鍍鎳層10、10處，形成約0.3~2.8微米的高低差《圖2(d)》，此高低差係利用平均結晶粒子直徑較小的鍍鎳層11的蝕刻速度比平均結晶粒子直徑較大的鍍鎳層10的蝕刻速度較快所作成的；該浸泡時間與高低差的結果顯示在圖4。
為了判定黏合性，以上述作業為媒介所得到的半導體元件裝載用基板上，使用黏晶粒(die bond)用的黏貼漿糊(paste)，將半導體元件5裝載上去，半導體元件5的電極和端子部門3以接合打線6連接後，用樹脂7實行封裝《圖2(e)》，封裝樹脂硬化後，將作為基板1的不鏽鋼從封裝樹脂剝取下來《圖2(f)》。
詳細觀察不鏽鋼被剝取下來的這一側，其結果，實施浸泡處理0.5分鐘，端子部門3側面的鍍鎳層形成約0.3微米的高低差階梯的半導體元件裝載用基板，在不鏽鋼這一側形成的鍍金屬層，隨處可見殘留部份，可以確認端子部門3與封裝樹脂7的黏合性很低；但是，實施浸泡處理1.5分鐘以上，端子部門3側面的鍍鎳層形成約1微米以上的高低差階梯的半導體元件裝載用基板，在不鏽鋼這一側形成的鍍金屬層，沒有殘留部份，又，從封 裝樹脂7也沒有端子部門3浮起或脫落的現象，可以確認該黏合性係良好地保持。
【比較例1】
比較例1係相對於實施例1之半導體元件裝載用基板的比較例。
與實施例相同，用不鏽鋼作為基板，作成阻抗遮罩，進行鍍金屬前置處理；其次，實施厚度為1微米的鍍金作業，接著，於其上，使用氨基磺酸鎳(nickel aminosulfonate；nickel sulfaminate)浴進行鍍鎳，在電流密度為15安培/平方分米(A/dm2)，形成平均結晶粒子直徑為0.8微米的鍍鎳層，其厚度為5微米；接著，在電流密度為10安培/平方分米，形成平均結晶粒子直徑為0.5微米的鍍鎳層11，其厚度為5微米。更進一步，在其上同樣地實施，平均結晶粒子直徑為0.8微米的鍍鎳層和平均結晶粒子直徑為0.5微米的鍍鎳層交互地層疊起來，在其上實施3微米厚度的鍍金作業。經由此作業，作成平均結晶粒子直徑為0.8微米的鍍鎳層有4層、平均結晶粒子直徑為0.5微米的鍍鎳層有3層、最上層和最下層為鍍金層，構成端子部門。
接著，與實施例1相同，剝下除去阻抗遮罩，使用可溶解鎳的溶液，在室溫下進行1.5分鐘的浸泡作業，但是在端子部門的鍍鎳層側面，只能得到0.3微米程度的高低差階梯。因此，可以判定：與實施例1的結果比較，比較例1生產性不佳，而且在0.3 微米程度的高低差階梯，其黏合性也很低。
【實施例2】
實施例2係具備圖1(b)所示之構造的半導體元件裝載用基板的實施例。
與實施例相同，用不鏽鋼作為基板，作成阻抗遮罩，不進行鍍金屬前置處理；實施厚度為1微米的鍍金作業，接著，於其上，使用氨基磺酸鎳浴進行鍍鎳，在電流密度為15安培/平方分米(A/dm2)，形成平均結晶粒子直徑為0.8微米的鍍鎳層，其厚度為10微米；接著，於其上，在電流密度為5安培/平方分米，形成平均結晶粒子直徑為0.3微米的鍍鎳層，其厚度為15微米；更進一步，在其上，在電流密度為15安培/平方分米(A/dm2)，形成平均結晶粒子直徑為0.8微米的鍍鎳層，其厚度為10微米；在其上實施3微米厚度的鍍金作業。
接著，與實施例1相同，剝下除去阻抗遮罩，使用可溶解鎳的溶液，在室溫下進行1.5分鐘的浸泡作業；裝載半導體元件；裝載半導體元件的電極和端子部門以接合打線連接；進行樹脂封裝；將不鏽鋼從樹脂封裝體拉開取下；觀察在不鏽鋼側的表面，其結果是完全沒有鍍金屬層殘留部份。
【產業上的可能應用】
本發明之半導體裝載用基板及其製造方法，可以降低製造成 本，雖然該製造方法是一個簡單的作業程序，但是端子部門與封裝樹脂的黏合性極優，將基板從樹脂封裝體拉開取下之際，不會殘留已作成的鍍金屬層，作為可靠性(Reliability)極高的半導體裝載用基板及其製造方法，能產生極為優良的結果，在相關產業領域中的廣泛應用是可以期待的。
1‧‧‧基板
2‧‧‧阻抗遮罩
2a‧‧‧作成阻抗圖案層的阻抗遮罩
2a1‧‧‧端子部門形成用之露出區域
2a2‧‧‧半導體元件搭載部門形成用之露出區域
2b‧‧‧覆蓋基板全表面的阻抗遮罩
3‧‧‧端子部門
4‧‧‧半導體元件搭載部門
5‧‧‧半導體元件
6‧‧‧打線
7‧‧‧樹脂
10‧‧‧平均結晶粒子直徑較大層
11‧‧‧平均結晶粒子直徑較小層
12‧‧‧層狀部門
13‧‧‧鍍金層
【圖1】圖1係顯示本發明的一個實施型態相關之半導體元件裝載用基板中的端子部門的概略結構組成之剖面圖，(a)係顯示某一個實例相關之半導體元件裝載用基板的端子部門的剖面圖，(b)係顯示其他的一個實例相關之半導體元件裝載用基板的端子部門的剖面圖。
【圖2】圖2係一個說明圖，包含本發明的一個實施型態相關之半導體元件裝載用基板的製造方法，以剖面顯示半導體裝置的製造作業；(a)係顯示在導電性基板上，阻抗遮罩(resist mask)作成的狀態；(b)係顯示在(a)之已作成阻抗遮罩的基板的露出區域上，包含層狀部門的鍍金屬層作成的狀態；(c)係顯示：從作成鍍金屬層的基板除去阻抗遮罩，施予蝕刻處理，作成本發明的一個實施型態相關之半導體元件裝載用基板的狀態；(d)係放大圖，顯示製備在(c)之半導體元件裝載用基板上的層狀部門的側面， 作成高低差；(e)顯示在(c)之半導體元件裝載用基板上裝載半導體元件，半導體元件的電極和端子部門以接合打線連接後，用樹脂將這些封裝的狀態；(f)係顯示從(e)所示之封裝樹脂體，將導電性基板剥離，完成後半導體裝置的狀態。
【圖3】圖3係本發明之變形實例，使用只有端子部門、沒有半導體裝載部門的半導體元件裝載用基板所製造者，係顯示該半導體裝置的概略結構組成之剖面圖。
【圖4】圖4係圖表，顯示：在本發明之實施例1相關之半導體元件裝載用基板製造時，對於使用相同種類金屬或合金，作成相鄰層金屬的平均結晶粒子直徑不同、由複數層狀所構成之層狀部門的導電性基板而言，施予蝕刻加工時的蝕刻液浸泡時間與相鄰層金屬高低差的關係。
1‧‧‧基板
3‧‧‧端子部門
10‧‧‧平均結晶粒子直徑較大層
11‧‧‧平均結晶粒子直徑較小層
12‧‧‧層狀部門
13‧‧‧鍍金層

Claims (5)

  1. 一種半導體元件裝載用基板，係：具有使用相同種類金屬或合金、相鄰層金屬的平均結晶粒子直徑不同的複數層狀所構成的層狀部門，並且，在前述層狀部門的側面，於前述相鄰層金屬處形成高低差階梯的凹下部份；至少具有端子部門為其特徵者。
  2. 如申請專利範圍第1項所述之半導體元件裝載用基板，其中前述層狀部門係由3層以上的層狀部分所構成為其特徵者。
  3. 如申請專利範圍第1項所述之半導體元件裝載用基板，其中前述層狀部門的前述相鄰層金屬的前述同種類金屬或合金的平均結晶粒子直徑，其差異是0.5微米以上為其特徵者。
  4. 一種半導體元件裝載用基板的製造方法，係包含：相對於具有至少含有用來形成端子部門區域的特定露出區域(exposure area)的阻抗圖案層所作成的導電性基板而言，藉由施作鍍金屬處理，保持阻抗圖案層厚度以下的厚度而作成層狀部門，係在前述導電性基板的露出區域，使用相同種類金屬或合金的相鄰層金屬的平均結晶粒子直徑不相同的複數層狀所構成的層狀部門之層狀部門形成作業；相對於前述層狀部門以層狀部門形成作業為媒介所形成的導電性基板而言，藉由施予蝕刻加 工，於前述層狀部門側面，在相鄰層金屬處形成有高低差的凹下部份之高低差階梯形成作業。以具有層狀部門形成作業及高低差階梯形成作業為其特徵者。
  5. 如申請專利範圍第4項所述之半導體元件裝載用基板的製造方法，其中前述層狀部門形成作業中，藉由電流密度改變而施行鍍金屬處理，前述層狀部門的相鄰層金屬的前述相同金屬或合金的平均結晶粒子直徑產生變化為其特徵者。
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