TWI664706B - 包含可去除載體的可佈線電鑄襯底 - Google Patents

包含可去除載體的可佈線電鑄襯底 Download PDF

Info

Publication number
TWI664706B
TWI664706B TW107112468A TW107112468A TWI664706B TW I664706 B TWI664706 B TW I664706B TW 107112468 A TW107112468 A TW 107112468A TW 107112468 A TW107112468 A TW 107112468A TW I664706 B TWI664706 B TW I664706B
Authority
TW
Taiwan
Prior art keywords
metal layer
layer
carrier
item
patent application
Prior art date
Application number
TW107112468A
Other languages
English (en)
Other versions
TW201839945A (zh
Inventor
達志 陳
耀輝 關
吉奧 荷西 阿蘇摸 維拉埃斯平
儒瓏 林
航 任
Original Assignee
新加坡商先進科技新加坡有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新加坡商先進科技新加坡有限公司 filed Critical 新加坡商先進科技新加坡有限公司
Publication of TW201839945A publication Critical patent/TW201839945A/zh
Application granted granted Critical
Publication of TWI664706B publication Critical patent/TWI664706B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

本發明係關於通過提供載體並將圖案化的第一金屬層鍍覆到載體上來製造用於組裝半導體封裝體的可佈線電鑄襯底，所述第一金屬層被配置為用作組裝的半導體封裝體中的表面安裝焊盤或輸入/輸出焊盤。將包含銅的圖案化的第二金屬層鍍覆在第一金屬層上，並且將配置用於安裝多個半導體晶片的第三金屬層鍍覆在第二金屬層上。然後去除載體以暴露第一金屬層。

Description

包含可去除載體的可佈線電鑄襯底
本發明涉及在電子設備的組裝和封裝中使用的襯底。
傳統上，通過將半導體晶片組裝在引線框形式的襯底上來製造半導體封裝體。這種襯底在晶片鍵合、引線鍵合以及晶片和引線鍵合的封裝期間支撐半導體晶片。封裝之後，將襯底和包封劑切割或分離以形成分離的半導體封裝體。
在可攜式設備、可穿戴設備和其他消費產品的驅動下，半導體封裝行業越來越需要生產外形尺寸更小的設備。要做到這一點，需要更緊湊且具有可佈線電路的更薄的襯底來實現這種具有成本效益的先進封裝解決方案的目的。
例如，名稱為“用於精細間距微型化的半導體封裝體及其製造方法(“Semiconductor Package for Fine Pitch Miniaturization and Manufacturing Method thereof)”的第7,795,071號美國專利公開了精細間距半導體製造封裝襯底以及使用該襯底的技術。導電跡線被嵌入載體中並被絕緣層隔離，之後載體被選擇性蝕刻以產生成品。
所述方法的問題在於，對於非常薄的封裝襯底(例如100μm或更薄的封裝襯底)來說，在製造襯底期間以及在其在半導體組裝過程中的處理期間遇到許多挑戰，諸如襯底中的翹曲或裂縫。這導致產量降低和成本增加，並且使半導體封裝體更薄的能力受到限制。
因此，本發明的目的是尋求提供一種用於半導體組裝和封裝的襯底，其適合於組裝薄封裝體並且在半導體組裝過程的處理期間固有地更加魯棒(robust)。
根據本發明的第一方面，提供了一種製造用於組裝半導體封裝體的可佈線電鑄襯底的方法，包括以下步驟：提供載體；將圖案化的第一金屬層鍍覆到所述載體上，所述第一金屬層被配置為用作組裝的半導體封裝體中的表面安裝焊盤或輸入/輸出焊盤；在所述第一金屬層上鍍覆包含銅的圖案化的第二金屬層；在所述第二金屬層上鍍覆第三金屬層，所述第三金屬層被配置為用於將多個半導體晶片安裝到所述第三金屬層上；然後去除所述載體以暴露所述第一金屬層。
根據本發明的第二方面，提供了一種用於組裝半導體封裝體的可佈線電鑄襯底，所述襯底包括：載體；第一金屬層，所述第一金屬層被配置為用作組裝的半導體封裝體中的表面安裝焊盤或輸入/輸出焊盤；在所述第一金屬層上的包含銅的第二金屬層；以及在所述第二金屬層上方的第三金屬層，所述第三金屬層被配置為用於將多個半導體晶片安裝到所述第三金屬層上；其中，所述載體能夠去除以暴露所述第一金屬層。
在下文中通過參考示出本發明的特定較佳實施例 的附圖更詳細地描述本發明將是方便的。附圖和相關描述的特殊性不應被理解為取代由申請專利範圍限定的本發明的廣義標識的一般性。
10‧‧‧襯底載體
12‧‧‧第一光刻膠
14‧‧‧暴露部分
16‧‧‧第一金屬層
18‧‧‧中間金屬層
20‧‧‧第二光刻膠層
22‧‧‧暴露部分
24‧‧‧第二金屬層
26‧‧‧第一介電層
30‧‧‧導電晶種層
32‧‧‧第三光刻膠層
34‧‧‧暴露部分
36‧‧‧第三金屬層
38‧‧‧精加工金屬層
40‧‧‧半導體晶片
42‧‧‧鍵合線
44‧‧‧第二介電層
46‧‧‧半導體封裝體
50‧‧‧第三金屬層
54‧‧‧第四光刻膠層
56‧‧‧暴露部
58‧‧‧精加工金屬層
60‧‧‧互連襯底結構
圖1A至圖1P示出了根據本發明較佳實施例的用於製造襯底的技術。
圖2A至圖2D示出了在去除用於支撐半導體晶片的襯底載體之前組裝半導體晶片的方法。
圖3A至圖3G示出了將選擇性表面精加工部結合到製造的襯底的跡線層上。
圖1A至圖1P示出了根據本發明較佳實施例的製造用於組裝半導體封裝體的可佈線電鑄襯底的技術。在圖1A中，提供襯底載體10。襯底載體10由導電材料製成並且較佳地可通過磁力吸引。在一個實施例中，襯底載體10包括不銹鋼，特別是430級的不銹鋼。襯底載體10的表面應首先進行化學處理以在使用之前去除所有污漬、油痕和污染物，以確保它們是乾淨的。
在圖1B中，通過用光敏乾膜層壓和覆蓋襯底載體10的頂表面和底表面，在襯底載體10的表面上形成第一光刻膠層12。在圖1C中，通過將第一光刻膠層12選擇性暴露於紫外光或通過直接鐳射影像處理來圖案化第一光刻膠層12，以在第一光刻膠層12上產生預定義圖案。無論是使用選擇性暴露於紫 外光還是鐳射影像處理，第一光刻膠層12的部分此後被化學地去除，以在第一光刻膠層12中產生暴露部分14。暴露部分14用於暴露襯底載體10位於第一光刻膠層12下面的表面。可選地，然後可以施加化學粗糙化技術以通過去除其暴露表面的一部分來粗糙化襯底載體10的暴露的下表面。
在圖1D中，通過使用圖案化的第一光刻膠層12作為掩模的電鍍技術，在第一光刻膠層12的暴露部分14內形成預定厚度的第一金屬層16。第一金屬層16將包括完成的半導體封裝體中的表面安裝焊盤或輸入/輸出焊盤。因此，第一金屬層16較佳包括金層、金鎳層或金鈀鎳層。之後，在圖1E中，已經用金和/或鎳鍍覆的暴露部分14的其餘部可以用另一種金屬(例如銅)填充以形成與第一光刻膠層12齊平的中間金屬層18。
在圖1F中，通過用光敏乾膜層壓和覆蓋第一光刻膠層12以及第一和中間金屬層16、18，在第一光刻膠層12以及第一和中間金屬層16、18上形成第二光刻膠層20。如圖1G所示，通過將第二光刻膠層20選擇性地暴露於紫外光並化學去除第二光刻膠層20的部分，或通過直接鐳射影像處理、接著化學去除第二光刻膠層20的部分，第二光刻膠層20進一步被圖案化，以在第二光刻膠層20上形成預定義的圖案。該過程在第二光刻膠層20中產生暴露部分22。第二光刻膠層20中的暴露部分22暴露中間金屬層18的部分的相應頂表面。
在圖1H中，通過使用圖案化的第二光刻膠層20作為掩模的電鍍技術，在第二光刻膠層20的暴露部分22中形成第二金屬層24。第二金屬層24可以用作與第一和中間金屬層16、18的連通互連件，使得其定義為在第一和中間金屬層16、18之上形成的並且表面積更小的垂直柱。第二金屬層24實際上可以 由單個或多個金屬層構成，並且較佳地包括銅。
在圖1I中，第一和第二光刻膠層12、20已通過上述任一過程被去除，以顯露第一、中間和第二金屬層16、18、24，之後可模制該多個金屬層。如圖1J所示，形成第一介電層26以包封該多個金屬層16、18、24。第一介電層26包括通過模制技術(例如傳遞模塑、注塑或壓塑成型或者通過薄膜層壓技術)引入的模塑膠。模塑膠可以包含環氧樹脂和二氧化矽填料。該多個金屬層16、18、24已被包覆成型，使得形成尤其覆蓋第二金屬層24的過量的模塑膠層26。
在圖1K中，第一介電層26的過量部分已經被去除以平坦化並且暴露第二金屬層24的頂表面。這種去除可以通過機械平坦化技術(例如研磨或拋光)或通過使用化學平坦化過程來執行。在平坦化之後，如圖1L所示，在第一介電層26和第二金屬層24的表面上形成導電晶種層30。導電晶種層30較佳包含銅，可以通過無電鍍或通過濺射技術形成。
在圖1M中，通過用光敏乾膜層壓和覆蓋導電晶種層30以及襯底載體10的底表面，在導電晶種層30以及襯底載體10的底表面上形成第三光刻膠層32。如圖1N所示，通過將第三光刻膠層32選擇性地暴露於紫外光並且化學地去除第三光刻膠層32的一部分，或者通過直接鐳射影像處理然後化學地去除第三光刻膠層32的一部分，第三光刻膠層32被進一步圖案化，以在第三光刻膠層32上形成預定義的圖案。該過程在第三光刻膠層32中產生暴露部分34。第三光刻膠層32中的暴露部分34暴露下面的導電晶種層30的部分的相應頂表面。
圖1O示出了第三金屬層36和精加工金屬層38，該第三金屬層和精加工金屬層通過使用圖案化的第三光刻膠層 32作為掩模進行電鍍而被連續地填充到第三光刻膠層32的暴露部分34中。第三金屬層36可以包括由諸如銅的單一金屬形成的跡線層，並且精加工金屬層38可以是包括鎳金層、鎳鈀金層或銀層的表面精加工部。在圖1P中，第三光刻膠層32已被去除。導電晶種層30也已經較佳地通過化學蝕刻技術被去除，以在導電晶種層30的尚未鍍覆有任何金屬層的部分處暴露下面的第一介電層26。
圖2A至2D示出了在去除用於支撐半導體晶片40的襯底載體10之前組裝半導體晶片40的方法。如圖2A所示，首先將半導體晶片40鍵合到最上面的精加工金屬層38上。為此，用於晶片附著的環氧樹脂被分配在精加工金屬層38上的晶片附著焊盤區域內，接著放置晶片，然後固化環氧樹脂以牢固地鍵合半導體晶片40。
在圖2B中，半導體晶片40已經通過使用精密電鍵合線42作為連接器的引線鍵合而被電連接到精加工金屬層38的頂部精加工層。鍵合線42通常可以包括金或銅線。或者，半導體晶片40可以通過使用形成在半導體晶片40的底表面上的焊料尖端凸點的倒裝晶片鍵合技術(未示出)來附接，焊料尖端凸點用於附接並形成與精加工金屬層38的電連接。
此後，半導體晶片40、鍵合線42、環氧樹脂、晶片焊盤和佈線跡線被第二介電層44包封，以保護它們免受外部環境的影響，如圖2C所示。包封劑較佳為通過注塑、傳遞模塑或壓塑模制技術引入的模塑膠。
在包封劑被模制以包封半導體晶片和鍵合線42以及其他連接件之後，去除襯底載體10以留下完成的半導體封裝體46。去除襯底載體10應較佳通過機械手段，例如通過剝離。 剝離襯底載體10暴露了包括第一金屬層16的半導體封裝體46的下面的表面安裝層或輸入/輸出焊盤層，用於將半導體封裝體46安裝到其他器件。
圖3A至圖3G示出了將選擇性表面精加工部結合到製造的襯底的跡線層上。在圖3A中，根據圖1N已經形成了圖案化的第三光刻膠層32。在第三光刻膠層32中存在暴露下面的導電晶種層30的部分的相應頂表面的暴露部分34。
在圖3B中，為了形成跡線層，通過使用圖案化的第三光刻膠層32作為掩模的鍍覆技術，在導電晶種層30上沉積第三金屬層50。可選地，可以在暴露部分34內的第三金屬層50上沉積另一銅層直到第三光刻膠層32的高度。
在圖3C中，通過用光敏乾膜層壓並覆蓋第三光刻膠層和第三金屬層50，在第三光刻膠層和第三金屬層50上形成第四光刻膠層54。如圖所示，通過將第四光刻膠層32選擇性暴露於紫外光以及化學去除第四光刻膠層54的部分，或通過直接鐳射影像處理隨後化學去除第四光刻膠層54的部分，第四光刻膠層32進一步被圖案化，以在第四光刻膠層54上產生預定義的圖案。該技術在第四光刻膠層54中產生對應於第三金屬層50的頂表面的某些區域的暴露部分56，以暴露出一些下面的第三金屬層50以用於施加選擇性表面精加工。
在圖3D中，通過使用第四光刻膠層54作為掩模的鍍覆技術，將用於形成表面精加工部的另一精加工金屬層58沉積到暴露部分56中。這種精加工金屬層58可以包括作為表面精加工部的鎳金層、鎳鈀金層或銀層。
然後去除第三光刻膠層32和第四光刻膠層54以形成圖3E中所示的結構，在此之後，去除導電晶種層30的暴露的 部分，以在襯底上形成它們的位置處顯露出第三金屬層50或精加工金屬層58，如圖3F所示。導電晶種層30的去除可以通過化學蝕刻技術來進行。
在圖3G中，襯底載體10已被去除以留下互連襯底結構60，以準備下游封裝技術，包括如上所述的晶片附接和包封。襯底載體10的去除應該較佳通過機械手段，例如通過剝離。剝離襯底載體10將暴露包括第一金屬層16的互連襯底結構60的下面的表面安裝層或輸入/輸出焊盤層，用於將由互連襯底結構60組裝的半導體封裝體安裝到其他器件。
除了具體描述的那些以外，可以容易地對本文描述的本發明進行變化、修改和/或添加，並且應當理解，本發明包括落入以上描述的精神和範圍內的所有這些變化、修改和/或添加。

Claims (15)

  1. 一種製造用於組裝半導體封裝體的可佈線電鑄襯底之方法，包括以下步驟：提供載體；將圖案化的第一金屬層鍍覆到所述載體上，所述第一金屬層被配置為用作組裝的半導體封裝體中的表面安裝焊盤或輸入/輸出焊盤；在所述第一金屬層上鍍覆包含銅的圖案化的第二金屬層；在所述第二金屬層上鍍覆第三金屬層，所述第三金屬層被配置為用於將多個半導體晶片安裝到所述第三金屬層上；以及在將半導體晶片配置於所述第三金屬層上之前，去除所述載體以暴露所述第一金屬層。
  2. 如申請專利範圍第1項所述之方法，其中，所述載體由能夠被磁力吸引的導電材料製成。
  3. 如申請專利範圍第2項所述之方法，其中，所述載體包括430級不銹鋼。
  4. 如申請專利範圍第1項所述之方法，更包括在鍍覆所述第一金屬層之前，通過去除所述載體的暴露表面的一部分來粗糙化所述暴露表面的步驟。
  5. 如申請專利範圍第1項所述之方法，其中，鍍覆所述第一金屬層和所述第二金屬層的步驟通過電鍍進行。
  6. 如申請專利範圍第1項所述之方法，其中，所述第一金屬層包括金層、金鎳層或金鈀鎳層。
  7. 如申請專利範圍第6項所述之方法，更包括在鍍覆所述第二金屬層之前，在所述金層、金鎳層或金鈀鎳層上鍍覆銅層的步驟。
  8. 如申請專利範圍第1項所述之方法，其中，所述第二金屬層具有比所述第一金屬層小的表面積，並且用作與所述第一金屬層的連通互連件。
  9. 如申請專利範圍第1項所述之方法，更包括在鍍覆所述第三金屬層之前，將所述第一金屬層和所述第二金屬層包封在介電材料中的步驟。
  10. 如申請專利範圍第9項所述之方法，更包括以下步驟：平坦化所述介電材料和所述第二金屬層，並在其頂表面上形成導電晶種層，使得所述第三金屬層鍍覆在所述導電晶種層上。
  11. 如申請專利範圍第1項所述之方法，更包括在去除所述載體以暴露所述第一金屬層之前，將多個半導體晶片鍵合到所述第三金屬層上的步驟。
  12. 如申請專利範圍第11項所述之方法，更包括在去除所述載體之前連接所述多個半導體晶片和所述襯底之間的鍵合線的步驟。
  13. 如申請專利範圍第11項所述之方法，更包括在鍵合所述多個半導體晶片之後用介電層包封所述半導體晶片的步驟。
  14. 如申請專利範圍第1項所述之方法，更包括在所述第三金屬層的選定部分上鍍覆包括鎳金層、鎳鈀金層或銀層的表面精加工部的步驟。
  15. 如申請專利範圍第1項所述之方法，其中，通過將所述載體從所述第一金屬層剝離而去除所述載體。
TW107112468A 2017-04-21 2018-04-12 包含可去除載體的可佈線電鑄襯底 TWI664706B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762488267P 2017-04-21 2017-04-21
US62/488,267 2017-04-21

Publications (2)

Publication Number Publication Date
TW201839945A TW201839945A (zh) 2018-11-01
TWI664706B true TWI664706B (zh) 2019-07-01

Family

ID=63854764

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107112468A TWI664706B (zh) 2017-04-21 2018-04-12 包含可去除載體的可佈線電鑄襯底

Country Status (5)

Country Link
US (1) US10475666B2 (zh)
KR (1) KR20180118553A (zh)
CN (1) CN108735680A (zh)
SG (1) SG10201803223YA (zh)
TW (1) TWI664706B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11189516B2 (en) 2019-05-24 2021-11-30 Applied Materials, Inc. Method for mask and substrate alignment
WO2020242611A1 (en) 2019-05-24 2020-12-03 Applied Materials, Inc. System and method for aligning a mask with a substrate
US11756816B2 (en) 2019-07-26 2023-09-12 Applied Materials, Inc. Carrier FOUP and a method of placing a carrier
US10916464B1 (en) 2019-07-26 2021-02-09 Applied Materials, Inc. Method of pre aligning carrier, wafer and carrier-wafer combination for throughput efficiency
US11196360B2 (en) 2019-07-26 2021-12-07 Applied Materials, Inc. System and method for electrostatically chucking a substrate to a carrier
CN113286440B (zh) * 2020-02-19 2022-09-02 何崇文 导线架及其制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080145967A1 (en) * 2006-12-14 2008-06-19 Advanpack Solutions Pte Ltd. Semiconductor package and manufacturing method thereof
TW201214645A (en) * 2010-06-14 2012-04-01 Sumitomo Metal Mining Co Substrate for mounting semiconductor element and method for manufacturing the substrate
WO2013097046A1 (zh) * 2011-12-26 2013-07-04 璩泽明 电极共平面的发光二极管元件、封装结构及光反射结构

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4431123B2 (ja) * 2006-05-22 2010-03-10 日立電線株式会社 電子装置用基板およびその製造方法、並びに電子装置およびその製造方法
US8203167B2 (en) * 2008-03-25 2012-06-19 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and adhesive between base and terminal
SG10201708630YA (en) * 2013-02-21 2017-12-28 Advanpack Solutions Pte Ltd Semiconductor structure and method of fabricating the same
TWI474450B (zh) * 2013-09-27 2015-02-21 Subtron Technology Co Ltd 封裝載板及其製作方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080145967A1 (en) * 2006-12-14 2008-06-19 Advanpack Solutions Pte Ltd. Semiconductor package and manufacturing method thereof
TW201214645A (en) * 2010-06-14 2012-04-01 Sumitomo Metal Mining Co Substrate for mounting semiconductor element and method for manufacturing the substrate
WO2013097046A1 (zh) * 2011-12-26 2013-07-04 璩泽明 电极共平面的发光二极管元件、封装结构及光反射结构

Also Published As

Publication number Publication date
US10475666B2 (en) 2019-11-12
SG10201803223YA (en) 2018-11-29
US20180308710A1 (en) 2018-10-25
TW201839945A (zh) 2018-11-01
CN108735680A (zh) 2018-11-02
KR20180118553A (ko) 2018-10-31

Similar Documents

Publication Publication Date Title
TWI664706B (zh) 包含可去除載體的可佈線電鑄襯底
US8873244B2 (en) Package structure
TWI390683B (zh) 半導體封裝及其製造方法
KR102551034B1 (ko) 반도체 패키지 및 그 제조방법
KR101609016B1 (ko) 반도체 소자용 기판의 제조 방법 및 반도체 장치
TWI612631B (zh) 半導體封裝及封裝半導體裝置之方法
TWI801417B (zh) 半導體元件用基板及其製造方法、半導體裝置及其製造方法
KR20100133310A (ko) 전자 디바이스 패키지 및 제조방법
CN108701660B (zh) 半导体封装衬底及其制造方法
US7745260B2 (en) Method of forming semiconductor package
JP2010118633A (ja) 埋込み型ソルダーバンプを持つプリント基板及びその製造方法
KR101674537B1 (ko) 리드프레임 제조방법과 그에 따른 리드프레임 및 반도체 패키지 제조방법과 그에 따른 반도체 패키지
KR100639737B1 (ko) 회로 장치의 제조 방법
JP4073308B2 (ja) 回路装置の製造方法
TW201541587A (zh) 晶片封裝基板、晶片封裝結構及製作方法
KR101605610B1 (ko) 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
TWI771712B (zh) 封裝基板及其製造方法
KR101579434B1 (ko) 반도체 패키지 제조 방법
TWI590407B (zh) 半導體封裝結構及其製作方法
KR101187913B1 (ko) 반도체 패키지용 리이드 프레임과, 이를 제조하는 방법
US20060284288A1 (en) Wafer and single chip having circuit rearranged structure and method for fabricating the same
KR20100112898A (ko) 플립 칩 반도체 패키지의 제조 방법
JPH10116858A (ja) Ｂｇａ型半導体装置の製造方法
TWI474413B (zh) 晶片封裝結構的製程
US20190164875A1 (en) Premolded substrate for mounting a semiconductor die and a method of fabrication thereof