TW201214645A - Substrate for mounting semiconductor element and method for manufacturing the substrate - Google Patents

Substrate for mounting semiconductor element and method for manufacturing the substrate Download PDF

Info

Publication number
TW201214645A
TW201214645A TW100120040A TW100120040A TW201214645A TW 201214645 A TW201214645 A TW 201214645A TW 100120040 A TW100120040 A TW 100120040A TW 100120040 A TW100120040 A TW 100120040A TW 201214645 A TW201214645 A TW 201214645A
Authority
TW
Taiwan
Prior art keywords
layer
substrate
layered
metal
semiconductor element
Prior art date
Application number
TW100120040A
Other languages
Chinese (zh)
Other versions
TWI469291B (en
Inventor
Hidehiko Kamohar
Juntarou Mikami
Original Assignee
Sumitomo Metal Mining Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co filed Critical Sumitomo Metal Mining Co
Publication of TW201214645A publication Critical patent/TW201214645A/en
Application granted granted Critical
Publication of TWI469291B publication Critical patent/TWI469291B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating

Abstract

Disclosed is a substrate for mounting a semiconductor element, which has a terminal section having excellent bonding performance with a sealing resin and excellent connecting characteristics with a bonding wire, and which can reduce manufacture cost and is sufficiently applicable to miniaturizing and thinning of a semiconductor device. Also disclosed is a method for manufacturing such substrate. The substrate at least has the terminal section (3), which has a layered section (12) configured of a plurality of layers wherein adjacent layers (10, 11) are respectively composed of a same kind of metal or alloy with different average crystal grain sizes, and which has a recessed section formed by etching on the side surface of the layered section (12), said recessed section having a step between the adjacent layers (10, 11).

Description

201214645 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係有關於裝載（load)以鍍金屬作業所作成的端子 (terminal)部門的半導體元件（semiconductor element)的基 板及其製造方法。 【先前技術】 【0002】 過去，在導電性基板的一個表面上，作成特定的阻抗圖案層 (resistant pattern layer )，從該阻抗圖案層顯露出來（pXp〇se) 的導電性基板的表面上，超過阻抗圖案層的厚度，將導電性金屬 作電沉積（electrodeposition);上端部份邊緣部位具有突出部 份的半導體元件裝載用金屬層（metal 1 ay er)和電極層（e 1 ^『〇如 layer)個別獨立，平行排列作成後，除去阻抗圖案層，在金屬層 上裝載半導體元件，半導體元件上的電極和電極層藉由接合打線 (bonding wire)而電力地連接；半導體元件裝載部份以樹脂封 裝後，除去基板，彳于到金屬層和電極層個別背面露出的樹脂封裝 體’這種半賴裝置的製造方法已廣為人知《例如，參照專利文 獻1》。 3 【0003】 201214645 依據專利文獻1所記載之半導體裝置的製造方法，因為突出 部份是位於封裝樹脂難以進入的地方，藉由錨點作用（anchor effect)，提高金屬層與電極層和封裝樹脂的結合力，在後作業 中，拉離基板之際，金屬層和電極層的必要零件不會留在基板上， 以埋入樹脂封裝體這·-側的形態被複製下來，可以防止金屬層和 電極層的偏移（slippage)或欠缺（lack)等結果。 又，藉由跨越金屬層及電極層的上端部份邊緣的全周圍所形 成的特有的突出形狀’可以阻止通過從半導體裝置内面來^金屬 層和電極層的各層與封裝樹脂的交界部分而侵入的水分，做到極 優的抗潮渔性（res i stance of moi sture)。- .&gt; 【0 00 4】 但疋’專利文獻1所§己載的製造方法中，因為跨越阻抗圖案 層實施電沆積，結果超過阻抗圖案層厚度部份的電沉積卻變成完 全沒有阻抗圖案層約束（restriction)的狀態，很容易查到電流 密度（electric current density)分布等的影響，保持突出部 份的固定長度就有困難，也有金屬層和電極層與封裝樹脂的黏合 力發生不平均的問題。又’因為麵層和電極層壯表面也變成 元全沒有約束的電、/儿積，上表面不是平面而是形成半球面狀，也 容易發生接合打線連接不佳的問釋。 4 [0005] 201214645 再者，從前’在專利文獻1記載的半導體裝置製造方法之外， 為人所知的裝載半導體元件板的製造方法，如：在導電性基 板的-個表面上’施作特賴案，做成阻抗圖案層，在從阻抗圖 案層露出的基板的表面上，於不超越阻抗圖案層厚度的範圍内， 將包含下層、中間層和上層的3層以上形成的導電性金屬鍍上 (Plating)後’除去阻抗圖案層，施予蝕刻（etching)處理， 進行將'述中P3層的寬度比前述下層和上層縮小的加工作業，藉 此使其橫斷面形狀是中間層為凹狀的半導體元件裝載用金屬層 《底墊（pad) 門》與電極層《端子…論⑴部門》個別箱 立、並排作錢，金顧上裝鮮導體元件，料體元件上的電 極與電極層藉由打線接合㈣力地連接；半導體元件裝載部分以 樹脂封裝後，除去基板’得到_和電極層_面露出的樹 脂封裝體’這鮮導航件裝_基板㈣紗时為人所熟知 《例如’參照專利文獻2》。 【0 0 0 6】 因為基板上 點合性提南，可以防 依據專利文獻2所記_铸體元件裝伽基板的製造方 法’因為金屬層和電極層的中間層係作成比上下層較小的料 封裝樹脂與金制和電極層呈難優的私性；又，〜 最初作成的下層續金方式作成，與基板的’ 止封裝樹脂在基板和下層之間回珠。 電鍍，金屬層和電極 再者’因為沒有超過阻抗圖案層厚度做 201214645 層的橫向大小料，與龍__合力安定且綠，電極層的 上表面平坦，敝線接合性滅，可妓分職铸體裝置的小 型化或薄型化。 先前技術之文獻 專利文獻 【0007】 專利文獻1 特開2002-9196號公報 · *· 專利文獻2 特開2009-135417號公報 【發明内容】 【發明所要解問題】 【0008】 但是，專利文獻2所記載的結構組成，由於必須將多種類導 電性金屬作多層電鍍，使得該作業變的繁瑣複雜，—直留下降低 成本的課題。 【0009】 有鑑於前述之先前技術的問題’本發'明之目的係提供一種半 導體元件裝載用基板及其製造方法，係端子部門與封裝樹脂的結 201214645 合力或與打線的連接性均極優，可以降低製造成本，也可以充分 對應半導體裝置的小型化或薄型化的半導體元件裝載用基板及其 製造方法。 【解決問題所採取的方法】 【0010】 依據本發明之半導體元件裝載用基板，其特徵為：具有使用 相同種類的金屬或合金所構成的複數層狀的層狀部門力相鄰層金 屬的平均結晶粒子直徑不同；並且，在前述層狀部門的侧面，在 相鄰層金屬處形成有高低差的凹下部份；至少具有端子部門。又， 於本發明之半導體元件裝載用基板，前述層狀部門以3層以上構 成是較合於_的；又，於本發明之半導體元㈣_基板，前 .述層狀部門中，在前述相鄰層金屬的前述相同種類的金屬或合金 的平均結晶粒子直徑的差是0· 5微米（卵）以上，則較合於理想。 【0011】 再者饭據本發明之半導體元件裝載用基板的製造方法，包 含:、層狀部門形成作業、以及，高低差階梯形成作業。層狀部門 形成作業，相對於具有至少含有絲形成端子部門區域的特定露 出區域（exposure area)的阻抗圖案層所作成的導電性基板而言， 藉，把作鍍金屬處理，保持阻抗圖案層厚度以下的厚度而作成層 狀。P門係在則述導電性基板的露出區域，使用相同種類金屬或 201214645 合金的相鄰層金屬的平均 的層狀部π之層狀州_===相_減層狀所構成 前r&quot;低差_職健，相對於 曰門層狀州形成作業為介質所形成的導· 言，藉由施予_加工，湖精±基板而 來rn, 於_層㈣π側面，在相觸金屬處 以具有層狀部 形成有純差_下部份之高低差階梯形成作業 門形成健及高傾階_雜業為特徵。 狀部===半導體元件裝載用基板的製造方法，於前述層 爲.’、纟於變更電流密度、施作鍍金屬處理，使前 述層狀部門中相鄰層中的&amp; 騎巾^軸_·飄合金的平均結晶粒 子直徑產生變化，則較為理想。 【發明之成果】 【0012】 。依據本侧，_造成本可崎低，軸此製造方法是簡 的♦序4一疋端子。ρ門與封裝樹脂的結合性極優，在徙樹脂封 體將基板分離之際，不會留下已作成的錢金屬層；X，端子部! 與接合打_連祕極優，可崎雜高可紐的半導體元件』 载用基板及其製造方法。 【實施方式】 【0014】 以說明 藉由實施例的說明，將關於本發明的作用成果加 201214645 “依據本個之铸體元錄_基缺其製造綠，由於係 稭由將平職晶粒子直___金屬或合金施行電麟作成 的端子部門中的層狀部份，為了作成層狀部份，使用的鍵金屬液 只要1種即可，齡騎置也無醉備多種，也變的容易管理。 構成此層狀部分的平均結晶粒子直徑齡屬層，對於 _液的溶解性也不同’粒子直錄小者溶輸為快速。此因為 則係/。著、纟。aa粒邊界（Grain bQundary)進人結晶粒邊界較 多的較小平·日日日粒子餘層就會優先地（㈣⑽—…）溶 解。 像這樣所得刺端子部n，其側社⑽金屬魏形成有高 低差如階梯般的凹下部份。因此，罐本發明，如同專利文獻i 之製造方法，藉由超越阻抗圖案層的厚度施行電鑄法 (electrotyping) ’不會形成突出部份，可以提高與封裝樹脂的 、-、。&amp; n。又，因為沒有超越阻抗圖案層的厚度施行電鑄法，層狀 邻知的上表面可以平坦地作成，與接合打線的連接性也變的極優。 【0015】 圖Ka)、（b)係本發明的一個實施型態相關之半導體元件裝载 用基板中的端子部門的概略剖面圖。本發明的一個實施型態相關 之半導體元件裝載用基板，在基板丨上，最上層和最下層係由鍍 金層13所構成，在鍍金層13之間，係具有由平均結晶粒子直徑 較大的鍍鎳（nickel plating)層10和平均結晶粒子直徑較小的 201214645 鐘鎳層11層#喊的層狀部份12;藉由施行朗加工，層狀部份 12在層疊的側面’相鄰層的金屬中，平均例子直徑較小的一方的 鏟鎳層11 ’麵於平均解直雜大的賴層，其細形成凹 下狀態的階段差。 再者，圖1(a)係做為該實例相關料體元件裝载縣板，端 Μ的層狀。|5伤12係由4層平均例子直徑較大的鐘錄層 和3層平均例子直徑較小的鍍錄層η所構成，圖1⑷係顯示該狀 之圖不’⑹係做為其他實例麵轉體元件裝細基板，端子 ^ 3的層狀部份12係由2層平均例子直徑較大賴㈣和1 二、’：i子直讀小的鍍鎳層η所構成，⑷係顯示該狀態之圖 不0 【0016】 件在轉難置㈣造作針，朗本發敗半導體元 1载用基_製物㈣，峨。圖2係—個說明圖， 2本發明的-個實施型態相關之半導體树裝載絲板的製造 ,，以剖面顯示半導體裳置的製造作業。 本㈣之半物树裝_基織造之際，其前置作業 膜（Phi鑛鋼製成的導電性基板1的兩面上，貼上感光性乾性才 板1的QSenSltlVe Dry Fllms)作成的阻抗遮罩。然後，在; 側的表面的阻抗2上’覆蓋上玻璃遮罩(gl— a '、略未転》’其上作成具有鍍金屬用露出區域的遮罩圖 201214645 案，經過施行曝光、顯影處理，具有至少包含端子部門形成用之 區域的特定露出區域的阻抗圖案層2以尤作成了《圖2⑷》。又， 在圖2的實例中，露出區域除了端子部門形成用之區域％以外， 還有半導體元件裝載部門《底塾部門》形成用之區域. 【0017] 其次，對於已作成阻抗圖案層2a的基板卜施行經金屬前處 理作業後，在露出區域2ai、2¾上施行鍍金作業。 接著，在已施行鑛金作業的露出區域％、^上，使用相同 麵金屬或合金例如鎳等，進行鍍金騎理，作成層疊起來而相 鄰層金屬的平均結晶粒子直徑不同的疊層，舉例來說，如圖工⑷、 ⑹所示，作賴造為概綠的躲部份12，其厚度低於阻抗圖 案層2a厚度。 接著’在已作成的層狀部份12上，施行鍍金作業《圖抑）》。 【0018】 其次，將形成在基板1兩面上的阻抗遮罩2a、2b剝取除去， 浸泡在使鎳溶解的液體忠-定時間，藉此施行餘刻加工處理。經 過此私序，如圖2(c)所示，在基板！上製備端子部門3和半導體 元料咖《綱Π》4，彻權娜觸作完成 了。此時’如上所述’構成層狀部份12的平均結晶粒子直徑不同 的鍍金屬層Π)、U，因為對於_液的溶解度不同，結晶粒子直 201214645 徑較小的層溶解較快’在層狀部份12的側面上，在相鄰層1〇、u 的金屬上’形成有高低差階梯的凹下部分《圖2(d)》。 如此知作’即可得到本發明之半導體元件裝載用基板。 【0019】 在半導體技製造之際，在前職造方法所制之半導體元 件裝載用基板上的特定位置《圖2之實财半導體元件裝載部門 4&gt;處，賴半導體元件5，半導體元件5的電極和端子部門3以 接合打線連接後’在基板上以打線6連接的半導體元件5和端子 σΡ門3的這一側’用樹脂7封裝起來《圖2(e)》。 【0020】 =封⑽《 7槪崎，_峨〗從樹脂封裝 =:=業，得到端子部門3和轉體元件裝載部門4的 2⑴》。^側以樹月曰封裝、而其背面露出的半導體裝置《圖 【〇〇21】 I構n本發月之轉體錢縣板，如®12所示，並未限定 ^為製備端子節和輪元件裝栽部門4,也適用於如s 導雜置之料，財奸州3秘有料體元件芽 載。卩Η 4的構造也可以。 201214645 [0 0 2 2] 士如圖3所示之半導體裝置製造之際’對於前述圖示未顯示 導電性基板上只有作成軒部⑽本發明之半導體元件裝载^ 板而言，將半導體元件直接裝載於導電性基板的特定位置上了 半導體元件的餘和端子簡以接合打線連雛，基板上叫 連接的半導體元件和端子部n這—側，蘭脂封裝起來。丁、、、 然後’封裝的樹脂硬化以後，將導電性基板從樹脂封裝體取 下，經此作f，得到端子部門3和以打線6連接的半導體元件$ 這一側以樹脂封裝、而其背面露出的半導體裝置。 【實施例1】 [0 0 2 3] 實施例1係具備圖1(a)所示之構造的半導體元件裝載用基板 的實施例。 將板厚度為0. 2毫米（删）的不鏽鋼《SUS430》作為基板i， 進行除油脂（degreasing)、酸洗（pickling ; acid cleaning) 處理以後，藉由貼合輪（Laminating Roll)，將厚度為〇. 〇5〇毫 米的感光性乾膜光阻（photosensitive dry film resist)黏貼 在基板1的兩面上’在基板1的一侧表面的乾膜光阻上覆蓋作成 鍍金屬遮罩圖案的玻璃遮罩，然後從其上方利用紫外線照射使其 曝光，進行顯像處理，作成藉由乾膜光阻的特定圖案所形成的阻 13 201214645 抗遮罩2a ’而基板1的背面側的表面上，作成全面覆蓋的阻抗遮 罩2b《圖2(a)》。 【0 0 2 4] 其次’相對於從基板1的阻抗遮罩2a露出的區域2ai、2出， 施行鍍金屬則處理後’實施厚度為1微米（# m )之鍍金，接著， 於其上，使用氣基^酸錄（nickei an^n〇SLjf〇nate ; nickei sulfaminate)浴實施鍍鎳，在電流密度為15安培/平方分米（A /dm2)，形成平均結晶粒子直徑為〇 8微米的鍍鎳層1〇，其厚度 為5微米；接著，在電流密度為5安培/平方分米，形成平均結 晶粒子直徑為0. 3微米的鍍鎳層11，其厚度為5微米d更進一步， 在其上同樣地貫％，平均結晶粒子直徑為〇. 8微米的鍍鎳層1〇和 平均結晶粒子餘為G.3微米的鍍_ n交魏層疊起來，作成 層疊部門12 ’在其上實施3微米厚度的鍍金作業。經由此作業， 作成平均結晶粒子直徑為〇· 8微料錄鎳層1G有4層、平均結晶 粒子直徑為G. 3微米的賴層丨丨有3層、最上層和最下層為鑛金 層13 ’構成端子部門3《圖2(b)》。 [0025] 其次，剝除在基板1的兩面上所作成的阻抗遮罩^《圖 2(c)》，使用可溶解鎳的溶液《例如，眺公司製造之簡系 列》’在室溫下’藉由0.5分鐘、h5分鐘、2.5分鐘、3.5分鐘的 201214645 .時間作浸泡處理，端子部門3側面的鑛鎳層1〇、1〇處，形成約〇. 3 〜2.8微米的高低差《圖2(d)》，此高低差係利用平均結晶粒子直 徑較小的賴層U的_速度比平均結故子直徑較大的鑛錄層 10的細賴織猶成的；該浸㈣_高餘_果顯示在 圖4 〇 [0026] 為了判定黏合性，以上述作業為媒介所得到的半導體元件裝 載用基板上’使用黏晶粒（die丨福）用的黏貼_ (卿⑹， 將半導體元件5裝載上去，半導體树5的電極和端子部門3以 接合打線6連接後，麟脂7實行封裝《圖2(e)&gt;，封裝樹脂硬化 後，將作為基板1的不鏽鋼從封裝樹脂剝取下來《圖2(f)》。 [0027] 詳細觀察轉鋼侧取下來的H其結果，實施浸泡處 理0. 5分鐘，端子部門3側面的鍍錄層形成約〇. 3微米的高低差 階梯的半導體元件裝載用基板，在不鐵鋼這一侧形成的鑛金屬 層，隨處可見殘留部份，可以確認端子部門3與封裝樹脂7的黏 合性很低；但是’實施浸泡處理h 5分鐘以上，端子部門3側面 的鍍鎳層形成約1微米以上的高低差階梯的半導體元件裝載用基 板，在不鏽鋼這一側形成的鍍金屬層，沒有殘留部份，又，從封 裝樹脂7也沒有端子部門3浮起統落的财，可以確認該黏合 15 201214645 性係良好地保持。 【比較例1】 [0028] 比較例1係相對於實施例1之半導體元件裝載用基板的比較 例〇 與實施例相同，用不鏽鋼作為基板，作成阻抗遮罩，進行鍍 金屬前置處理；其次，實施厚度為1微米賴金作業，接著，於 ，、上使用氨基確酸錄（nickel aminosulfonate; nickel sulfaminate)浴進行鍍鎳，在電流密度為15安培/平方分米（a /dm2) ’形成平均結晶粒子直徑為Q· 8微米的鍍_，其厚度為$ 微求二接f ’在電流密度㈣安培/平方分米，形成平均結晶粒 子直徑為G. 5微米的麟層u，其厚度為5微米。更進一步，在 其上同樣地實施’平均結晶粒子直彳£為G 8微糊_層和平均 結晶粒子紐為〇· 5微米__交互地層疊起來，在其上實施3 微米厚度_金作業。經由此作業，作成平均結雜子直徑為〇. 8 «的鑛鎳層有4層、平均結晶粒子直徑為G. 5微米的鑛錄層有3 層、最上層和最下層紐金層，構成端子部門。 接著’與實施例1相同，剥下除去阻抗遮罩，使用可溶觸 的溶液，在室溫下進行L 5分鐘的浸泡作業，但是在端子部⑽ 鍍錄層側面，只能得到〇. 3微雜度的高低差階梯。因此，可以 判定：與實施例丨的結果比較，比較例丨生產性不佳，而且在〇丨 201214645 微米程度的高低差階梯，其黏合性也很低。 【實施例2】 【0029】 貫施例2係具備圖1(b)所示之構造的半導體猶裝载用基板 的貫施例。 與實施例相同，用不鏽鋼作為基板，作成阻抗遮罩，不進行 鍍金屬前置處理；實施厚度為1微米的鍍金作業，摻著，於其上， 使用氨基磺酸鎳浴進行鍍鎳，在電流密度為丨5安培/平方分米（A /dm2)’形成平均結晶粒子直㈣Q8微米的鍍蘇層，其厚度為 1〇微米；接著’於其上，在電流密度為5安培/平方分米，形成 平均結晶粒子直徑為〇.3微米的麟層，其厚度為15微米；更進 —步’在其上’在電流密度為15安培々方分米（A/dm2)，形成 平均結晶粒子直徑為0. 8微米的鍍錄層，其厚度為10微米；在其 上實施3微米厚度的鍍金作業。 +接著，與實施例1_，剝下除去阻抗遮罩，使用可溶解錄 ，溶液’在室溫下進行」· 5分鐘的浸泡作f ;裝辭導體元件； ，载半導體元件的f極和端子部⑽接合㈣連接；進行樹月旨封 裝；將不鏽峨翻旨職齡_τ ;贿在獨編的表面， 其結果是完全沒有鍍金屬層殘留部份。 【產業上的可能應用】 201214645 【0030】 本發明之半導體I載用基板及其製造方法，可以降低製、&amp;成 本，雖然該製造方法是—個簡單的作餘序，但㈣子部門與封 裝樹脂的黏合性極優’將基板從樹脂封裝體拉開取下之際，不會 殘留已作成_金屬層，作為可靠性（Reliability)碎的半導 體裝載絲板及其製造妓，能產生㈣優㈣結果，在相關產 業領域中的廣泛應用是可以期待的。 【圖式簡單說明】 【0013】 【圖1】圖i係顯示本發明的一個實施型態相關之料體元件裝載 用基板中的端子部門的概略結構組成之剖面圖，（a)係顯 示某-個實例相關之半導體元件裝載用基板的端子部門 的剖面圖，（b)係顯示其他的一個實例相關之半導體元件 裝載用基板的端子部門的剖面圖。 【圖2】圖2係-個說· ’包含本發明的—個實施㈣相關之半 導體元件裝載用基板的製造方法，以剖面顯示半導體裝置 的製造作業；（a)係顯示在導電性基板上，阻抗遮罩 (reslst mask)作成的狀態；⑹係顯示在⑷之已作成 阻抗遮罩的基板的露出區域上，包含層狀部門的鑛金屬層 作成的狀態；（e)_* :從作成鍍金屬層的基板除去阻 201214645 抗遮罩，施予触刻處理，作成本發明的—個實施型態相關 之半導體元件裝載用基板的狀態；（d)係放大圖，顯示製 備在(C)之半導體元件裝·基板上的層狀部門的側面， 作成高低差；（e)顯示在(c)之半導體元件裳載用基板上裝 載半導體元件，半導體元件的電極和端子部門以接合打線 連接後，用樹脂將這些封裝離態；⑴係顯示從⑹所示 之封裝樹脂體，將導電性基板剥離，完成後半導體裝置的 狀態。201214645 6. TECHNOLOGICAL FIELD OF THE INVENTION [0001] The present invention relates to a substrate for mounting a semiconductor element of a terminal portion formed by a metal plating operation, and a method of manufacturing the same . [Prior Art] In the past, a specific resistance pattern layer was formed on one surface of a conductive substrate, and a surface of the conductive substrate (pXp〇se) was exposed from the impedance pattern layer. Exceeding the thickness of the impedance pattern layer, the conductive metal is electrodeposited; the upper end portion has a protruding portion of the semiconductor element loading metal layer (metal 1 aer er) and the electrode layer (e 1 ^ After being individually and in parallel, the impedance pattern layer is removed, the semiconductor element is mounted on the metal layer, and the electrode and the electrode layer on the semiconductor element are electrically connected by bonding wires; the semiconductor component loading portion is After the resin is packaged, a method of manufacturing a semiconductor device in which the substrate is removed and the resin package is exposed to the back surface of the metal layer and the electrode layer is known. For example, refer to Patent Document 1. [0003] According to the method for manufacturing a semiconductor device described in Patent Document 1, since the protruding portion is located where the encapsulating resin is difficult to enter, the metal layer and the electrode layer and the encapsulating resin are improved by an anchor effect. The bonding force, in the post-operation, when the substrate is pulled away, the necessary parts of the metal layer and the electrode layer are not left on the substrate, and the shape of the resin package is buried, and the metal layer can be prevented. And the result of the slippage or lack of the electrode layer. Moreover, the intrinsic protruding shape formed by the entire periphery of the edge of the upper end portion of the metal layer and the electrode layer can prevent the intrusion of the interface between the metal layer and the electrode layer and the encapsulating resin from the inner surface of the semiconductor device. Moisture, to achieve excellent moisture resistance (res i stance of moi sture). [0 00 4] However, in the manufacturing method of the patent document 1, the electric deposition is performed across the impedance pattern layer, and as a result, the electrodeposition exceeding the thickness portion of the impedance pattern layer becomes completely impedance-free. In the state of the pattern layer restriction, it is easy to find the influence of the current current density distribution, etc., it is difficult to maintain the fixed length of the protruding portion, and the adhesion between the metal layer and the electrode layer and the encapsulating resin does not occur. The average problem. In addition, because the surface of the surface layer and the electrode layer are also made of electricity and electricity, the upper surface is not flat but is formed into a hemispherical shape, and it is easy to cause a poor connection of the bonding wire. [0004] In addition to the method for manufacturing a semiconductor device described in Patent Document 1, the method for manufacturing a semiconductor device board is known as "the surface of the conductive substrate". In the case of the resist pattern layer, a conductive metal formed of three or more layers including the lower layer, the intermediate layer, and the upper layer is formed on the surface of the substrate exposed from the impedance pattern layer without exceeding the thickness of the impedance pattern layer. After plating, the impedance pattern layer is removed, and an etching process is performed to perform a processing operation of reducing the width of the P3 layer from the lower layer and the upper layer, thereby making the cross-sectional shape an intermediate layer. For the concave semiconductor element loading metal layer "pad" and the electrode layer "terminal ... (1) department" individually boxed, side by side for money, Jin Gu loaded with fresh conductor components, electrodes on the material body The electrode layer is connected to the electrode layer by wire bonding (four); after the semiconductor component loading portion is encapsulated with a resin, the substrate is removed and the resin package exposed to the surface of the electrode layer is removed. When the well known "e.g." refer to Patent Document 2. " [0 0 0 6] Because the dot-bonding on the substrate is raised, it can be prevented according to the method of manufacturing the galvanic substrate of the cast component according to Patent Document 2 because the intermediate layer of the metal layer and the electrode layer is smaller than the upper and lower layers. The material encapsulating resin is inferior to the gold and the electrode layer; in addition, the first layer is formed by the original layer, and the encapsulating resin of the substrate is returned between the substrate and the lower layer. Electroplating, metal layer and electrode are further 'Because there is no thickness of the layer of the impedance pattern to make the horizontal size of the layer of 201214645, and the dragon __ is stable and green, the upper surface of the electrode layer is flat, and the joint of the electrode line is extinguished. The casting device is miniaturized or thinned. [Patent Document 1] Japanese Laid-Open Patent Publication No. JP-A-2002-196417 (Patent Document 1) [Invention] [0008] However, Patent Document 2 In the structural composition described, since it is necessary to perform multi-layer electroplating of a plurality of types of conductive metals, the work becomes complicated and complicated, and the problem of cost reduction is left. [0009] In view of the foregoing problems of the prior art, the object of the present invention is to provide a substrate for mounting a semiconductor element and a method of manufacturing the same, which is excellent in the joint force of the terminal portion and the package resin 201214645 or the connection with the wire bonding. The semiconductor element mounting substrate and the method of manufacturing the same can be sufficiently reduced in size and thickness of the semiconductor device. [Means for Solving the Problem] The substrate for mounting a semiconductor element according to the present invention is characterized in that it has an average of a plurality of layered layer-force adjacent layer metals which are formed of the same kind of metal or alloy. The crystal particles have different diameters; and, on the side of the layered portion, a depressed portion having a step is formed at the adjacent layer metal; at least a terminal portion is provided. Further, in the substrate for mounting a semiconductor element of the present invention, the layered portion is made of three or more layers, and the semiconductor element (four)_substrate of the present invention, in the above-mentioned layered portion, is as described above. It is preferable that the difference in the average crystal particle diameter of the same kind of metal or alloy of the adjacent layer metal is 0.5 μm or more. Further, the method for producing a substrate for mounting a semiconductor element according to the present invention includes a layer forming operation and a step forming operation. The layered portion forming operation, with respect to the conductive substrate having the impedance pattern layer having at least a specific exposure area of the wire forming terminal portion region, is subjected to metallization treatment to maintain the thickness of the resist pattern layer It is layered in the following thickness. The P gate is formed in the exposed region of the conductive substrate, and the layered state of the layered portion π of the same type of metal or the adjacent layer metal of the 201214645 alloy is used. The former r&quot; Low difference _ occupational health, relative to the formation of the layered state of the Tuen Mun, the formation of the medium, by the application of _ processing, Hu Jing ± substrate to rn, on the _ layer (four) π side, at the contact metal The step having the layered portion formed with the pure difference _ lower portion is formed by the formation of the work gate and the high step. <======================================================================================================= It is preferable that the average crystal particle diameter of the floating alloy is changed. [Results of the Invention] [0012]. According to this side, _ causes the original low, and the manufacturing method of the shaft is simple. The combination of ρ gate and encapsulating resin is excellent. When the substrate is separated by the resin sealing body, the deposited metal layer will not be left behind; X, the terminal part is excellent with the bonding. "Microconductor semiconductor device" carrier substrate and method of manufacturing the same. [Embodiment] [0014] In order to explain the effect of the present invention by the description of the embodiment, 201214645 "according to this casting material _ base lack of its manufacturing green, due to the straw will be used Straight ___metal or alloy is applied to the layered part of the terminal section made of electric lining. In order to make a layered part, only one type of key metal liquid can be used, and the age riding is not drunk, and it also becomes It is easy to manage. The average crystal particle diameter constituting this layered part is different from that of the _ liquid. The particle direct recording is small and dissolves quickly. This is because the aa, 纟, a. grain boundary (Grain bQundary) The smaller flat and daily solar particles with more crystal grain boundaries will be preferentially dissolved ((4)(10)-...). The tangent terminal portion n thus obtained has a height difference between the side (10) and the metal. The concave portion is formed like a step. Therefore, the present invention, as in the manufacturing method of Patent Document i, can be improved by encapsulating electroforming by the thickness of the layer beyond the impedance pattern layer. Resin, -,. Further, since the electroforming method is not performed beyond the thickness of the impedance pattern layer, the upper surface of the layered neighboring layer can be formed flat, and the connection with the bonding wire is also excellent. [0015] Fig. Ka), (b) is a schematic cross-sectional view of a terminal portion in a substrate for mounting a semiconductor element according to an embodiment of the present invention. The substrate for mounting a semiconductor device according to an embodiment of the present invention is on the uppermost layer of the substrate. The lowermost layer is composed of a gold plating layer 13 having a nickel plating layer 10 having a large average crystal particle diameter and a 201214645 nickel layer 11 layer having a small average crystal particle diameter between the gold plating layers 13. #叫的状状部分12; By performing Lang processing, the layered portion 12 is on the side of the laminated side of the adjacent layer of the metal, the average example of the smaller diameter of the shovel nickel layer 11' surface is averaged straight In the case of a large layer, the stage of the finely formed concave state is poor. Furthermore, Fig. 1(a) is used as the relevant material element of this example to load the county plate, and the end layer is layered. 4-layer average case with a larger diameter of the clock recording layer and a 3-layer average case The plated layer η having a smaller diameter is formed. Fig. 1(4) shows that the figure is not '(6) is used as a thin substrate for other example surface-turning elements, and the layered portion 12 of the terminal ^3 is a two-layer average example. Larger diameters (4) and 1 2, ':i sub-direct reading of a small nickel-plated layer η, (4) shows that the state of the figure is not 0 [0016] pieces in the turn hard (four) made a needle, Longben defeated the semiconductor The element 1 is loaded with a substrate (four), and is shown in Fig. 2. Fig. 2 is an explanatory view showing the manufacture of a semiconductor tree-loaded wire plate according to an embodiment of the present invention, and shows the manufacturing operation of the semiconductor skirt in a cross section. In the case of the semi-material tree _ base weaving, the front working film (QSenSltlVe Dry Fllms of the photosensitive dry board 1 on both sides of the conductive substrate 1 made of Phi ore) is formed by impedance shielding. cover. Then, on the impedance 2 of the surface on the side, 'covering the glass mask (gl-a ', slightly untwisted'' on the mask pattern 201214645 with the exposed area for metal plating, after exposure and development treatment The impedance pattern layer 2 having a specific exposed region including at least the region for forming the terminal portion is particularly formed as "Fig. 2 (4)". Further, in the example of Fig. 2, the exposed region is in addition to the % of the region for forming the terminal portion. There is a region for forming a semiconductor element loading unit "bottom unit". [0017] Next, after the metal pre-processing operation is performed on the substrate on which the impedance pattern layer 2a has been formed, gold plating is performed on the exposed regions 2ai, 23⁄4. In the exposed areas % and ^ of the operation of the gold mining operation, the same surface metal or alloy such as nickel is used for gold plating, and the lamination is performed, and the average crystal particle diameter of the adjacent layer metals is different, for example, It is said that, as shown in the drawings (4) and (6), the hiding portion 12 which is made into a green color is thicker than the thickness of the impedance pattern layer 2a. Then 'on the layered portion 12 which has been formed Plated purposes job "FIG suppression)." Next, the impedance masks 2a and 2b formed on both surfaces of the substrate 1 are stripped and removed, and immersed in a liquid which dissolves nickel for a predetermined time, thereby performing a finishing process. After this private sequence, as shown in Figure 2(c), on the substrate! On the preparation of the terminal department 3 and the semiconductor elementary material "Gang Yu" 4, Chu Quan Na touched the work. At this time, 'the metallized layer Π) and U which constitute the layered portion 12 having different average crystal particle diameters as described above, because the solubility of the liquid particles is different, the layer having a smaller diameter of the crystal particles of 201214645 dissolves faster. On the side of the layered portion 12, a recessed portion of the step of height difference is formed on the metal of the adjacent layers 1〇, u (Fig. 2(d)). Thus, the substrate for mounting a semiconductor element of the present invention can be obtained. [0019] In the semiconductor device manufacturing, the specific position on the semiconductor component mounting substrate manufactured by the predecessor manufacturing method, "the solid semiconductor component mounting section 4 of FIG. 2", the semiconductor component 5, and the semiconductor component 5 The electrode and the terminal portion 3 are joined by a bonding wire, and the side of the semiconductor element 5 and the terminal σ gate 3 connected by the wire 6 on the substrate is packaged with the resin 7 (Fig. 2(e). [0020] = Seal (10) "7槪崎, _峨" from the resin package =:= industry, get the terminal department 3 and the rotating component loading department 4 2 (1). ^The side of the semiconductor device is packaged on the back side of the tree, and the semiconductor device exposed on the back side of the picture is shown in Fig. 21, as shown in the ®12, which is not limited to the preparation of the terminal section and The wheel component loading department 4 is also suitable for materials such as s. The structure of 卩Η 4 is also available. 201214645 [0 0 2 2] When the semiconductor device shown in FIG. 3 is manufactured, 'the above-mentioned illustration does not show that only the conductive substrate is made of the semiconductor device mounting plate of the present invention. The semiconductor device is directly mounted on a specific position of the conductive substrate, and the terminal and the terminal are connected by a bonding wire. The substrate is connected to the semiconductor element and the terminal portion n, and the resin is encapsulated. After the resin is hardened, the conductive substrate is removed from the resin package, and f is obtained to obtain the terminal unit 3 and the semiconductor element connected by the wire 6. This side is encapsulated with a resin, and A semiconductor device exposed on the back side. [Embodiment 1] [0 0 2 3] Embodiment 1 is an embodiment of a substrate for mounting a semiconductor element having the structure shown in Fig. 1(a). The stainless steel "SUS430" having a thickness of 0.2 mm (deleted) is used as the substrate i, and after degreasing and pickling treatment, the thickness is adjusted by a Laminating Roll. 〇 5 〇 5 〇 photosensitive dry film resist adhered to both sides of the substrate 1 'on the dry film photoresist on one side of the substrate 1 over the glass to form a metallized mask pattern The mask is then exposed to ultraviolet light from above, and subjected to development processing to form a resist 13 formed by a specific pattern of dry film photoresist. 201214645 Anti-mask 2a' is formed on the surface on the back side of the substrate 1 Make a comprehensive coverage of the impedance mask 2b "Fig. 2 (a)". [0 0 2 4] Next, with respect to the regions 2ai and 2 exposed from the impedance mask 2a of the substrate 1, metallization is performed, and then gold plating having a thickness of 1 μm (#m) is performed, and then thereon. Nickel plating was carried out using a bath of nickei an^n〇SLjf〇nate; nickei sulfaminate at a current density of 15 amps/dm2 (A/dm2) to form an average crystal particle diameter of 〇8 μm. a nickel-plated layer having a thickness of 5 μm; and then, at a current density of 5 amps/dm 2 , a nickel-plated layer 11 having an average crystal particle diameter of 0.3 μm, having a thickness of 5 μm d further In the same manner, the average crystal particle diameter is 〇. 8 μm of the nickel-plated layer 1 〇 and the average crystal grain is G. 3 μm. A gold plating operation of 3 micrometers thickness is performed on the upper surface. Through this operation, the average crystal particle diameter is 〇·8 micro-recorded nickel layer 1G has 4 layers, and the average crystal particle diameter is G. 3 micron. The layer has 3 layers, and the uppermost layer and the lowermost layer are gold layers. 13 'Composed terminal department 3 "Fig. 2 (b)". [0025] Next, stripping the impedance mask formed on both sides of the substrate 1 "Fig. 2 (c)", using a solution that dissolves nickel "for example, a simple series manufactured by the company" at room temperature The immersion treatment was carried out for 0.514 minutes, h5 minutes, 2.5 minutes, and 3.5 minutes of 201214645. The ore layer of the side of the terminal section 3 was formed at 1 〇 and 1 ,, forming a height difference of about 3 to 2.8 μm. (d)", the height difference is determined by the finer layer of the layer U having a smaller average crystal particle diameter than the average layer of the mineral layer 10 having a larger diameter of the average knot; the dip (four)_ _ fruit is shown in Fig. 4 0026 [0026] In order to determine the adhesion, the adhesive for the semiconductor element mounting substrate obtained by using the above-mentioned operation is used. 5 Loading, the electrode of the semiconductor tree 5 and the terminal unit 3 are connected by the bonding wire 6 , and the resin 7 is packaged as shown in Fig. 2(e). After the sealing resin is cured, the stainless steel as the substrate 1 is stripped from the sealing resin. Go down to Figure 2(f). [0027] Observe the results of H taken from the steel side in detail and implement 5 minutes, the plating layer on the side of the terminal section 3 forms a substrate for mounting a semiconductor element of about 3 micrometers, and the residual metal is formed on the side of the metal layer formed on the side of the non-ferrous steel. It is confirmed that the adhesion between the terminal portion 3 and the sealing resin 7 is low. However, the immersion treatment h is performed for 5 minutes or more, and the nickel plating layer on the side surface of the terminal portion 3 forms a semiconductor element mounting substrate having a step of about 1 μm or higher. In the metal plating layer formed on the side of the stainless steel, there is no residual portion, and the sealing resin 7 is not floated from the terminal portion 3, and it can be confirmed that the bonding 15 201214645 system is well maintained. [Comparative Example 1 [Comparative Example 1] A comparative example of the semiconductor element mounting substrate of Example 1 is the same as the embodiment, and a stainless steel is used as the substrate to form an impedance mask, and a metal plating pre-treatment is performed. Second, the thickness is performed. 1 micron lysine operation, followed by nickel plating on a nickel aminosulfonate (nickel sulfaminate) bath at a current density of 15 amps/ Square decimeter (a /dm2) 'Formed with an average crystal particle diameter of Q · 8 μm plated _, the thickness of which is $ micro-finished f ' at current density (four) amps / square decimeter, forming an average crystal particle diameter of G 5 micron layer u, which has a thickness of 5 micrometers. Further, on the same, the 'average crystal particles are directly 为G G micro-paste layer and the average crystal particle 纽·5 micron__ interaction The layers are stacked and a 3 micron thickness _ gold operation is performed thereon. Through this operation, the average number of the agglomerated nickel layers is 〇. 8 «The mineral nickel layer has 4 layers, and the average crystal particle diameter is G. 5 μm. The layer has 3 layers, the uppermost layer and the lowermost layer of gold, forming the terminal department. Then, in the same manner as in Example 1, the impedance mask was peeled off, and the solution which was soluble was used, and the soaking operation was performed for 5 minutes at room temperature. However, only the side of the plating layer of the terminal portion (10) was obtained. The step of the level of micro-difference. Therefore, it can be judged that, compared with the results of the example, the comparative example is inferior in productivity, and the adhesion is also low in the steps of the height difference of 201214645 micrometers. [Embodiment 2] [0029] The second embodiment is a configuration example of a semiconductor substrate for mounting having the structure shown in Fig. 1(b). As in the embodiment, stainless steel is used as the substrate to form an impedance mask, and no metallization pretreatment is performed; a gold plating operation having a thickness of 1 μm is applied, and a nickel sulfamate bath is used for nickel plating thereon. The current density is 丨5 amps/dm 2 (A /dm2)' to form an average crystalline particle straight (four) Q8 micron sulphide layer having a thickness of 1 〇 micron; then 'on it, at a current density of 5 amps per square centimeter Rice, forming a lining layer with an average crystal particle diameter of 〇.3 μm, having a thickness of 15 μm; further stepping 'on it' at a current density of 15 amps per square meter (A/dm 2 ) to form an average crystal The plating layer having a particle diameter of 0.8 μm has a thickness of 10 μm; a gold plating operation of 3 μm thickness is performed thereon. + Next, with Example 1_, stripping off the impedance mask, using the dissolveable recording, the solution 'at room temperature' · 5 minutes of immersion for f; reprinting the conductor element; , the f-pole and terminal of the semiconductor element Part (10) joint (four) connection; carry out the tree month package; put the stainless steel age _τ; bribe on the surface of the original, the result is that there is no residual part of the metallization layer. [Industrial Applicable Applications] 201214645 [0030] The semiconductor I carrier substrate and the method of manufacturing the same according to the present invention can reduce the cost of manufacturing and &amp; cost, although the manufacturing method is a simple pre-order, but (4) sub-sectors Excellent adhesion of the encapsulating resin. When the substrate is removed from the resin package, the semiconductor-loaded wire board and its manufacturing defects, which have been fabricated as a metal layer, do not remain, and can be produced (4) The results of excellent (4) can be expected in a wide range of applications in related industries. [Fig. 1] Fig. 1 is a cross-sectional view showing a schematic configuration of a terminal portion in a substrate for loading a material element according to an embodiment of the present invention, and (a) shows a certain A cross-sectional view of a terminal portion of a semiconductor component mounting substrate according to an example, and (b) is a cross-sectional view showing a terminal portion of a semiconductor component mounting substrate according to another example. FIG. 2 is a view showing a method of manufacturing a substrate for mounting a semiconductor element according to an embodiment (four) of the present invention, showing a manufacturing operation of the semiconductor device in a cross section; (a) showing on a conductive substrate. (6) is a state in which the resistive mask is formed in the exposed region of the substrate (4), and the state in which the layer of the ore metal layer of the layered portion is formed; (e)_*: from creation The substrate of the metallized layer is removed from the mask 201214645, and the contact treatment is performed, and the state of the substrate for mounting the semiconductor element related to the embodiment of the invention is obtained; (d) is an enlarged view showing the preparation in (C) The side surface of the layered portion on the semiconductor device package substrate is formed with a height difference; (e) the semiconductor device is mounted on the substrate for mounting the semiconductor device of (c), and the electrode of the semiconductor device and the terminal portion are connected by bonding wires. These packages are separated from each other by a resin; (1) The packaged resin body shown in (6) is shown, and the conductive substrate is peeled off to complete the state of the semiconductor device.

I 【圖3】圖3係本發明之變形實例’使用只有端子部門、沒有半導 _載部門的半導體元件裝_基板所製造者，係顯示該 半導體裝置的概略結構組成之剖面圖。 【圖4】圖4係圖表’顯示：在本發明之實施例i相關之半導體元 件錢用基板製造時，對於使用相同種類金屬或合金，作 成相鄰層金屬的平均結晶粒子直鮮同、由複數層狀所構 成之層狀部門的導電性基板而言，施予侧加工時的姓刻 液浸泡時間與相鄰層金屬高低差的關係。 ^ 【主要元件符號說明】 【0031】 ......基板 201214645 2·_••…阻抗遮罩 2a……作成阻抗圖案層的阻抗遮罩 2ai……端子部門形成用之露出區域 2a2……半導體元件搭載部門形成用之露出區域 2b……覆蓋基板全表面的阻抗遮罩 3……端子部門 4……半導體元件搭載部門 5……半導體元件 6 ......打線 7 ......樹脂 10……平均結晶粒子直徑較大層 11……平均結晶粒子直徑較小層 12……層狀部門 13……鍍金層 20[Fig. 3] Fig. 3 is a cross-sectional view showing a schematic configuration of the semiconductor device using a semiconductor device mounting substrate having only a terminal portion and no semiconductor package. [ Fig. 4] Fig. 4 is a diagram showing that when the semiconductor element substrate for use in the embodiment i of the present invention is manufactured, the average crystal grain of the adjacent layer metal is made to be the same as the same type of metal or alloy. In the conductive substrate of the layered portion formed in a layered state, the relationship between the immersion time of the surname and the height of the adjacent layer metal at the time of the processing of the donor side is different. ^ [Description of main component symbols] [0031] ... substrate 201214645 2·_••... Impedance mask 2a... Impedance mask 2ai for impedance pattern layer... Exposure area 2a2 for terminal sector formation... ...the exposed area 2b for forming the semiconductor element mounting unit...the impedance mask 3 covering the entire surface of the substrate...the terminal unit 4...the semiconductor element mounting unit 5...the semiconductor element 6...the line 7 ... Resin 10...average crystal particle diameter larger layer 11...average crystal particle diameter smaller layer 12...layered department 13...gold plating layer 20

Claims (1)

201214645 七 、申請專利範圍： :種半導狀聽_基板，係：料使__類金屬或合 、，a ― _子餘不_複數層狀所構成的 ;开：在前述層狀部門的側面，於前述相鄰層金屬 ^两低差階梯的凹下部份；至少具有端子部Η為其特徵 者0 專利範圍第1項所述之半導體元件裝載用基板，其中前 述層狀部⑽由3層社的層狀部分所縣為其特徵者。 專利範圍第1項所述之半導體元件裝載用基板，.其中前 部門的前述相鄰層金屬的前述同種類金屬或合金的平 句’粒子餘，其差異是0 5微米以上為其舰者。 =導體元件裝_基板㈣造方法，係包含：相對於具有 ^ S有用來形成端子部門區域的特定㈣區域（卿0_ 的阻抗圖案層所作成的導電性基板而言，藉由施作鍍金 :理’保持阻抗圖案層厚度以下的厚度而作成層狀部門，係 来j述導電性基板的露出區域，使用相同種類金屬或合金的相 :金屬解均結晶粒子直徑補_複數層狀所構成的層 、,]之層狀4門形成作冑；相對於前述屬狀部門以層狀部門 形成作業為齡所形成輯賴基如言，藉由施予钱刻加 201214645 工j於前述層狀部η側面，在相鄰層金屬處形成有高低差的凹 下部份之高低紐梯形成作業。叫有層㈣m彡成作業及高 低差階梯形成作業為其特徵者。 錄金屬處理， 22201214645 VII. Patent application scope: : Semi-conducting listening _ substrate, system: material __ class metal or combination, a ― _ sub-remaining _ complex layered; open: in the aforementioned layered department a side surface of the semiconductor element mounting substrate according to the first aspect of the invention, wherein the layered portion (10) is The layered part of the 3rd floor is characterized by the county. The substrate for mounting a semiconductor element according to the first aspect of the invention, wherein the difference between the particles of the same type of metal or alloy of the adjacent layer metal of the front part is 0 5 μm or more. = Conductor component mounting - The method of fabricating the substrate (4) includes: performing a gold plating with respect to a conductive substrate having a specific (four) region for forming a terminal sector region (the impedance pattern layer of the 0_: The layer having the thickness below the thickness of the impedance pattern layer is formed as a layered portion, and the exposed region of the conductive substrate is used, and the phase of the same type of metal or alloy is used: the metal solution is a uniform crystal particle diameter and a plurality of layers are formed. The layered 4 gates of the layer, ,] are formed as 胄; compared with the formation of the layered department in the above-mentioned genus department, the formation of the ancestor is based on the words, and the money is added to the layered part by adding 201214645 The η side surface is formed by forming a high and low step of the concave portion of the height difference in the adjacent layer metal. It is characterized by the layer (4) m 彡 forming operation and the step forming operation of the height difference step. Recording metal processing, 22
TW100120040A 2010-06-14 2011-06-08 Semiconductor substrate mounting substrate and manufacturing method thereof TWI469291B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010135411A JP5333353B2 (en) 2010-06-14 2010-06-14 Semiconductor device mounting substrate and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TW201214645A true TW201214645A (en) 2012-04-01
TWI469291B TWI469291B (en) 2015-01-11

Family

ID=45348132

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100120040A TWI469291B (en) 2010-06-14 2011-06-08 Semiconductor substrate mounting substrate and manufacturing method thereof

Country Status (5)

Country Link
JP (1) JP5333353B2 (en)
KR (1) KR101402450B1 (en)
CN (1) CN102971845B (en)
TW (1) TWI469291B (en)
WO (1) WO2011158731A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI664706B (en) * 2017-04-21 2019-07-01 新加坡商先進科技新加坡有限公司 Routable electroforming substrate comprising removable carrier
TWI699867B (en) * 2017-03-29 2020-07-21 日商東芝股份有限公司 Semiconductor device and mthod for manufacturing same
TWI787343B (en) * 2017-09-20 2022-12-21 日商大口電材股份有限公司 Substrate for mounting semiconductor element and manufacturing method thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6362337B2 (en) * 2014-01-21 2018-07-25 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
WO2017133758A1 (en) * 2016-02-02 2017-08-10 Osram Opto Semiconductors Gmbh Lead frame and method for producing a lead frame
TWI660225B (en) * 2017-04-21 2019-05-21 新加坡商先進科技新加坡有限公司 Display panel fabricated on a routable substrate
JP6863846B2 (en) * 2017-07-19 2021-04-21 大口マテリアル株式会社 Substrate for mounting semiconductor elements and its manufacturing method

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06196324A (en) * 1992-12-25 1994-07-15 Matsushita Electric Ind Co Ltd Multilayer structure thin film and manufacture thereof
JP3626075B2 (en) * 2000-06-20 2005-03-02 九州日立マクセル株式会社 Manufacturing method of semiconductor device
JP3833892B2 (en) * 2000-12-20 2006-10-18 本田技研工業株式会社 Ni-Cu alloy plating film
US6774470B2 (en) * 2001-12-28 2004-08-10 Dai Nippon Printing Co., Ltd. Non-contact data carrier and method of fabricating the same
JP2004253574A (en) * 2003-02-19 2004-09-09 Fuji Electric Holdings Co Ltd Semiconductor device
JP4245370B2 (en) * 2003-02-21 2009-03-25 大日本印刷株式会社 Manufacturing method of semiconductor device
JP2005072290A (en) * 2003-08-26 2005-03-17 Mitsui Mining & Smelting Co Ltd Copper foil for printed wiring board, method for manufacturing the same, and copper clad laminate using the same
KR100884662B1 (en) * 2004-07-15 2009-02-18 다이니폰 인사츠 가부시키가이샤 Semiconductor device and semiconductor device producing substrate and production methods therefor
JP5001542B2 (en) * 2005-03-17 2012-08-15 日立電線株式会社 Electronic device substrate, method for manufacturing the same, and method for manufacturing the electronic device
JP2008306128A (en) * 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd Semiconductor device and its production process
US20090114345A1 (en) * 2007-11-07 2009-05-07 Sumitomo Metal Mining Co., Ltd. Method for manufacturing a substrate for mounting a semiconductor element
JP2009135417A (en) * 2007-11-07 2009-06-18 Sumitomo Metal Mining Co Ltd Method for manufacturing substrate for mounting semiconductor element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI699867B (en) * 2017-03-29 2020-07-21 日商東芝股份有限公司 Semiconductor device and mthod for manufacturing same
TWI664706B (en) * 2017-04-21 2019-07-01 新加坡商先進科技新加坡有限公司 Routable electroforming substrate comprising removable carrier
US10475666B2 (en) 2017-04-21 2019-11-12 Asm Technology Singapore Pte Ltd Routable electroforming substrate comprising removable carrier
TWI787343B (en) * 2017-09-20 2022-12-21 日商大口電材股份有限公司 Substrate for mounting semiconductor element and manufacturing method thereof

Also Published As

Publication number Publication date
CN102971845A (en) 2013-03-13
KR20130036017A (en) 2013-04-09
WO2011158731A1 (en) 2011-12-22
TWI469291B (en) 2015-01-11
KR101402450B1 (en) 2014-06-03
CN102971845B (en) 2015-07-01
JP2012004186A (en) 2012-01-05
JP5333353B2 (en) 2013-11-06

Similar Documents

Publication Publication Date Title
TW201214645A (en) Substrate for mounting semiconductor element and method for manufacturing the substrate
TW508705B (en) Wiring substrate and fabricating method thereof
CN103824836B (en) Quasiconductor load-carrying unit and semiconductor package part
CN107039144A (en) Inductor components
TW200901234A (en) Sulfuration resistant chip resistor and method for making same
TW201218323A (en) Method for manufacturing package substrate for semiconductor element mounting
CN103477725A (en) A non-deleterious technique for creating continuous conductive circuits upon the surfaces of a non-conductive substrate
TW200931548A (en) Method for manufacturing a substrate for mounting a semiconductor element
JP5948881B2 (en) Lead frame for semiconductor devices
CN102573335B (en) The method of initial layer core veneer
CN103517571A (en) Metal electroplating deposition method
JP6492930B2 (en) Lead frame for semiconductor device and manufacturing method thereof
JP5781877B2 (en) Wiring board manufacturing method
US11516907B2 (en) Glass wiring board
CN105070698B (en) Wafer scale scolding tin micro convex point and preparation method thereof
CN110854066A (en) Semiconductor electroplating method
CN106252315B (en) Encapsulating structure and its manufacturing method
JPH02253628A (en) Manufacture of semiconductor device
TW201131720A (en) Semiconductor package with single sided substrate design and manufacturing methods thereof
JPH10270630A (en) Substrate for semiconductor device and manufacture thereof
CN102856221A (en) Manufacturing process for IC (integrated circuit) packaging bump
JPH03159152A (en) Manufacture of bump electrode
TWI739008B (en) Wiring board and method for manufacturing wiring board
JP6493312B2 (en) Resin-sealed semiconductor device and manufacturing method thereof
JP2006294862A (en) Wiring circuit board and manufacturing method thereof

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees