CN102856221A - Manufacturing process for IC (integrated circuit) packaging bump - Google Patents
Manufacturing process for IC (integrated circuit) packaging bump Download PDFInfo
- Publication number
- CN102856221A CN102856221A CN201210293532XA CN201210293532A CN102856221A CN 102856221 A CN102856221 A CN 102856221A CN 201210293532X A CN201210293532X A CN 201210293532XA CN 201210293532 A CN201210293532 A CN 201210293532A CN 102856221 A CN102856221 A CN 102856221A
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- layer
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- projection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
The invention discloses a manufacturing process for an IC (integrated circuit) packaging bump. The manufacturing process comprises the following steps of providing a silicon chip, forming at least one aluminum cushion and one silicon chip protective layer on the silicon chip, forming at least one double-layered bump on the silicon chip, wherein the double-layered bump covers the aluminum cushion and the silicon chip protective layer; forming at least one protective layer on the silicon chip, forming at least one conductive layer on the protective layer; forming at least one photoresist layer with uniform thickness on the surface of the silicon surface, wherein the photoresist layer totally covers the protective layer and the conductive layer; performing exposing and developing on the silicon chip where the double-layered bump is required to be formed; depositing the double-layered bump on the surface of the silicon chip; removing the photoresist layer on the surface of the silicon chip; and removing the excessive metal area by chemical etching. By adopting the manufacturing process provided by the invention, the manufacturing process flow for the IC packaging bump is simple, the double-layered bump with gold and palladium can be manufactured to act on combined wafers and panels, thus, the material cost can be reduced; the service life of the product is longer; the reliability is better, and the market competitiveness is strengthened.
Description
Technical field
The present invention relates to the drive IC encapsulation field, particularly relate to a kind of manufacturing process of IC encapsulating lug.
Background technology
Industry is to use the proof gold projection in the drive IC encapsulation at present, replaces gold for the saving cost also has the dealer to release the combinations such as copper, nickel gold.In the IC encapsulation process, raising along with packaging density, conventional package form originally has been difficult to satisfy the bonding technology requirement, for reaching the technology controlling and process requirement, we develop some corresponding encapsulation technologies, improved the reliability of product, wherein gold/palladium projection because of its price and metal itself with respect to the stability of other metals, make it have more advantage.
Electro-plating method is generally adopted in the manufacturing of gold/palladium projection, will form behind the metal deposition.But traditional manufacture process is difficult to guarantee the reliability of projection, and its life-span is not good yet, can not satisfy client's demand.
Summary of the invention
The technical problem that the present invention mainly solves provides a kind of manufacturing process of IC encapsulating lug, can produce the double-deck projection that gold adds palladium, acts in conjunction with wafer and panel, can reduce material cost, life of product is longer, and reliability has strengthened market competitiveness more.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: a kind of manufacturing process of IC encapsulating lug is provided, comprises the steps:
A, provide a silicon chip, be formed with at least an aluminium pad and a silicon chip sheath on the wherein said silicon chip, on described silicon chip, form at least the pair of lamina projection, described double-deck projection aluminium coating pad and silicon chip sheath;
B, on silicon chip, also form at least a protective layer, on described protective layer, form at least a conductive layer;
C, on silicon chip surface, form at least the photoresist layer of a layer thickness homogeneous, the complete protective mulch of described photoresist layer and conductive layer;
Expose and develop in d, the place that on silicon chip needs is formed double-deck projection;
E, deposit double-deck projection at silicon chip surface;
F, remove the photoresist layer of silicon chip surface;
Unnecessary metallic region is removed in g, employing chemical etching.
In a preferred embodiment of the present invention, the deposition process of described double-deck projection comprises the steps:
The first, deposit at least a palladium layer at silicon chip surface, described palladium layer covers conductive layer and protective layer at least;
The second, deposit at least one first gold medal layer on palladium layer surface, described the first gold medal layer covers conductive layer, protective layer and palladium layer at least.
In a preferred embodiment of the present invention, the palladium layer of described double-deck projection and the first gold medal layer adopt plating mode to deposit.
In a preferred embodiment of the present invention, in the described electroplating process negative electrode of electroplating is connected silicon chip surface.
In a preferred embodiment of the present invention, described protective layer is titanium tungsten layer, and described titanium tungsten layer is formed on the silicon chip by sputtering way.
In a preferred embodiment of the present invention, described conductive layer is the second gold medal layer, and described the second gold medal layer is formed on the titanium tungsten layer by sputtering way.
In a preferred embodiment of the present invention, described photoresist layer adopts high rotating speed Photoresisting coating machines to form at silicon chip surface.
In a preferred embodiment of the present invention, the place that needs on the described silicon chip to form double-deck projection manifests by the exposure imaging technology, and described light shield all covers double-deck projection.
In a preferred embodiment of the present invention, described chemically etching process comprises the steps:
The first, utilize chemical etching to remove without the need for the zone of titanium tungsten;
The second, utilize chemical etching that unnecessary gold zone is removed.
The invention has the beneficial effects as follows: the manufacturing process flow of IC encapsulating lug of the present invention is simple, can produce the double-deck projection that gold adds palladium, acts in conjunction with wafer and panel, can reduce material cost, life of product is longer, and reliability has strengthened market competitiveness more.
Description of drawings
Fig. 1 is the structural representation of drive IC encapsulating lug one preferred embodiment of the present invention;
Fig. 2 is the structural representation of drive IC encapsulating structure one preferred embodiment of the present invention;
Fig. 3 is that Fig. 7 is the flow chart of the manufacturing process of IC encapsulating lug of the present invention;
The mark of each parts is as follows in the accompanying drawing: 1, the first gold medal layer, 2, the palladium layer, 3, conductive layer, 4, protective layer, 5, the silicon chip sheath, 6, the aluminium pad, 7, encapsulating lug, 8, silicon chip, 9, base plate for packaging, 10, slotted eye, 11, photoresist layer, 12, light shield.
Embodiment
Below in conjunction with accompanying drawing preferred embodiment of the present invention is described in detail, thereby so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that protection scope of the present invention is made more explicit defining.
Be illustrated in figure 1 as the IC encapsulating lug that the present invention is correlated with, it comprises: aluminium pad 6, silicon chip sheath 5, protective layer 4, conductive layer 3 and double-deck projection.
Described aluminium pad 6 is arranged on the silicon chip 8; described aluminium pad 6 is provided with silicon chip sheath 5 with silicon chip 8 surfaces; described double-deck projection is arranged on the aluminium pad 6, and described double-deck projection comprises the first gold medal layer 1 and palladium layer 2, and conductive layer 3 and protective layer 4 are set between described double-deck projection and the silicon chip sheath 5.
Be illustrated in figure 2 as IC encapsulating structure of the present invention, it comprises: silicon chip 8, encapsulating lug 7 and base plate for packaging 9, and described encapsulating lug 7 is arranged on silicon chip 8 surfaces, and the lower surface of described base plate for packaging 9 is provided with slotted eye 10, and described encapsulating lug 7 is disposed in the slotted eye 10.
, comprise the steps: to the manufacturing process that Figure 7 shows that a kind of IC encapsulating lug of the present invention such as Fig. 3
One silicon chip 8 at first is provided, is formed with at least an aluminium pad 6 and a silicon chip sheath 5 on the wherein said silicon chip 8, on described silicon chip 8, form at least the pair of lamina projection, described double-deck projection aluminium coating pad 6 and silicon chip sheath 5.
Described aluminium pad 6 is arranged on and is used for connecting the IC internal wiring on the silicon chip.For being electrically connected, the IC internal information is produced a desired effect via circuit transmission between aluminium pad 6 and the IC internal wiring.
Described aluminium pad 6 is provided with silicon chip sheath 5 with silicon chip surface, and it is mainly as the protective layer of IC internal wiring, and it can prevent the pollution of sealing oxygen or external environment dust, guarantees that IC can normal operation in general environment.
As shown in Figure 3, on silicon chip 8, also form at least a protective layer 4, on described protective layer 4, form at least a conductive layer 3.Described protective layer 4 is titanium tungsten layer, and titanium tungsten layer is formed on the silicon chip by sputtering way.Described conductive layer 3 is the second gold medal layer, and described the second gold medal layer is formed on the titanium tungsten layer by sputtering way.
As shown in Figure 4, on silicon chip 8 surfaces, form at least the photoresist layer 11 of a layer thickness homogeneous, described photoresist layer 11 whole protective mulches 4 and conductive layers 3.Preferably, described photoresist layer 11 adopts high rotating speed Photoresisting coating machines to form on silicon chip 8 surfaces.
To shown in Fig. 5 (b), the place that needs to form double-deck projection 8 of described silicon manifests by the exposure imaging technology such as Fig. 5 (a), and the light shield 12 in the described shadow all covers double-deck projection.
As shown in Figure 6, at the double-deck projection of silicon chip 8 surface depositions.The deposition process of described double-deck projection comprises the steps:
The first, deposit at least a palladium layer 2 on silicon chip 8 surfaces, described palladium layer covers conductive layer 3 and protective layer 4 at least;
The second, deposit at least one first gold medal layer 1 on palladium layer 2 surface, described the first gold medal layer 1 covers conductive layer 3, protective layer 4 and palladium layer 2 at least.
In the process of encapsulation; the hardness of metal is the Consideration of a key, and gold is a metal that suitable hardness can be provided, and not only can guarantee the meeting with stresses of sealer of sheet; also can avoid simultaneously projection to produce deformation, cause adjacent two projections to form short circuit.
Palladium is a kind of very stable material, its price only has the 30%(gold of gold: 330RMB/g palladium: 117 RMB/g), and only need to increase by one program on the program of manufacturing projection, compare with copper nickel gold projection, no matter material cost or processing cost all have market competitiveness.
Adopt the combination of golden palladium projection both can reduce the cost of golden projection, manufacturing process is complicated not as copper nickel gold projection again, and palladium is difficult for the reliability of its product of oxidation considerably beyond copper in air.
Among the present invention, the palladium layer 2 of described double-deck projection and the first gold medal layer 1 adopt plating mode to deposit, and in the described electroplating process negative electrode of electroplating are connected silicon chip surface.
The mode of in the manufacture process of projection, electroplating owing to employing, thus need a good metal of conduction work as conductive layer, and gold is conductivity in all metals, the best metal of ductility, so employing is golden as conductive layer 3 in the encapsulating lug among the present invention.
Titanium tungsten layer mainly contains two functions: the one, work as adhesion layer, and the 2nd, work as barrier layer.
Titanium tungsten can form good associativity with aluminium pad 6, has effectively strengthened the bond strength of projection with IC, and gold can form alloy with aluminium under the operational environment of high temperature in addition, and then has affected the function of IC, and titanium tungsten layer can stop that gold forms alloy with aluminium.
As shown in Figure 7, the photoresist layer 11 on silicon chip 8 surfaces is removed, and adopt the metallic region removal that chemical etching will be unnecessary.Described chemically etching process comprises the steps:
The first, utilize chemical etching to remove without the need for the zone of titanium tungsten;
The second, utilize chemical etching that unnecessary gold zone is removed, thus complete whole manufacturing process.
The manufacturing process beneficial effect of IC encapsulating lug of the present invention is:
Gold copper-base alloy has stability, and the price of gold and palladium material, processing cost etc. are added up more cheap than the copper nickel gold projection of present industry use, and be more attractive to the client;
Flow process is simple, can produce the double-deck projection that gold adds palladium, acts in conjunction with wafer and panel, can reduce material cost, and life of product is longer, and reliability has strengthened market competitiveness more.
The above only is embodiments of the invention; be not so limit claim of the present invention; every equivalent structure or equivalent flow process conversion that utilizes specification of the present invention and accompanying drawing content to do; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.
Claims (9)
1. the manufacturing process of an IC encapsulating lug is characterized in that, comprises the steps:
A, provide a silicon chip, be formed with at least an aluminium pad and a silicon chip sheath on the wherein said silicon chip, on described silicon chip, form at least the pair of lamina projection, described double-deck projection aluminium coating pad and silicon chip sheath;
B, on silicon chip, also form at least a protective layer, on described protective layer, form at least a conductive layer;
C, on silicon chip surface, form at least the photoresist layer of a layer thickness homogeneous, the complete protective mulch of described photoresist layer and conductive layer;
Expose and develop in d, the place that on silicon chip needs is formed double-deck projection;
E, deposit double-deck projection at silicon chip surface;
F, remove the photoresist layer of silicon chip surface;
Unnecessary metallic region is removed in g, employing chemical etching.
2. the manufacturing process of IC encapsulating lug according to claim 1 is characterized in that, the deposition process of described double-deck projection comprises the steps:
The first, deposit at least a palladium layer at silicon chip surface, described palladium layer covers conductive layer and protective layer at least;
The second, deposit at least one first gold medal layer on palladium layer surface, described the first gold medal layer covers conductive layer, protective layer and palladium layer at least.
3. the manufacturing process of IC encapsulating lug according to claim 2 is characterized in that, the palladium layer of described double-deck projection and the first gold medal layer adopt plating mode to deposit.
4. the manufacturing process of IC encapsulating lug according to claim 3 is characterized in that, in the described electroplating process negative electrode of electroplating is connected silicon chip surface.
5. the manufacturing process of IC encapsulating lug according to claim 1 is characterized in that, described protective layer is titanium tungsten layer, and described titanium tungsten layer is formed on the silicon chip by sputtering way.
6. the manufacturing process of IC encapsulating lug according to claim 5 is characterized in that, described conductive layer is the second gold medal layer, and described the second gold medal layer is formed on the titanium tungsten layer by sputtering way.
7. the manufacturing process of IC encapsulating lug according to claim 1 is characterized in that, described photoresist layer adopts high rotating speed Photoresisting coating machines to form at silicon chip surface.
8. the manufacturing process of IC encapsulating lug according to claim 1 is characterized in that, the place that needs on the described silicon chip to form double-deck projection manifests by the exposure imaging technology, and described light shield all covers double-deck projection.
9. the manufacturing process of IC encapsulating lug according to claim 6 is characterized in that, described chemically etching process comprises the steps:
The first, utilize chemical etching to remove without the need for the zone of titanium tungsten;
The second, utilize chemical etching that unnecessary gold zone is removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210293532XA CN102856221A (en) | 2012-08-17 | 2012-08-17 | Manufacturing process for IC (integrated circuit) packaging bump |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210293532XA CN102856221A (en) | 2012-08-17 | 2012-08-17 | Manufacturing process for IC (integrated circuit) packaging bump |
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| CN102856221A true CN102856221A (en) | 2013-01-02 |
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| CN201210293532XA Pending CN102856221A (en) | 2012-08-17 | 2012-08-17 | Manufacturing process for IC (integrated circuit) packaging bump |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108615688A (en) * | 2018-05-08 | 2018-10-02 | 江苏汇成光电有限公司 | A kind of golden bumping manufacturing process of IC chip |
| CN109727949A (en) * | 2019-02-22 | 2019-05-07 | 江苏汇成光电有限公司 | A kind of silicon wafer encapsulating structure and preparation method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1750258A (en) * | 2004-09-15 | 2006-03-22 | 三星电子株式会社 | Comprise microelectronic device chip and encapsulation, application and the manufacturing of hybrid au bump |
| CN101221912A (en) * | 2007-01-12 | 2008-07-16 | 百慕达南茂科技股份有限公司 | Multi-layer projection structure and manufacturing method thereof |
| CN102074486A (en) * | 2009-10-20 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Method of forming an integrated circuit structure |
| CN102214616A (en) * | 2010-12-31 | 2011-10-12 | 友达光电股份有限公司 | Metal conductive structure and manufacturing method thereof |
| CN102543766A (en) * | 2012-01-17 | 2012-07-04 | 南通富士通微电子股份有限公司 | Columnar bump packaging process |
| CN102543895A (en) * | 2010-12-21 | 2012-07-04 | 南茂科技股份有限公司 | Bump structure and manufacturing method thereof |
-
2012
- 2012-08-17 CN CN201210293532XA patent/CN102856221A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1750258A (en) * | 2004-09-15 | 2006-03-22 | 三星电子株式会社 | Comprise microelectronic device chip and encapsulation, application and the manufacturing of hybrid au bump |
| CN101221912A (en) * | 2007-01-12 | 2008-07-16 | 百慕达南茂科技股份有限公司 | Multi-layer projection structure and manufacturing method thereof |
| CN102074486A (en) * | 2009-10-20 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Method of forming an integrated circuit structure |
| CN102543895A (en) * | 2010-12-21 | 2012-07-04 | 南茂科技股份有限公司 | Bump structure and manufacturing method thereof |
| CN102214616A (en) * | 2010-12-31 | 2011-10-12 | 友达光电股份有限公司 | Metal conductive structure and manufacturing method thereof |
| CN102543766A (en) * | 2012-01-17 | 2012-07-04 | 南通富士通微电子股份有限公司 | Columnar bump packaging process |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108615688A (en) * | 2018-05-08 | 2018-10-02 | 江苏汇成光电有限公司 | A kind of golden bumping manufacturing process of IC chip |
| CN109727949A (en) * | 2019-02-22 | 2019-05-07 | 江苏汇成光电有限公司 | A kind of silicon wafer encapsulating structure and preparation method thereof |
| CN109727949B (en) * | 2019-02-22 | 2024-04-16 | 江苏汇成光电有限公司 | Silicon chip packaging structure and preparation method thereof |
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Application publication date: 20130102 |