CN102971845A - 半导体元件搭载用基板及其制造方法 - Google Patents

半导体元件搭载用基板及其制造方法 Download PDF

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CN102971845A
CN102971845A CN201180029619XA CN201180029619A CN102971845A CN 102971845 A CN102971845 A CN 102971845A CN 201180029619X A CN201180029619X A CN 201180029619XA CN 201180029619 A CN201180029619 A CN 201180029619A CN 102971845 A CN102971845 A CN 102971845A
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superimposed portions
crystal grain
grain diameter
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CN102971845B (zh
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蒲原英彦
三上顺太郎
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Sumitomo Metal Mining Co Ltd
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Abstract

本发明提供一种半导体元件搭载用基板及其制造方法，其端子部与密封树脂的结合力出色、端子部与键合线的连接性出色，能降低制造成本，且能充分应对半导体装置的小型化、薄型化。该半导体元件搭载用基板至少具有端子部（3），该端子部（3）具有使用同种金属或同种合金构成为相邻层（10、11）之间平均晶粒直径不同的多层状的层状部（12），并且，在层状部（12）的侧面通过实施蚀刻加工形成有在相邻层（10、11）之间构成台阶的凹部。

Description

半导体元件搭载用基板及其制造方法
技术领域
本发明涉及利用镀敷形成端子部的半导体元件搭载用基板及其制造方法。
背景技术
以往，公知有一种半导体装置的制造方法，通过在导电性基板的一表面侧形成规定的抗蚀图案层，然后在导电性基板的自该抗蚀图案层暴露的表面电沉积超过抗蚀图案层厚度的导电性金属，而独立且并列形成上端部周缘具有突出部的半导体元件搭载用的金属层和电极层，之后除去抗蚀图案层，将半导体元件搭载于金属层上，用键合线（日文：ボンデイングワイヤ）电连接电极层和半导体元件上的电极，用树脂密封半导体元件搭载部分，之后除去基板，获得金属层的背面和电极层的背面暴露的树脂密封体（例如，参照专利文献1）。
根据专利文献1所述的半导体装置的制造方法，由于突出部以陷入到密封树脂中的状态存在，因此利用锚固效果提高了金属层及电极层同密封树脂的结合力，在后续工序中揭去基板时，金属层、电极层的必要零件不会残留于基板侧，而是以埋没于树脂密封体侧的状态被转印，能有效防止金属层、电极层的错位、脱落等。
另外，利用遍布金属层及电极层的上端部周缘整周地形成的特有的突出形状，能够阻止从半导体装置背面侧通过金属层及电极层的各层同密封树脂之间的边界部分进入的水分，而制造出耐湿性出色的装置。
但是，在专利文献1所述的制造方法中，由于进行超过抗蚀图案层的电沉积，因此超过抗蚀图案层厚度的部分的电沉积处于完全不受抗蚀图案层制约的状态，容易受到电流密度分布等的影响，难以确保突出部的长度恒定，存在金属层、电极层同密封树脂的结合力产生波动的问题。另外，金属层、电极层的上表面的电沉积也完全不受制约，因此上表面没有成为平面，而形成为半球面状，存在容易发生键合线连接不良的问题。
另外，以往，还公知一种不同于专利文献1所述的半导体装置的制造方法的半导体元件搭载用基板的制造方法，在导电性基板的一表面侧形成实施了规定图案加工的抗蚀图案层，在基板的从抗蚀图案层暴露的表面，通过镀敷形成不超过抗蚀图案层厚度的范围内的、由包括下层、中间层及上层在内的三层以上构成的导电性金属，之后，除去抗蚀图案层，实施蚀刻处理而进行使上述中间层宽度小于上述下层宽度及上层宽度的加工，从而独立且并列形成其剖面形状中中间层形成为凹状的半导体元件搭载用的金属层（焊盘部）和电极层（端子部），然后，将半导体元件搭载于金属层上，用键合线电连接电极层和半导体元件上的电极，用树脂密封半导体元件搭载部分，之后除去基板，获得金属层的背面和电极层的背面暴露的树脂密封体（例如，参照专利文献2）。
根据专利文献2所述的半导体元件搭载用基板的制造方法，由于金属层的中间层及电极层的中间层形成得小于上下层，因此，密封树脂同金属层及电极层之间显示出出色的密合性，另外，由于最初形成于基板上的下层由镀金形成，因此，提高了下层和基板的密合性，能防止密封树脂蔓延至基板和下层之间。
另外，由于不用进行超过抗蚀图案层厚度的电铸，因此，金属层、电极层的横向大小均匀，金属层、电极层同密封树脂的结合力较高且稳定，电极层的上表面平坦而使焊接性出色，并且能充分应对半导体装置的小型化、薄型化。
在先技术文献
专利文献
专利文献1：日本特开2002－9196号公报
专利文献2：日本特开2009－135417号公报
发明内容
发明要解决的问题
但是，在专利文献2所述的结构中，需要层叠镀敷多种导电性金属，因此其工序复杂，在降低成本方面存在课题。
本发明是鉴于上述现有技术的问题点而完成的，其目的在于，提供一种端子部与密封树脂的结合力出色、端子部与键合线的连接性出色，能降低制造成本，且能充分应对半导体装置的小型化、薄型化的半导体元件搭载用基板及其制造方法。
用于解决问题的方案
本发明的半导体元件搭载用基板其特征在于，至少具有端子部，该端子部具有使用同种金属或同种合金构成为相邻层之间平均晶粒直径不同的多层状的层状部，并且，在上述层状部的侧面形成有在上述相邻层之间构成台阶的凹部。另外，在本发明的半导体元件搭载用基板中，优选上述层状部由三层以上构成。另外，在本发明的半导体元件搭载用基板中，优选上述层状部中的上述相邻层之间的上述同种金属或同种合金的平均晶粒直径之差为0.5μm以上。
另外，本发明的半导体元件搭载用基板的制造方法其特征在于，该方法包括以下工序：层状部形成工序，该工序通过对形成有具有至少包括端子部形成用区域在内的规定暴露区域的抗蚀图案层的导电性基板实施镀敷处理，从而在上述导电性基板的暴露区域形成使用同种金属或同种合金构成为相邻层之间平均晶粒直径不同的多层状，且厚度为抗蚀图案层的厚度以下的层状部；以及台阶形成工序，该工序通过对经上述层状部形成工序形成了上述层状部的导电性基板实施蚀刻加工，而在上述层状部的侧面形成在上述相邻层之间构成台阶的凹部。
另外，在本发明的半导体元件搭载用基板的制造方法中，优选在上述层状部形成工序中通过改变电流密度地实施镀敷处理，而使上述层状部中的每个相邻层之间的上述同种金属或同种合金的平均晶粒直径发生变化。
发明的效果
采用本发明，能获得一种能降低制造成本，尽管其制造方法工序简单但端子部与密封树脂的结合性出色，从树脂密封体揭去基板时基板不会残留已形成的镀层，另外，端子部与键合线的连接性出色，可靠性高的半导体元件搭载用基板及其制造方法。
附图说明
图1是表示本发明一实施方式的半导体元件搭载用基板中的端子部的概略结构的剖视图，图1（a）是表示一例半导体元件搭载用基板的端子部的剖视图，图1（b）是表示另一例半导体元件搭载用基板的端子部的剖视图。
图2是以剖面表示包括本发明一实施方式的半导体元件搭载用基板的制造方法在内的、半导体装置的制造工序的说明图，图2（a）是表示在导电性基板上形成了抗蚀剂掩膜的状态的图，图2（b）是表示在图2（a）的形成了抗蚀剂掩膜的基板的暴露区域形成了包括层状部在内的镀层的状态的图，图2（c）是表示从形成了镀层的基板除去抗蚀剂掩膜，实施蚀刻处理而形成了本发明一实施方式的半导体元件搭载用基板的状态的图，图2（d）是表示在图2（c）的半导体元件搭载用基板所具有的层状部的侧面形成的台阶的放大图，图2（e）是表示将半导体元件搭载于图2（c）的半导体元件搭载用基板上并用键合线连接端子部和半导体元件的电极，之后，用树脂对它们进行了密封的状态的图，图2（f）是表示从图2（e）所示的密封树脂体揭去导电性基板而完成了的半导体装置的图。
图3是表示使用作为本发明变形例的仅有端子部而没有半导体搭载部的半导体元件搭载用基板制造出的半导体装置的概略结构的剖视图。
图4是表示制造本发明的实施例1的半导体元件搭载用基板时，对使用同种金属或同种合金形成有构成为相邻层之间平均晶粒直径不同的多层状的层状部的导电性基板实施蚀刻加工时的、在蚀刻液中浸渍的时间和相邻层之间的台阶间的关系的曲线图。
具体实施方式
在说明实施例之前，先说明本发明的作用效果。
采用本发明的半导体元件搭载用基板及其制造方法，由于通过镀敷平均晶粒直径不同的同一金属或同一合金而形成端子部中的层状部，因此，只需一种用于形成层状部的镀敷液即可，也不需要准备多种镀敷装置，管理起来也很容易。
构成该层状部的平均晶粒直径不同的镀层对于蚀刻液的溶解性不同，晶粒直径小的层溶解得快。这是因为，蚀刻是沿着晶界深入的，因此晶界多的平均晶粒直径小的层会优先溶解。
这样获得的端子部在其侧面形成有在相邻层之间构成台阶的凹部。因此，采用本发明，不像专利文献1的制造方法那样通过进行超过抗蚀图案层厚度的电铸来形成突出部，就能提高端子部和形成密封树脂的结合性。另外，由于不用进行超过抗蚀图案层厚度的电铸，因此能使层状部的上表面形成得平坦，端子部与键合线的连接性出色。
图1（a）和图1（b）是表示本发明一实施方式的半导体元件搭载用基板中的端子部的概略剖视图。本发明一实施方式的半导体元件搭载用基板其基板1上的最上层和最下层由金镀层13构成。在金镀层13之间具有层状部12，层状部12由平均晶粒直径大的镍镀层10和平均晶粒直径小的镍镀层11层叠而成。通过实施蚀刻加工，在层状部12的层叠出的侧面，形成有在相邻层之间平均晶粒直径小的镍镀层11的侧面相对于平均晶粒直径大的镍镀层10的侧面凹进的状态的台阶。
并且，图1（a）是表示作为一例半导体元件搭载用基板，由四层平均晶粒直径大的镍镀层10和三层平均晶粒直径小的镍镀层11构成端子部3的层状部12的状态的图，图1（b）是表示作为另一例半导体元件搭载用基板，由两层平均晶粒直径大的镍镀层11和一层平均晶粒直径小的镍镀层10构成端子部3的层状部12的状态的图。
接着，在半导体装置的制造工序中说明本发明的半导体元件搭载用基板的制造方法的一实施方式。图2是以剖面表示包括本发明的半导体元件搭载用基板的制造方法的工序在内的、半导体装置的制造工序的说明图。
在制造本发明的半导体元件搭载用基板时，作为前处理，例如在由不锈钢构成的导电性基板1的两表面粘贴由感光性干膜构成的抗蚀剂掩膜2。然后，将形成有具有镀敷用暴露区域的掩膜图案的玻璃掩膜（省略图示）覆盖于基板1的一个表面的抗蚀剂掩膜2上，通过进行曝光、显影处理，而形成具有至少包括端子部形成用区域在内的规定暴露区域的抗蚀图案层2a（图2（a））。另外，在图2的例子中，暴露区域除了包括端子部形成用区域2a1之外，还包括半导体元件搭载部（焊盘部）形成用区域2a2。
接着，对形成了抗蚀图案层2a的基板1实施镀敷前处理，然后在暴露区域2a1、暴露区域2a2上实施镀金。
接下来，例如使用镍等同种金属或同种合金，在实施了镀金的暴露区域2a1、暴露区域2a2上以使相邻层之间的平均粒径不同地进行层叠的方式实施镀敷处理，形成例如图1（a）、图1（b）所示那样的、厚度为抗蚀图案层2a厚度以下的构成为多层状的层状部12。
接着，在形成后的层状部12上实施镀金（图2（b））。
接下来，剥离除去形成于基板1的两表面的抗蚀剂掩膜2a、抗蚀剂掩膜2b，通过在能够溶解镍的溶液中浸渍规定时间来实施蚀刻加工处理。由此，如图2（c）所示，制成了在基板1上具有端子部3和半导体元件搭载部（焊盘部）4的半导体元件搭载用基板。此时，如上所述，由于构成层状部12的平均晶粒直径不同的镀层10、镀层11对于蚀刻液的溶解性不同，晶粒直径小的镀层溶解得快，因此，在层状部12的侧面形成了在相邻层10、镀层11之间构成台阶的凹部（图2（d））。
这样，便获得了本发明的半导体元件搭载用基板。
在制造半导体装置时，将半导体元件5搭载于用上述制造方法获得的半导体元件搭载用基板上的规定部位（图2的例子中为半导体元件搭载部4），用键合线6连接端子部3和半导体元件5的电极，之后，用树脂7将基板的用键合线6连接起来的半导体元件5及端子部3这一侧密封起来（图2（e））。
接着，待密封的树脂7固化之后，从树脂密封体揭去导电性基板1。由此，获得了端子部3及半导体元件搭载部4中的半导体元件5这一侧被树脂7密封，其背面侧暴露的半导体装置（图2（f））。
另外，本发明的半导体搭载用基板并不限定于图2所示那样具有端子部3和半导体搭载部4的结构，也可以是仅有端子部3而没有半导体搭载部的结构，以适于制造图3所示那样半导体装置。
在制造图3所示的半导体装置时，使用上述的未图示的在导电性基板上仅形成了端子部的本发明的半导体元件搭载用基板，将半导体元件直接搭载于导电性基板的规定位置，用键合线连接端子部和半导体元件的电极，之后，用树脂将基板的用键合线连接起来的半导体元件及端子部这一侧密封起来。
接着，待密封的树脂固化后，从树脂密封体揭去导电性基板。由此，获得了端子部3及半导体元件5的连接键合线6这一侧被树脂7密封，其背面侧呈暴露的状态的半导体装置。
实施例1
实施例1是具有图1（a）所示的结构的半导体元件搭载用基板的实施例。
用板厚为0.2mm的不锈钢（SUS430）作为基板1，进行脱脂、酸洗处理之后，用层压辊将厚0.050mm的感光性干膜抗蚀剂粘贴于基板1的两表面，然后，将形成有镀敷掩膜图案的玻璃掩膜覆盖在基板1的一个表面的干膜抗蚀剂上，然后通过从其上照射紫外光曝光并进行显影处理，形成由干膜抗蚀剂形成了规定图案的抗蚀剂掩膜2a，在基板1的另一侧的表面形成了覆盖整个表面的抗蚀剂掩膜2b（图2（a））。
接下来，对基板1中的从抗蚀剂掩膜2a暴露的区域2a1、区域2a2实施镀敷前处理，然后实施厚度为1μm的镀金，接着，使用氨基磺酸镍浴在金镀层上进行镀镍，以15A/dm2的电流密度形成厚度为5μm的平均晶粒直径约为0.8μm的镍镀层10，再以5A/dm2的电流密度形成厚度为5μm的平均晶粒直径约为0.3μm的镍镀层11。然后再在镍镀层11上同样地交替层叠平均晶粒直径约为0.8μm的镍镀层10和平均晶粒直径约为0.3μm的镍镀层11来形成层叠部12，再在层叠部12上实施3μm厚的镀金。由此，形成了具有四层平均晶粒直径约为0.8μm的镍镀层10、三层平均晶粒直径约为0.3μm的镍镀层11，且最下层和最上层由金镀层13构成的端子部3（图2（b））。
接着，剥离除去形成于基板1的两表面的抗蚀剂掩膜2a、抗蚀剂掩膜2b（图2（c）），使用能够溶解镍的溶液（例如，NH－1860系列：美格（日文：メツク）株式会社制），在室温下，进行0.5分钟、1.5分钟、2.5分钟、3.5分钟的浸渍处理，由此，在端子部3侧面的镍镀层10、镍镀层11间形成了约为0.3μm～2.8μm的台阶（图2（d））。该台阶是利用平均晶粒直径小的镍镀层11的蚀刻速度大于平均晶粒直径大的镍镀层10的蚀刻速度的原理而形成的。该浸渍时间和台阶的结果示于图4。
为了判断接合性，使用粘晶用胶（日文：ダイボンド用ペ一スト）将半导体元件5搭载于通过上述工序所得的半导体元件搭载用基板，用键合线6连接端子部3和半导体元件5的电极，之后，用树脂7进行密封（图2（e）），待密封树脂固化后，从树脂密封体揭去作为基板1的不锈钢（图2（f））。
详细观察揭下来的不锈钢侧，结果确认到，对于进行了0.5分钟的浸渍处理而在端子部3侧面的镍镀层形成了约0.3μm的台阶的半导体元件搭载用基板而言，在不锈钢侧散布有残留着已形成的镀层的部分，端子部3和密封树脂7的接合性低，但对于进行了1.5分钟以上的浸渍处理而在端子部3侧面的镍镀层形成了约1μm以上的台阶的半导体元件搭载用基板而言，在不锈钢侧均不存在残留着镀层的部分，另外，也不存在端子部3从密封树脂7松动或脱落的现象，良好地保持了端子部3和密封树脂7的接合性。
比较例1
比较例1是与实施例1的半导体元件搭载用基板进行对比的比较例。
与实施例1同样使用不锈钢作为基板，形成抗蚀剂掩膜，进行镀敷前处理，接着，实施镀金直至厚度达到1μm，然后使用氨基磺酸镍浴在金镀层上镀镍，以15A/dm2的电流密度形成平均晶粒直径约为0.8μm的镍镀层直至厚度达到5μm，接着以10A/dm2的电流密度形成平均晶粒直径约为0.5μm的镍镀层直至厚度达到5μm。然后，在该平均晶粒直径约为0.5μm的镍镀层上同样地交替层叠平均晶粒直径约为0.8μm的镍镀层和平均晶粒直径约为0.5μm的镍镀层，再于最上层的镍镀层其上实施了厚度为3μm的镀金。由此，形成了具有四层平均晶粒直径约为0.8μm的镍镀层、三层平均晶粒直径约为0.5μm的镍镀层，且最下层和最上层由金镀层构成的端子部。
接下来，与实施例1同样地剥离除去抗蚀剂掩膜，使用能够溶解镍的溶液，在室温下进行1.5分钟的浸渍处理，但在端子部的镍镀层侧面仅获得了0.3μm左右的台阶。因此，根据实施例1的结果，可断定比较例1生产率差，且台阶仅为0.3μm左右的话，接合性差。
实施例2
实施例2是具有图1（b）所示的结构的半导体元件搭载用基板的实施例。
与实施例1同样使用不锈钢作为基板，形成抗蚀剂掩膜，进行镀敷前处理，实施1μm厚的镀金，接着，使用氨基磺酸镍浴在金镀层上实施镀镍，以15A/dm2的电流密度形成厚度为10μm的平均晶粒直径约为0.8μm的镍镀层，再于该镍镀层上以5A/dm2的电流密度形成厚度为15μm的平均晶粒直径约为0.3μm的镍镀层，然后，再以15A/dm2的电流密度形成厚度为10μm的平均晶粒直径约为0.8μm的镍镀层，再于最上层的镍镀层上实施了厚度为3μm的镀金。
接着，与实施例1同样地剥离除去抗蚀剂掩膜，使用能够溶解镍的溶液，在室温下进行1.5分钟的浸渍处理，搭载半导体元件，用键合线连接端子部和半导体元件的电极，进行树脂密封，从树脂密封体揭去不锈钢，观察不锈钢侧，结果均不存在残留着镀层的部分。
产业上的可利用性
本发明的半导体搭载用基板及其制造方法作为能降低制造成本，尽管其制造方法工序简单但端子部和密封树脂的密合性出色，从树脂密封体揭去基板时基板不会残留已形成的镀层，可靠性高的半导体元件搭载用基板及其制造方法，能发挥极其出色的效果，因此可期待广泛用于该产业领域。
附图标记说明
1、基板；2、抗蚀剂掩膜；2a、形成了抗蚀图案层的抗蚀剂掩膜；2a1、端子部形成用暴露区域；2a2、半导体元件搭载部形成用暴露区域；2b、覆盖基板整个表面的抗蚀剂掩膜；3、端子部；4、半导体元件搭载部；5、半导体元件；6、键合线；7、树脂；10、平均晶粒直径大的层；11、平均晶粒直径小的层；12、层状部；13、金镀层

Claims (5)

1.一种半导体元件搭载用基板，其特征在于，
该基板至少具有端子部，
该端子部具有使用同种金属或同种合金构成为相邻层之间平均晶粒直径不同的多层状的层状部，并且，在上述层状部的侧面形成有在上述相邻层之间构成台阶的凹部。
2.根据权利要求1所述的半导体元件搭载用基板，其特征在于，
上述层状部构成为三层以上的层状。
3.根据权利要求1所述的半导体元件搭载用基板，其特征在于，
上述层状部中的上述相邻层之间的上述同种金属或同种合金的平均晶粒直径之差为0.5μm以上。
4.一种半导体元件搭载用基板的制造方法，其特征在于，
该方法包括以下工序：
层状部形成工序，该工序通过对形成有具有至少包括端子部形成用区域在内的规定暴露区域的抗蚀图案层的导电性基板实施镀敷处理，而在上述导电性基板的暴露区域形成使用同种金属或同种合金构成为相邻层之间平均晶粒直径不同的多层状，且厚度为抗蚀图案层的厚度以下的层状部；以及
台阶形成工序，该工序通过对经上述层状部形成工序形成了上述层状部的导电性基板实施蚀刻加工，而在上述层状部的侧面形成在上述相邻层之间构成台阶的凹部。
5.根据权利要求4所述的半导体元件搭载用基板的制造方法，其特征在于，
在上述层状部形成工序中，通过改变电流密度地实施镀敷处理，而使上述层状部中的每个相邻层之间的上述同种金属或同种合金的平均晶粒直径发生变化。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109285823A (zh) * 2017-07-19 2019-01-29 大口电材株式会社 半导体元件搭载用基板以及其制造方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6362337B2 (ja) * 2014-01-21 2018-07-25 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
WO2017133758A1 (en) * 2016-02-02 2017-08-10 Osram Opto Semiconductors Gmbh Lead frame and method for producing a lead frame
JP2018170333A (ja) * 2017-03-29 2018-11-01 株式会社東芝 半導体装置及びその製造方法
US10475666B2 (en) 2017-04-21 2019-11-12 Asm Technology Singapore Pte Ltd Routable electroforming substrate comprising removable carrier
US20180308421A1 (en) * 2017-04-21 2018-10-25 Asm Technology Singapore Pte Ltd Display panel fabricated on a routable substrate
JP6927634B2 (ja) * 2017-09-20 2021-09-01 大口マテリアル株式会社 半導体素子搭載用基板及びその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002009196A (ja) * 2000-06-20 2002-01-11 Kyushu Hitachi Maxell Ltd 半導体装置の製造方法
CN1295645C (zh) * 2001-12-28 2007-01-17 大日本印刷株式会社 非接触式数据载体的制造方法
US20090114345A1 (en) * 2007-11-07 2009-05-07 Sumitomo Metal Mining Co., Ltd. Method for manufacturing a substrate for mounting a semiconductor element

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06196324A (ja) * 1992-12-25 1994-07-15 Matsushita Electric Ind Co Ltd 多層構造薄膜およびその製法
JP3833892B2 (ja) * 2000-12-20 2006-10-18 本田技研工業株式会社 Ｎｉ−Ｃｕ合金メッキ被膜
JP2004253574A (ja) * 2003-02-19 2004-09-09 Fuji Electric Holdings Co Ltd 半導体装置
JP4245370B2 (ja) * 2003-02-21 2009-03-25 大日本印刷株式会社 半導体装置の製造方法
JP2005072290A (ja) * 2003-08-26 2005-03-17 Mitsui Mining & Smelting Co Ltd プリント配線板用銅箔及びそのプリント配線板用銅箔の製造方法並びにそのプリント配線板用銅箔を用いた銅張積層板
KR100884662B1 (ko) * 2004-07-15 2009-02-18 다이니폰 인사츠 가부시키가이샤 반도체장치와 반도체장치 제조용 기판 및 그들의 제조방법
JP5001542B2 (ja) * 2005-03-17 2012-08-15 日立電線株式会社 電子装置用基板およびその製造方法、ならびに電子装置の製造方法
JP2008306128A (ja) * 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
JP2009135417A (ja) * 2007-11-07 2009-06-18 Sumitomo Metal Mining Co Ltd 半導体素子搭載用基板の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002009196A (ja) * 2000-06-20 2002-01-11 Kyushu Hitachi Maxell Ltd 半導体装置の製造方法
CN1295645C (zh) * 2001-12-28 2007-01-17 大日本印刷株式会社 非接触式数据载体的制造方法
US20090114345A1 (en) * 2007-11-07 2009-05-07 Sumitomo Metal Mining Co., Ltd. Method for manufacturing a substrate for mounting a semiconductor element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109285823A (zh) * 2017-07-19 2019-01-29 大口电材株式会社 半导体元件搭载用基板以及其制造方法

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