WO2011158731A1 - 半導体素子搭載用基板及びその製造方法 - Google Patents

半導体素子搭載用基板及びその製造方法 Download PDF

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Publication number
WO2011158731A1
WO2011158731A1 PCT/JP2011/063266 JP2011063266W WO2011158731A1 WO 2011158731 A1 WO2011158731 A1 WO 2011158731A1 JP 2011063266 W JP2011063266 W JP 2011063266W WO 2011158731 A1 WO2011158731 A1 WO 2011158731A1
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Prior art keywords
substrate
semiconductor element
layer
crystal grain
average crystal
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PCT/JP2011/063266
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English (en)
French (fr)
Inventor
英彦 蒲原
順太郎 三上
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住友金属鉱山株式会社
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Application filed by 住友金属鉱山株式会社 filed Critical 住友金属鉱山株式会社
Priority to CN201180029619.XA priority Critical patent/CN102971845B/zh
Priority to KR1020127032408A priority patent/KR101402450B1/ko
Publication of WO2011158731A1 publication Critical patent/WO2011158731A1/ja

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating

Definitions

  • the present invention relates to a semiconductor element mounting substrate on which a terminal portion is formed by plating and a method for manufacturing the same.
  • a metal layer for mounting a semiconductor element having an overhanging portion on the periphery of the upper end portion and an electrode layer are formed in parallel independently, and then the resist pattern layer is removed, and the semiconductor element is mounted on the metal layer.
  • the electrode and the electrode layer are electrically connected by a bonding wire, the semiconductor element mounting portion is sealed with resin, and then the substrate is removed to obtain a resin sealed body in which the back surfaces of the metal layer and the electrode layer are exposed.
  • a method for manufacturing a semiconductor device is known (for example, see Patent Document 1).
  • the anchoring effect improves the bonding force between the metal layer and the electrode layer and the sealing resin.
  • the necessary parts of the metal layer and electrode layer are transferred without being left on the substrate side and embedded in the resin sealing body side, effectively shifting or missing the metal layer or electrode layer, etc. Can be prevented.
  • moisture that penetrates through the boundary portion between the metal layer and the electrode layer from the back side of the semiconductor device and the sealing resin due to the unique protruding shape formed over the entire periphery of the upper edge of the metal layer and the electrode layer Can be prevented and the moisture resistance can be improved.
  • a resist pattern layer subjected to predetermined buttering is formed on one side of a conductive substrate, and the substrate is exposed from the resist pattern layer.
  • the resist pattern layer is removed and an etching treatment is performed to form the intermediate layer.
  • the semiconductor element is mounted on the metal layer, and the electrode on the semiconductor element and the electrode layer are electrically connected by a bonding wire so that the semiconductor element mounting portion is
  • a method for manufacturing a semiconductor element mounting substrate is known in which a substrate is removed and a resin sealing body in which the back surfaces of the metal layer and the electrode layer are exposed is obtained (for example, Patent Document 2). reference).
  • the intermediate layer of the metal layer and the electrode layer is formed to be smaller than the upper and lower layers, so that the sealing resin, the metal layer, and the electrode layer are formed.
  • Excellent adhesion, and the first lower layer formed on the substrate by gold plating improves the adhesion to the substrate and prevents the sealing resin from flowing between the substrate and the lower layer it can.
  • the electroforming is not performed beyond the thickness of the resist pattern layer, the lateral dimensions of the metal layer and the electrode layer are uniform, the bonding force with the sealing resin is stable and high, and the upper surface of the electrode layer is flat. It has excellent bonding properties and can sufficiently cope with the downsizing and thinning of semiconductor devices.
  • the present invention has been made in view of the above-described problems of the prior art, and the terminal portion has excellent bonding strength with a sealing resin and connectivity with a bonding wire, can reduce manufacturing costs, and reduce the size of a semiconductor device.
  • Another object of the present invention is to provide a semiconductor element mounting substrate that can sufficiently cope with the reduction in thickness and a manufacturing method thereof.
  • a substrate for mounting a semiconductor element according to the present invention has a layered portion configured in a plurality of layers having different average crystal grain sizes of adjacent layers using the same type of metal or alloy, and a side surface of the layered portion Is characterized in that it has at least a terminal portion in which a concave portion having a step is formed between the adjacent layers.
  • the layered portion is composed of three or more layers.
  • a difference in average crystal grain size of the same type of metal or alloy between the adjacent layers in the layered portion is 0.5 ⁇ m or more.
  • the method for manufacturing a semiconductor element mounting substrate includes performing a plating process on a conductive substrate on which a resist pattern layer having a predetermined exposed region including at least a region for forming a terminal portion is formed.
  • a layered portion configured in a plurality of layers having different average crystal grain sizes of adjacent layers using the same type of metal or alloy is provided with a thickness equal to or less than the thickness of the resist pattern layer.
  • Forming a step between the adjacent layers on the side surface of the layered portion by etching the conductive substrate on which the layered portion is formed through the layered portion forming step. It is characterized by having a step forming step for forming a concave portion with a mark.
  • the same kind of metal is used for each adjacent layer in the layered portion by performing plating treatment while changing the current density.
  • the manufacturing cost can be reduced, and the bonding method between the terminal portion and the sealing resin is excellent and the substrate is peeled off from the resin sealing body even though the manufacturing method is a simple process.
  • the formed plating layer does not remain, and a highly reliable semiconductor element mounting substrate having excellent connectivity between the terminal portion and the bonding wire and its manufacturing method can be obtained.
  • FIG. 1 is a cross-sectional view showing a schematic configuration of a terminal portion in a semiconductor element mounting substrate according to an embodiment of the present invention
  • (a) is a cross-sectional view showing a terminal portion of a semiconductor element mounting substrate according to an example thereof.
  • b) is a cross-sectional view showing a terminal portion of a semiconductor element mounting substrate according to another example.
  • FIG. 2 is a cross-sectional view illustrating a semiconductor device manufacturing process including a method for manufacturing a semiconductor element mounting substrate according to an embodiment of the present invention.
  • FIG. 2A shows a state in which a resist mask is formed on a conductive substrate.
  • FIG. B is a diagram showing a state in which a plating layer including a layered portion is formed in an exposed region of the substrate on which the resist mask of (a) is formed, and (c) is a resist from the substrate on which the plating layer is formed.
  • (d) is the layered part with which the semiconductor element mounting substrate of (c) is equipped Enlarged view showing the step formed on the side
  • (e) shows the mounting of the semiconductor element on the substrate for mounting the semiconductor element of (c), and after connecting the electrode of the semiconductor element and the terminal part with a bonding wire, these are made of resin.
  • FIG. 3 is a cross-sectional view showing a schematic configuration of a semiconductor device manufactured using a semiconductor element mounting substrate having only a terminal portion and no semiconductor mounting portion as a modification of the present invention.
  • FIG. 4 shows a layered structure composed of a plurality of layers in which the average crystal grain size of adjacent layers is different using the same type of metal or alloy in manufacturing the semiconductor element mounting substrate according to the first embodiment of the present invention. It is a graph which shows the relationship between the immersion time in etching liquid, and the level
  • the layered portion in the terminal portion is formed by plating the same metal or alloy having different average crystal grain sizes, so that it is used for forming the layered portion.
  • One type of plating solution is sufficient, and it is not necessary to prepare a plurality of types of plating apparatuses, and management is easy.
  • the plating layers having different average crystal grain sizes constituting the layered portion have different solubility in the etching solution, and a layer having a smaller crystal grain size dissolves faster. This is because etching proceeds along the crystal grain boundaries, so that a layer having many crystal grain boundaries and a small average crystal grain size is preferentially dissolved.
  • the terminal portion thus obtained is formed with a recess having a step between adjacent layers on its side surface.
  • the bonding with the forming sealing resin is improved without forming an overhanging portion by electroforming beyond the thickness of the resist pattern layer. Can be made. Further, since the electroforming is not performed beyond the thickness of the resist pattern layer, the upper surface of the layered portion can be formed flat and the connectivity with the bonding wire is excellent.
  • FIG. 1A and 1B are schematic cross-sectional views of a terminal portion of a semiconductor element mounting substrate according to an embodiment of the present invention.
  • the substrate for mounting a semiconductor element according to an embodiment of the present invention includes a gold plating layer 13 on the uppermost layer and the lowermost layer on the substrate 1. Between the gold plating layers 13, there is a layered portion 12 in which a nickel plating layer 10 having a large average crystal grain size and a nickel plating layer 11 having a small average crystal grain size are laminated.
  • the layered portion 12 is subjected to an etching process, so that the nickel plating layer 11 having a smaller average crystal grain size is adjacent to each other on the laminated side surface, and the nickel plating layer 10 having a larger average crystal grain size.
  • FIG. 1A shows a semiconductor element mounting substrate according to an example, in which a layered portion 12 of a terminal portion 3 includes four nickel plating layers 10 having a large average crystal grain size and three layers of average crystal grains. It is a figure which shows the state comprised with the nickel plating layer 11 with a small diameter, (b) is an average of two layers as the layered part 12 of the terminal part 3 as a board
  • FIG. 2 is an explanatory view showing in cross section the manufacturing process of the semiconductor device including the process of the manufacturing method of the semiconductor element mounting substrate of the present invention.
  • a resist mask 2 made of a photosensitive dry film is attached to both surfaces of a conductive substrate 1 made of stainless steel.
  • a resist mask 2 on one surface of the substrate 1 is covered with a glass mask (not shown) on which a mask pattern having an exposed region for plating is formed, and subjected to exposure and development processing.
  • a resist pattern layer 2a having a predetermined exposed region including at least the region is formed (FIG. 2A).
  • the exposed region has a semiconductor element mounting portion (pad portion) forming region 2 a 2 in addition to the terminal portion forming region 2 a 1 .
  • the substrate 1 on which the resist pattern layer 2a is formed is subjected to pre-plating treatment, and then gold plating is performed on the exposed regions 2a 1 and 2a 2 .
  • the same kind of metal such as nickel or an alloy is used so that the average particle diameters of adjacent layers are different from each other.
  • the plating process is performed, and for example, as shown in FIGS. 1A and 1B, the layered portion 12 configured in a plurality of layers is formed with a thickness equal to or less than the thickness of the resist pattern layer 2a. To do.
  • gold plating is performed on the formed layered portion 12 (FIG. 2B).
  • the resist masks 2a and 2b formed on both surfaces of the substrate 1 are peeled and removed and immersed in a solution for dissolving nickel for a predetermined time to perform an etching process.
  • a substrate for mounting a semiconductor element in which the substrate 1 includes the terminal portion 3 and the semiconductor element mounting portion (pad portion) 4, is completed.
  • the plating layers 10 and 11 having different average crystal grain sizes constituting the layered portion 12 have different solubility in the etching solution, and a layer having a smaller crystal grain size dissolves earlier.
  • a concave portion having a step between the adjacent layers 10 and 11 is formed (FIG. 2D). In this way, the semiconductor element mounting substrate of the present invention is obtained.
  • the semiconductor element 5 is mounted on a predetermined portion (the semiconductor element mounting portion 4 in the example of FIG. 2) on the semiconductor element mounting substrate obtained by the above manufacturing method, and the electrodes and terminal portions of the semiconductor element 5 are mounted. 3 is connected with a bonding wire 6, and the semiconductor element 5 and the terminal portion 3 side connected with the bonding wire 6 on the substrate are sealed with a resin 7 (FIG. 2 (e)).
  • the conductive substrate 1 is peeled off from the resin sealing body. Thereby, the semiconductor device 5 side in the terminal part 3 and the semiconductor element mounting part 4 is sealed with the resin 7, and the semiconductor device with the back side exposed is obtained (FIG. 2 (f)).
  • the semiconductor mounting substrate according to the present invention is not limited to the configuration including the terminal portion 3 and the semiconductor mounting portion 4 as shown in FIG. 2, but the semiconductor device as shown in FIG. For example, a configuration having only the terminal portion 3 and no semiconductor mounting portion may be employed.
  • the semiconductor element is directly placed at a predetermined position on the conductive substrate with respect to the semiconductor element mounting substrate of the present invention in which only the terminal portion is formed on the conductive substrate (not shown).
  • the semiconductor element and the terminal portion side connected with the bonding wire on the substrate are sealed with resin.
  • the conductive substrate is peeled off from the resin sealing body. As a result, the semiconductor device is obtained in which the terminal 3 and the side of the semiconductor element 5 where the bonding wires 6 are connected are sealed with the resin 7 and the back side is exposed.
  • Example 1 is an example of a semiconductor element mounting substrate having the configuration shown in FIG.
  • a stainless steel (SUS430) with a thickness of 0.2 mm was used as the substrate 1 and after degreasing and acid cleaning treatment, a photosensitive dry film resist with a thickness of 0.050 mm was attached to both surfaces of the substrate 1 by a laminate roll. After that, a glass mask on which a plating mask pattern is formed is placed on the dry film resist on one side of the substrate 1, and further exposed to ultraviolet light for development processing, and a dry film resist is used. A resist mask 2a having a predetermined pattern was formed, and a resist mask 2b covering the entire surface was formed on the opposite surface of the substrate 1 (FIG. 2 (a)).
  • nickel plating layer 11 having a particle size of about 0.3 ⁇ m was formed to a thickness of 5 ⁇ m.
  • a nickel plating layer 10 having an average crystal grain size of about 0.8 ⁇ m and a nickel plating layer 11 having an average crystal grain size of about 0.3 ⁇ m are alternately stacked to form a laminated portion 12.
  • a 3 ⁇ m thick gold plating was applied thereon.
  • four nickel plating layers 10 having an average crystal grain size of about 0.8 ⁇ m, three nickel plating layers 11 having an average crystal grain size of about 0.3 ⁇ m, and the lowermost layer and the uppermost layer are the gold plating layer 13.
  • the terminal part 3 comprised by this was formed (FIG.2 (b)).
  • the resist masks 2a and 2b formed on both surfaces of the substrate 1 are peeled and removed (FIG. 2C), and a solution for dissolving nickel (for example, NH-1860 series: manufactured by MEC Co., Ltd.) is used.
  • the nickel plating layers 10 and 11 on the side face of the terminal portion 3 are subjected to about 0.3 to 2... By immersion treatment at room temperature for 0.5 minutes, 1.5 minutes, 2.5 minutes and 3.5 minutes.
  • a step of 8 ⁇ m was formed (FIG. 2 (d)). This step is formed by utilizing the fact that the etching rate of the nickel plating layer 11 having a small average crystal grain size is faster than that of the nickel plating layer 10 having a large average crystal grain size.
  • the results of the immersion time and the step are shown in FIG.
  • the semiconductor element 5 is mounted on the semiconductor element mounting substrate obtained through the above-described process using a die bonding paste, and the electrode of the semiconductor element 5 and the terminal portion 3 are connected by the bonding wire 6. After that, sealing was performed with the resin 7 (FIG. 2E), and the stainless steel as the substrate 1 was peeled off from the resin sealing body after the sealing resin was cured (FIG. 2F).
  • the substrate for mounting a semiconductor element in which a step of about 0.3 ⁇ m was formed on the nickel plating layer on the side surface of the terminal portion 3 after immersion treatment for 0.5 minutes The part where the plating layer formed on the stainless steel side remains is scattered, and it has been confirmed that the bonding property between the terminal part 3 and the sealing resin 7 is low.
  • the substrate for mounting a semiconductor element in which a step of about 1 ⁇ m or more is formed on the nickel plating layer on the side surface of the portion 3 has no portion where the plating layer remains on the stainless steel side. It was confirmed that the bonding property was maintained well without floating or falling off.
  • Comparative Example 1 is a comparative example for the semiconductor element mounting substrate of Example 1.
  • a resist mask was formed using stainless steel as a substrate, plating pretreatment was performed, and then gold plating was applied to a thickness of 1 ⁇ m, and then a nickel sulfamate bath was used thereon.
  • a nickel plating layer having a current density of 15 A / dm 2 and an average crystal grain size of about 0.8 ⁇ m is formed until a thickness of 5 ⁇ m is reached, and then the current crystal density is 10 A / dm 2 and the average crystal grain size is about A nickel plating layer of 0.5 ⁇ m was formed until the thickness became 5 ⁇ m.
  • a nickel plating layer having an average crystal grain size of about 0.8 ⁇ m and a nickel plating layer having an average crystal grain size of about 0.5 ⁇ m are alternately laminated, and a gold plating is formed thereon with a thickness of 3 ⁇ m.
  • a gold plating is formed thereon with a thickness of 3 ⁇ m.
  • four nickel plating layers with an average crystal grain size of about 0.8 ⁇ m, three nickel plating layers with an average crystal grain size of about 0.5 ⁇ m, and the bottom and top layers are composed of gold plating layers.
  • a terminal portion was formed.
  • the resist mask was peeled and removed, and immersion treatment was performed for 1.5 minutes at room temperature using a solution for dissolving nickel.
  • Example 2 is an example of a semiconductor element mounting substrate having the configuration shown in FIG.
  • a resist mask is formed, plating pretreatment is performed, gold plating is applied to a thickness of 1 ⁇ m, and then nickel plating using a nickel sulfamate bath is performed thereon.
  • a nickel plating layer having an average crystal grain size of about 0.8 ⁇ m is formed at a current density of 15 A / dm 2 and a thickness of 10 ⁇ m is formed thereon, and an average crystal grain size at a current density of 5 A / dm 2 is formed thereon.
  • a nickel plating layer having a thickness of about 0.3 ⁇ m is formed to a thickness of 15 ⁇ m, and a nickel plating layer having a current density of 15 A / dm 2 and an average crystal grain size of about 0.8 ⁇ m is formed to a thickness of 10 ⁇ m. Then, gold plating was applied thereon to a thickness of 3 ⁇ m.
  • Example 2 the resist mask was peeled and removed, and a solution for dissolving nickel was used for immersion treatment at room temperature for 1.5 minutes to mount the semiconductor element, and the electrodes and terminal portions of the semiconductor element Were connected with a bonding wire, resin-sealed, stainless steel was peeled off from the resin-sealed body, and the stainless steel side was observed. As a result, there was no portion where the plating layer remained.
  • the semiconductor mounting substrate and the manufacturing method thereof according to the present invention can reduce the manufacturing cost and have excellent adhesion between the terminal portion and the sealing resin, although the manufacturing method is a simple process. When peeled off from the stationary body, the formed plating layer does not remain, and the highly reliable semiconductor element mounting substrate and the manufacturing method thereof are extremely effective. Expected to be used.

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Abstract

　端子部が封止樹脂との結合力やボンディングワイヤとの接続性に優れ、製造コストを低減でき、半導体装置の小型化や薄型化に十分対応することができる半導体素子搭載用基板及びその製造方法を提供する。　同じ種類の金属又は合金を用いて隣り合う層１０，１１同士の平均結晶粒径が異なる複数の層状に構成された層状部１２を有し、且つ、層状部１２の側面にはエッチング加工を施すことによって隣り合う層１０，１１同士で段差のついた凹部が形成されている、端子部３を少なくとも有する。

Description

半導体素子搭載用基板及びその製造方法
　本発明は、めっきにより端子部が形成される半導体素子搭載用基板及びその製造方法に関する。
　従来、導電性基板の一面側に、所定のレジストパターン層を形成し、そのレジストパターン層から導電性基板が露出した面にレジストパターン層の厚みを越えて導電性金属を電着することで、上端部周縁に張り出し部を有する半導体素子搭載用の金属層と電極層とを独立して並設形成した後、レジストパターン層を除去し、金属層上に半導体素子を搭載し、半導体素子上の電極と電極層とをボンディングワイヤにより電気的に接続し、半導体素子搭載部分を樹脂で封止した後、基板を除去して金属層と電極層の各裏面が露出した樹脂封止体を得るようにした半導体装置の製造方法が知られている（例えば、特許文献１参照）。
　特許文献１に記載の半導体装置の製造方法によれば、張り出し部が封止樹脂にくい込んだ状態で位置するため、アンカー効果により金属層及び電極層と封止樹脂との結合力が向上し、後工程で基板を引き離す際、金属層や電極層の必要部品が、基板側に残ることなく樹脂封止体側に埋没した状態で転写され、金属層や電極層のズレや欠落等を効果的に防止することができる。
　また、金属層及び電極層の上端部周縁全周に亘って形成される特有の張り出し形状により、半導体装置裏面側からの金属層及び電極層の各層と封止樹脂との境界部分を通して侵入する水分を阻止し、耐湿性に優れたものとすることができる。
　しかしながら、特許文献１に記載の製造方法では、レジストパターン層を越えて電着を行うため、レジストパターン層の厚さを越えた部分の電着はレジストパターン層の制約が何ら無い状態となってしまい、電流密度の分布等の影響を受け易く、張り出し部の長さを一定に保つことが困難であり、金属層や電極層と封止樹脂との結合力にバラツキが生ずるという問題があった。また、金属層や電極層の上面も何ら制約のない電着となるため、上面が平面にならず、半球面状に形成され、ボンディングワイヤの接続不良が発生し易いという問題があった。
　また、従来、特許文献１に記載の半導体装置の製造方法とは別に、導電性基板の一面側に所定のバターニングを施したレジストパターン層を形成し、レジストパターン層から基板が露出した面に、レジストパターン層の厚みを越えない範囲で、下層、中間層及び上層を含む３層以上からなる導電性金属をめっきにより形成した後、レジストパターン層を除去し、エッチング処理を施して前記中間層に前記下層及び上層よりもその幅を小さくする加工を行うことで、その断面形状において中間層が凹状に形成された半導体素子搭載用の金属層（パッド部）と電極層（端子部）とを独立して並設形成した後、金属層上に半導体素子を搭載し、半導体素子上の電極と電極層とをボンディングワイヤにより電気的に接続し、半導体素子搭載部分を樹脂で封止した後、基板を除去して金属層と電極層の各裏面が露出した樹脂封止体を得るようにした半導体素子搭載用基板の製造方法が知られている（例えば、特許文献２参照）。
　特許文献２に記載の半導体素子搭載用基板の製造方法によれば、金属層及び電極層の中間層が上下層よりも小さく形成されていることで、封止樹脂と金属層及び電極層とが優れた密着性を示し、また、基板上に最初に形成される下層を金めっきで形成することで基板との密着性が向上し、封止樹脂が基板と下層との間に回り込むことを防止できる。
　また、レジストパターン層の厚みを越えて電鋳しないので、金属層や電極層の横方向の大きさが均一で、封止樹脂との結合力が安定して高く、電極層の上面が平坦でボンディング性に優れ、かつ半導体装置の小型化や薄型化に十分対応することができる。
特開２００２－９１９６号公報 特開２００９－１３５４１７号公報
　しかしながら、特許文献２に記載の構成では、複数種類の導電性金属を積層めっきする必要があるため、その工程が煩雑となり、コスト低減に課題が残されていた。
　本発明は、上記従来技術の問題点に鑑みてなされたものであり、端子部が封止樹脂との結合力やボンディングワイヤとの接続性に優れ、製造コストを低減でき、半導体装置の小型化や薄型化に十分対応することができる半導体素子搭載用基板及びその製造方法を提供することを目的とする。
　本発明による半導体素子搭載用基板は、同じ種類の金属又は合金を用いて隣り合う層同士の平均結晶粒径が異なる複数の層状に構成された層状部を有し、且つ、前記層状部の側面には前記隣り合う層同士で段差のついた凹部が形成されている、端子部を少なくとも有することを特徴としている。また、本発明の半導体素子搭載用基板においては、前記層状部は、３層以上で構成されているのが好ましい。また、本発明の半導体素子搭載用基板においては、前記層状部における前記隣り合う層同士での前記同じ種類の金属又は合金の平均結晶粒径の差が０．５μｍ以上であるのが好ましい。
　また、本発明による半導体素子搭載用基板の製造方法は、端子部形成用の領域を少なくとも含む所定の露出領域を有するレジストパターン層が形成された導電性基板に対し、めっき処理を施すことにより、前記導電性基板の露出領域に、同じ種類の金属又は合金を用いた隣り合う層同士の平均結晶粒径が異なる複数の層状に構成された層状部を、レジストパターン層の厚み以下の厚みをもたせて形成する層状部形成工程と、前記層状部形成工程を介して前記層状部が形成された導電性基板に対し、エッチング加工を施すことにより、前記層状部の側面に前記隣り合う層同士で段差のついた凹部を形成する段差形成工程を有することを特徴としている。
　また、本発明の半導体素子搭載用基板の製造方法においては、前記層状部形成工程において、電流密度を変更してめっき処理を施すことで、前記層状部における隣り合う層ごとに前記同じ種類の金属又は合金の平均結晶粒径を変化させるのが好ましい。
　本発明によれば、製造コストが低減でき、その製造方法が簡略な工程であるにも拘らず、端子部と封止樹脂との結合性に優れ、基板を樹脂封止体から引き剥がした際に、形成しためっき層が残ることがなく、また、端子部とボンディングワイヤとの接続性に優れ、信頼性の高い半導体素子搭載用基板及びその製造方法を得ることができる。
図１は本発明の一実施形態にかかる半導体素子搭載用基板における端子部の概略構成を示す断面図で、(a)はその一例にかかる半導体素子搭載用基板の端子部を示す断面図、(b)は他の例にかかる半導体素子搭載用基板の端子部を示す断面図である。 図２は本発明の一実施形態にかかる半導体素子搭載用基板の製造方法を含む、半導体装置の製造工程を断面で示す説明図で、(a)は導電性基板上にレジストマスクを形成した状態を示す図、(b)は(a)のレジストマスクが形成された基板の露出領域に層状部を含むめっき層を形成した状態を示す図、(c)はめっき層が形成された基板からレジストマスクを除去し、エッチング処理を施して本発明の一実施形態にかかる半導体素子搭載用基板が形成された状態を示す図、(d)は(c)の半導体素子搭載用基板に備わる層状部の側面に形成される段差を示す拡大図、(e)は(c)の半導体素子搭載用基板に半導体素子を搭載し、半導体素子の電極と端子部とをボンディングワイヤで接続後、これらを樹脂で封止した状態を示す図、(f)は(e)に示す封止樹脂体から導電性基板を引き剥がすことにより完成した半導体装置を示す図である。 図３は本発明の変形例として端子部のみ有し半導体搭載部を有しない半導体素子搭載用基板を用いて製造される、半導体装置の概略構成を示す断面図である。 図４は本発明の実施例１にかかる半導体素子搭載用基板の製造に際し、同じ種類の金属又は合金を用いて、隣り合う層同士の平均結晶粒径が異なる、複数の層状に構成された層状部が形成された導電性基板に対し、エッチング加工を施したときの、エッチング液への浸漬時間と隣り合う層同士の段差との関係を示すグラフである。
　実施例の説明に先立ち、本発明の作用効果について説明する。
　本発明の半導体素子搭載用基板及びその製造方法によれば、端子部における層状部を、平均結晶粒径が異なる同じ金属又は合金をめっきすることにより形成するので、層状部の形成のために使用するめっき液は１種類で済み、めっき装置も複数種類準備する必要がなく管理も容易となる。
　この層状部を構成する平均結晶粒径が異なるめっき層は、エッチング液に対する溶解性が異なり、結晶粒径が小さい層の方が早く溶解する。これは、エッチングが結晶粒界に沿って進むため、結晶粒界が多い平均結晶粒径の小さい層が優先的に溶解するためである。
　このようにして得られた端子部は、その側面に、隣り合う層同士で段差のついた凹部が形成される。このため、本発明によれば、特許文献１の製造方法のように、レジストパターン層の厚みを越えて電鋳することによって張り出し部を形成することなく、形成封止樹脂との結合性を向上させることができる。また、レジストパターン層の厚みを越えて電鋳しないので、層状部の上面を平坦に形成でき、ボンディングワイヤとの接続性が優れたものとなる。
　図１(a)，(b)は、本発明の一実施形態にかかる半導体素子搭載用基板における端子部の概略断面図である。本発明の一実施形態にかかる半導体素子搭載用基板は、基板１上における、最上層と最下層が金めっき層１３で構成されている。金めっき層１３の間には、平均結晶粒径が大きいニッケルめっき層１０と平均結晶粒径が小さいニッケルめっき層１１が積層された層状部１２を有している。層状部１２は、エッチング加工が施されることにより、積層された側面に、隣り合う層同士で、平均結晶粒径の小さい方のニッケルめっき層１１が、平均結晶粒径が大きいニッケルめっき層１０に対して、側面が凹となった状態の段差が形成されている。
　そして、図１(a)は、その一例にかかる半導体素子搭載用基板として、端子部３の層状部１２が、４層の平均結晶粒径が大きいニッケルめっき層１０と、３層の平均結晶粒径が小さいニッケルめっき層１１とで構成されている状態を示す図であり、(b)は、他の例にかかる半導体素子搭載用基板として、端子部３の層状部１２が、２層の平均結晶粒径が大きいニッケルめっき層１１と、１層の平均結品粒径が小さいニッケルめっき層１０とで構成されている状態を示す図である。
　次に、本発明の半導体素子搭載用基板の製造方法の一実施形態を半導体装置の製造工程の中で説明する。図２は本発明の半導体素子搭載用基板の製造方法の工程を含む、半導体装置の製造工程を断面で示す説明図である。
　本発明の半導体素子搭載用基板の製造に際しては、前工程として、例えば、ステンレス鋼からなる導電性基板１の両面に感光性ドライフィルムからなるレジストマスク２を貼り付ける。その後、基板１の一方の面のレジスト２の上に、めっき用の露出領域を有するマスクパターンが形成されたガラスマスク（図示省略）を被せ、露光、現像処理を行うことで、端子部形成用の領域を少なくとも含む所定の露出領域を有するレジストパターン層２ａを形成する（図２(a)）。なお、図２の例では、露出領域は、端子部形成用の領域２ａ1の他に、半導体素子搭載部（パッド部）形成用の領域２ａ2を有している。
　次いで、レジストパターン層２ａが形成された基板１に対して、めっき前処理を施した後、露出領域２ａ1，２ａ2の上に金めっきを施す。
　次いで、金めっきが施された露出領域２ａ1，２ａ2の上に、例えば、ニッケルなど同じ種類の金属又は合金を用いて、隣り合う層同士の平均粒子径が異なるようにして、積層されるように、めっき処理を施し、例えば、図１(a)，(b)に示したような、複数の層状に構成された層状部１２を、レジストパターン層２ａの厚み以下の厚みをもたせて形成する。
　次いで、形成した層状部１２の上に金めっきを施す（図２(b)）。
　次いで、基板１の両面に形成されていたレジストマスク２ａ，２ｂを剥離除去し、ニッケルを溶解させる溶液に所定時間浸漬することによってエッチング加工処理を施す。これにより、図２(c)に示すように、基板１に端子部３と半導体素子搭載部（パッド部）４を備えた、半導体素子搭載用基板が出来上がる。このとき、上述したように、層状部１２を構成する平均結晶粒径が異なるめっき層１０，１１は、エッチング液に対する溶解性が異なり、結晶粒径が小さい層の方が早く溶解するため、層状部１２の側面に、隣り合う層１０，１１同士で段差のついた凹部が形成される（図２(d)）。
　このようにして、本発明の半導体素子搭載用基板が得られる。
　半導体装置の製造に際しては、上記製造方法で得た半導体素子搭載用基板上の所定部位（図２の例では半導体素子搭載部４）に半導体素子５を搭載し、半導体素子５の電極と端子部３とをボンディングワイヤ６で接続した後、基板におけるボンディングワイヤ６で接続された半導体素子５及び端子部３側を樹脂７で封止する（図２(e)）。
　次いで、封止した樹脂７が硬化した後、樹脂封止体から導電性基板１を引き剥がす。これにより、端子部３及び半導体素子搭載部４における半導体素子５側が樹脂７で封止され、その裏側が露出した半導体装置が得られる（図２(f)）。
　なお、本発明の半導体搭載用基板は、図２に示したような、端子部３と半導体搭載部４とを備えた構成に限定されるものではなく、図３に示すような半導体装置の製造に適用するように、端子部３のみ有し半導体搭載部を有しない構成であってもよい。
　図３に示す半導体装置の製造に際しては、上述の図示しない導電性基板の上に端子部のみが形成された本発明の半導体素子搭載用基板に対し、半導体素子を導電性基板の所定位置に直接搭載し、半導体素子の電極と端子部とをボンディングワイヤで接続した後、基板におけるボンディングワイヤで接続された半導体素子及び端子部側を樹脂で封止する。
　次いで、封止した樹脂が硬化した後、樹脂封止体から導電性基板を引き剥がす。これにより、端子部３及び半導体素子５のボンディングワイヤ６を接続する側が樹脂７で封止され、その裏側が露出した状態の半導体装置が得られる。
　実施例１は図１(a)に示した構成を備えた半導体素子搭載用基板の実施例である。
　板厚が０．２ｍｍのステンレス鋼（ＳＵＳ４３０）を基板１として、脱脂・酸洗浄処理を行った後、厚さ０．０５０ｍｍの感光性ドライフィルムレジストをラミネートロールによって基板１の両面に貼り付けた後、めっきマスクパターンが形成されたガラスマスクを基板１の一方の面のドライフィルムレジストの上から被せ、さらにその上から紫外光を照射することで露光して現像処理を行い、ドライフィルムレジストによる所定のパターンが形成されたレジストマスク２ａを形成し、基板１の反対側の面には全面を覆うレジストマスク２ｂを形成した（図２(a)）。
　次いで、基板１におけるレジストマスク２ａから露出した領域２ａ1，２ａ2に対してめっき前処理を施した後、金めっきを厚さ１μｍとなるように施し、次いで、その上にスルファミン酸ニッケル浴を用いてニッケルめっきを、電流密度１５Ａ／ｄｍ2で、平均結晶粒径が約０．８μｍのニッケルめっき層１０を厚さ５μｍとなるように形成し、次いで電流密度５Ａ／ｄｍ2で、平均結晶粒径が約０．３μｍのニッケルめっき層１１を厚さ５μｍとなるように形成した。更にその上に同様にして、平均結晶粒径が約０．８μｍのニッケルめっき層１０と平均結晶粒径が約０．３μｍのニッケルめっき層１１を交互に積層して積層部１２を形成し、その上に３μｍ厚の金めっきを施した。これにより、平均結晶粒径が約０．８μｍのニッケルめっき層１０が４層、平均結晶粒径が約０．３μｍのニッケルめっき層１１が３層で、最下層と最上層が金めっき層１３で構成される端子部３を形成した（図２(b)）。
　次に、基板１の両面に形成されていたレジストマスク２ａ，２ｂを剥離除去し（図２(c)）、ニッケルを溶解させる溶液（例えば、ＮＨ－１８６０シリーズ：メック株式会社製）を用いて、室温で０．５分、１．５分、２．５分、３．５分の間浸債処理することにより、端子部３側面のニッケルめっき層１０，１１に約０．３～２．８μｍの段差を形成した（図２(d)）。この段差は、平均結晶粒径の小さいニッケルめっき層１１のエッチング速度が平均結晶粒径の大きいニッケルめっき層１０より速くなることを利用して形成される。その浸漬時間と段差の結果を図４に示す。
　接合性を判断するために、上記工程を介して得た半導体素子搭載用基板にダイボンド用ペーストを用いて半導体素子５を搭載し、半導体素子５の電極と端子部３とをボンディングワイヤ６で接続した後、樹脂７で封止を行い（図２(e)）、封止樹脂硬化後に基板１であるステンレス鋼を樹脂封止体から引き剥がした（図２(f)）。
　引き剥がされたステンレス鋼側を詳細に観察した結果、０．５分間の浸漬処理をして端子部３側面のニッケルめっき層に約０．３μｍの段差が形成された半導体素子搭載用基板は、ステンレス鋼側に形成しためっき層が残っている部分が散見され、端子部３と封止樹脂７との接合性が低いことが確認されたが、１．５分以上の浸漬処理をして端子部３側面のニッケルめっき層に約１μｍ以上の段差が形成された半導体素子搭載用基板は、ステンレス鋼側にめっき層が残っている部分は皆無であり、また、封止樹脂７から端子部３が浮いたり脱落することも無く、その接合性が良好に保持されていることが確認できた。
比較例１
　比較例１は実施例１の半導体素子搭載用基板に対する比較例である。
　実施例１と同様にステンレス鋼を基板として、レジストマスクを形成し、めっき前処理を行い、次に、金めっきを厚さ１μｍとなるまで施し、次いで、その上にスルファミン酸ニッケル浴を用いたニッケルめっきを、電流密度１５Ａ／ｄｍ2で、平均結晶粒径が約０．８μｍのニッケルめっき層を厚さ５μｍとなるまで形成し、次いで電流密度１０Ａ／ｄｍ2で、平均結晶粒径が約０．５μｍのニッケルめっき層を厚さ５μｍとなるまで形成した。更にその上に同様にして平均結晶粒径が約０．８μｍのニッケルめっき層と平均結晶粒径が約０．５μｍのニッケルめっき層を交互に積層し、その上に金めっきを厚さ３μｍとなるように施した。これにより、平均結晶粒径が約０．８μｍのニッケルめっき層が４層、平均結晶粒径が約０．５μｍのニッケルめっき層が３層で、最下層と最上層が金めっき層で構成される端子部を形成した。
　次に、実施例１と同様に、レジストマスクを剥離除去し、ニッケルを溶解させる溶液を用いて、室温で１．５分間浸漬処理を行ったが、端子部のニッケルめっき層側面に段差は０．３μｍ程度しか得られなかった。そのため実施例１の結果より、比較例１は生産性が悪く、且つ０．３μｍ程度の段差では、接合性が低いと判断した。
　実施例２は図１(b)に示した構成を備えた半導体素子搭載用基板の実施例である。
　実施例１と同様にステンレス綱を基板として、レジストマスクを形成し、めっき前処理を行ない、金めっきを１μｍ厚となるように施し、次いで、その上にスルファミン酸ニッケル浴を用いたニッケルめっきを、電流密度１５Ａ／ｄｍ2で施して、平均結晶粒径が約０．８μｍのニッケルめっき層を厚さ１０μｍとなるように形成し、その上に電流密度５Ａ／ｄｍ2で、平均結晶粒径が約０．３μｍのニッケルめっき層を厚さ１５μｍとなるように形成し、更に電流密度１５Ａ／ｄｍ2で、平均結晶粒径が約０．８μｍのニッケルめっき層を厚さ１０μｍとなるように形成し、その上に金めっきを厚さ３μｍとなるように施した。
　次に、実施例１と同様に、レジストマスクを剥離除去し、ニッケルを溶解させる溶液を用いて、室温で１．５分間浸漬処理を行い、半導体素子を搭載し、半導体素子の電極と端子部とをボンディングワイヤで接続し、樹脂封止を行い、ステンレス鋼を樹脂封止体から引き剥がし、ステンレス鋼側を観察した結果、めっき層が残っている部分は皆無であった。
　本発明の半導体搭載用基板及びその製造方法は、製造コストが低減でき、その製造方法が簡略な工程であるにも拘らず、端子部と封止樹脂との密着性に優れ、基板を樹脂封止体から引き剥がした際に、形成しためっき層が残ることがなく、信頼性の高い半導体素子搭載用基板及びその製造方法として極めて優れた効果を奏するものであることから、当該産業分野において幅広く用いられることが期待される。
　１　　　　　基板
　２　　　　　レジストマスク
　２ａ　　　　レジストパターン層が形成されたレジストマスク
　２ａ1　　　 端子部形成用の露出領域
　２ａ2　　　 半導体素子搭載部形成用の露出領域
　２ｂ　　　　基板全面を覆うレジストマスク
　３　　　　　端子部
　４　　　　　半導体素子搭載部
　５　　　　　半導体素子
　６　　　　　ワイヤ
　７　　　　　樹脂
１０　　　　　平均結晶粒径の大きい層
１１　　　　　平均結晶粒径の小さい層
１２　　　　　層状部
１３　　　　　金めっき層

Claims (5)

  1. 　同じ種類の金属又は合金を用いて隣り合う層同士の平均結晶粒径が異なる複数の層状に構成された層状部を有し、且つ、前記層状部の側面には前記隣り合う層同士で段差のついた凹部が形成されている、端子部を少なくとも有することを特徴とする半導体素子搭載用基板。
  2. 　前記層状部は、３層以上の層状に構成されていることを特徴とする請求項１に記載の半導体素子搭載用基板。
  3. 　前記層状部における前記隣り合う層同士での前記同じ種類の金属又は合金の平均結晶粒径の差が０．５μｍ以上であることを特徴とする請求項１に記載の半導体素子搭載用基板。
  4. 　端子部形成用の領域を少なくとも含む所定の露出領域を有するレジストパターン層が形成された導電性基板に対し、めっき処理を施すことにより、前記導電性基板の露出領域に、同じ種類の金属又は合金を用いた隣り合う層同士の平均結晶粒径が異なる複数の層状に構成された層状部を、レジストパターン層の厚み以下の厚みをもたせて形成する層状部形成工程と、前記層状部形成工程を介して前記層状部が形成された導電性基板に対し、エッチング加工を施すことにより、前記層状部の側面に前記隣り合う層同士で段差のついた凹部を形成する段差形成工程を有することを特徴とする半導体素子搭載用基板の製造方法。
  5. 　前記層状部形成工程において、電流密度を変更してめっき処理を施すことで、前記層状部における隣り合う層ごとに前記同じ種類の金属又は合金の平均結晶粒径を変化させることを特徴とする請求項４に記載の半導体素子搭載用基板の製造方法。
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