201014476 六、發明說明： 【發明所屬之技術領域】 本發明，係有關於多層層積電路基板’特別是有關於 難以產生金屬電路之斷線的多層層積電路基板。 【先前技術】 在我們身邊所存在的製品（例如電性製品、電子製品 φ 、半導體製品、天線電路基板、1C卡、機器人等）中’均 係以不會佔據過多空間的小型製品爲受到歡迎者’且係期 待有更進而作了小型化之製品。爲了對此種製品之需要有 所對應，在嘗試將製品之外形作小型化、以及嘗試將製品 之內部作小型化的兩方面上，將製品小型化的技術開發均 係曰益進行。然而’在嘗試將製品之外形小型化的方向所 致之製品的小型化上，可以說已經到達了極限’而成爲期 待能夠更進一步地將製品的內部小型化。 Φ 在此種狀況下，作爲將製品之內部小型化的方向’於 近年，在將被使用於製品中之電路基板設爲輕薄短小之電 路構造的方法上，係受到囑目。先前技術中之電路基板’ 係檢討有：在平面上形成1層或是2層的電路’並經由將 該電路本身細微化一事，來將電路基板小型化’但是’若 是僅藉由被形成在平面上之電路的細微化，則小型化仍係 有所限度，因此，係成爲對於將電路基板多層化並立體性 地形成電路的多層層積電路基板而有所檢討。 此種多層層積電路基板，一般而言，係藉由增層（ -5- 201014476 build up)法來製作。所謂增層法，係藉由對於被形成在 絕緣性之樹脂薄膜上的導電層進行蝕刻，而將其作部分性 的除去，並形成金屬電路，接著，在該金屬電路上塗布接 著劑，並進而貼合被形成有導電層之樹脂薄膜。而後，在 所貼合之樹脂薄膜的導通部處形成導通貫孔，並在該導通 貫孔之內部塡充電鍍或是糊等。接著，藉由對於所貼合之 樹脂薄膜的導電層進行蝕刻，而將其作部分性的除去，並 形成金屬電路。之後，反覆進行此些之工程，而將金屬電 路多層化。然而，藉由此增層法所形成之多層層積電路基 板，係有著：若是對其本身而施加有熱，則在金屬電路處 會產生斷線的問題。 在日本特開2005-2439 1 1號公報（專利文獻1)、日 本特開2007-26648 1號公報（專利文獻2)、日本特開 2008-060582號公報（專利文獻 3 )、日本特開 2007-33563 1號公報（專利文獻4)、日本特開2005-2230 1 0 ( 專利文獻5 )、以及日本特開2008-091 439號公報（專利 文獻6)中，係爲了解決此些之課題，而進行有各種之嘗 試，但是，不論是任一之多層層積電路基板，均並非爲能 夠將上述之問題充分地作解決者。以下，對於在專利文獻 1〜6中所展示之多層層積電路基板的槪略作說明。 專利文獻1之多層層積電路基板，係藉由在2層之樹 脂薄膜的金屬電路之連接中，使用並不包含鉛之低熔點的 銲錫，來提升樹脂薄膜彼此之接合強度，並防止金屬電路 之斷線。然而，此多層層積電路基板，當被施加有熱時， -6- 201014476 低熔點銲錫會再度熔解，而金屬電路會斷線。 在專利文獻2中，係記載有：藉由在以從表面側之金 屬電路起而一直貫通至背面側之金屬電路處的方式而被開 孔之導通貫孔中塡充銲錫，而將可撓性基板與補強基板間 之接合強度提升並作接合，藉由此，來防止金屬電路之斷 線，但是，與專利文獻1相同的，當被施加有熱時，係易 於產生金屬電路之斷線》 φ 在專利文獻3中，係記載有藉由銲錫突塊來將樹脂薄 膜彼此作接合之多層層積電路基板。然而，由於將銲錫突 塊之口徑縮小一事係爲困難，因此，係有著無法對應於多 層層積電路基板之小型化的問題。 在專利文獻4中，係揭示有在多層層積電路基板之導 通貫孔中塡充導電性樹脂所致的多層層積電路基板，但是 ，在由於長期間導通所發生之熱而在金屬電路中產生斷線 —事上，係仍存在有擔憂。 φ 在專利文獻5中，係藉由在樹脂薄膜之層積時來在導 通貫孔中塡充導電性糊，而提升表、背面之樹脂薄膜彼此 的接著性，但次，導電性糊與樹脂薄膜間的密著度，係並 不能說是充分。 進而，在專利文獻6中，係記載有一種：經由在樹脂 薄膜彼此之貼合中使用接著劑，來對於作了層積的樹脂薄 膜彼此之位置偏差作防止的多層層積電路基板，但是，僅 對於位置偏差作防止，係並不能說是可以充分地防止金屬 電路之斷線。 201014476 〔先前技術文獻〕 〔專利文獻〕 〔專利文獻1〕曰本特開2005-243911號公報 〔專利文獻2〕日本特開2007-266481號公報 〔專利文獻3〕日本特開2008-060582號公報 〔專利文獻4〕曰本特開2007-33 563 1號公報 〔專利文獻5〕日本特開2005-223010號公報 〔專利文獻6〕日本特開2008-091439號公報 【發明內容】 〔發明所欲解決之課題〕 如以上所述一般，專利文獻1〜6，係均爲藉由對於樹 脂薄膜彼此間之接著手段或是接著材料作改良，來提供一 種難以產生金屬電路之斷線的多層層積電路基板者。 然而，在上述任一之多層層積電路基板中，由於導通 部均係爲藉由1個的導通貫孔所形成者，因此，係具備有 共通的問題點，亦即是：若是對其本身施加熱，則由於樹 脂薄膜之熱膨脹係數與導通貫孔內之金屬電路的熱膨脹係 數係爲相異，因此，藉由此些之熱膨脹的差，在導通貫孔 內之金屬電路處係被施加有壓縮或是拉張應力，而使得導 通貫孔內之金屬電路斷線。 又，作爲另外的問題點，例如當對於多層層積電路基 板而施加有熱的情況時，在被包含於多層層積電路基板中 的複數之樹脂薄膜處，因應於與熱源間所相距之距離，在 -8- 201014476 各樹脂薄膜間會產生膨脹差，而多層層積電路基板係變形 ，在被形成於樹脂薄膜上之導通貫孔內的金屬電路處，係 被施加有應力，而亦有著使金屬電路斷線的問題。本發明 ，係有鑑於上述一般之現狀而進行者，其目的，係在於提 供一種難以產生金屬電路之斷線的多層層積電路基板。 〔用以解決課題之手段〕 本發明之多層層積電路基板，係爲包含有將樹脂薄膜 與電路層交互作層積的層積構造之多層層積電路基板，其 特徵爲：上述樹脂薄膜，係具備有1個以上的多孔導通部 ，上述多孔導通部，係佔據直徑10/zm以上3000#m以 下之區域，且具備有2個以上的導通貫孔，該導通貫孔， 係具備有5ΜΠ1以上300//m以下之內徑。 又，若是將上述樹脂薄膜之厚度設爲T，並將上述導 通貫孔之內徑設爲d，則係以成爲0<d/TS60爲較理想 〇 又，上述之樹脂薄膜，係以對於長尺狀之物作加工來 使用爲理想。 又，本發明，係爲一種使用有多層層積電路基板之橇 件或是製品。 又，較理想，上述製品，係爲電氣製品、電子製品、 半導體製品、天線電路基板、1C卡、太陽電池、汽車或者 是機器人中之任一者。 201014476 〔發明之效果〕 本發明之多層層積電路基板，係藉由具備有上述之各 構成，而具備有難以產生金屬電路之斷線的效果。 【實施方式】 〈多層層積電路基板〉 以下，參考圖1，針對本發明之多層層積電路基板作 說明。圖1，係爲對於本發明之多層層積電路基板的其中 一例作展示之模式性剖面圖。另外，在本發明之圖面中， 相同之參考符號，係爲代表相同部分或是相當部分者。 本發明之多層層積電路基板1，係如圖1中所示一般 ，包含有將樹脂薄膜100與電路層2 00交互作了層積的層 積構造。另外，圖1雖係展示將樹脂薄膜100作了 3層層 積的構造，但是，在本發明中之層積構造的最小層積數， 係爲將樹脂薄膜1 〇〇作了 2層層積的構造。於此情況，電 路層200之層積數，係可設爲2層或者是3層。另一方面 ，在本發明中之層積構造的最多層積數，係並未被特別限 定，而可因應於用途來作層積，但是，通常，一般而言係 爲將樹脂薄膜100層積了 2〜30層左右者。 於此，本發明之多層層積電路基板1的樹脂薄膜100 ，其特徵爲，係具備有1個以上的多孔導通部110，且在 該多孔導通部110處，係設置有將樹脂薄膜之表背面作貫 通之2個以上的導通貫孔12〇。如此這般，藉由設置2個 以上的將樹脂薄膜100之表背面作貫通之導通貫孔120, -10- 201014476 而能夠成爲使金屬電路之斷線難以產生。以下，針對在本 發明之多層層積電路基板中所包含的各構成部作說明。 〈樹脂薄膜〉 在本發明之多層層積電路基板中，係包含有2層以上 之樹脂薄膜。而，該些之樹脂薄膜，係由絕緣性之材料所 成，並能夠使用在此種用途中所被作利用之先前技術週知 φ 的樹脂薄膜中之任一者。作爲此種樹脂薄膜，例如，係可 使用聚醯亞胺（PI )系、丙烯酸系、液晶聚合物（LCP ) 、聚對苯二甲酸乙二酯（PET)、聚萘二甲酸乙二酯（ PEN)等之樹脂薄膜。 該種樹脂薄膜1〇〇，係以對於長尺狀之物作加工來使 用爲理想。作爲該種長尺狀之樹脂薄膜，例如，係以具備 有1〜1000 0m左右之長度者爲理想，又以1〇〇〜3000m左 右者爲更理想。藉由使用長尺狀者，係能夠進行連續加工 φ ，而能夠將生產效率提升。若是不滿lm，則作爲捲繞爲 筒狀者來使用一事係變得困難，而使加工效率降低，故並 不理想，又，若是超過1 000〇m，則在後述之基底層的形 成中，會有對於連續加工造成妨礙之虞，故並不理想。 另外，所謂的「樹脂薄膜爲長尺狀者」，係指具備有 如同上述一般之長度，而適合於作爲捲繞成筒狀之形狀來 使用者，但是，就算是並不滿足上述一般之長度者，若是 藉由將複數枚之樹脂薄膜作貼合來作爲長尺狀者而處理者 ，則亦包含在本發明之範圍內。 -11 - 201014476 又’樹脂薄膜100之厚度，係以3/zm以上200/zm 以下爲理想。若是樹脂薄膜1〇〇之厚度較更薄，貝lj 由於作業性會變得過差，故並不理想，又，若是變得較 200以m更厚’則由於導通貫孔12〇係成爲難以加工，故 並不理想。 〈電路層〉 在被形成於本發明之樹脂薄膜100上的電路層200處 ，係包含有金屬電路50。又，電路層200之金屬電路50 以外的部分，係亦可藉由絕緣性之接著性樹脂70來作塡 充，並可經由此接著性樹脂70來將樹脂薄膜1〇〇彼此相 互作貼合。如此這般，本發明之電路層200，係可僅經由 金屬電路50來構成，亦可藉由金屬電路50與接著性樹脂 70來構成。 〈金屬電路〉 金屬電路50，係包含有電鎪層140，又，係亦可進而 在此電鍍層140與樹脂薄膜100之間’而包含有基底層 130。另外，在本發明中，在便利上，係亦有將被形成於 導通貫孔120內之基底層130以及電鍍層140稱作金屬電 路50的情況。 於此，基底層130，係爲具備有將電鏟層140與樹脂 薄膜1 00間之密著性提升的功能，而能夠形成爲1層’亦 能夠形成爲2層以上。當將基底層130形成爲2層以上的 -12- 201014476 情況時，係以包含有氧化防止層與基底金屬層爲理想。此 種基底層，係可使用任意之方法來形成，但是，例如係可 藉由無電解電鍍、蒸鍍、濺鍍等來形成之。特別是從能夠 正確地對膜厚作控制之觀點來看，係以藉由濺鍍來形成爲 理想。 此氧化防止層，係以藉由從由Ni、Cr、Ti、Co以及 Si所成之群中所選擇的至少1種之金屬、或者是將該些金 Φ 屬至少包含有1種的合金所構成爲理想，其層厚，係以設 爲2〜20nm爲理想。 又，基底金屬層，係以被形成在氧化防止層上爲理想 ，並以藉由從由〇\1、人\1、人巨、811、：!^、81以及乙11所成 之群中所選擇的至少一種之金屬、或者是將該些金屬至少 包含有1種的合金所構成爲理想。又，基底金屬層之層厚 ，係以設爲50〜500nm左右爲理想。 又，上述電鍍層140,係爲藉由電鍍所形成之層，並 以藉由從由Cu、Au、Ag、Sn、Ni、Bi以及Zn所成之群 中所選擇的至少一種之金屬、或者是將該些金屬至少包含 有1種的合金所構成爲理想，又以藉由Cu或是包含有Cu 之合金來構成爲更理想。另外，當形成前述之基底金屬層 的情況時，基底金屬層與電鍍層140，係以使用相同之材 料爲理想。 〈接著性樹脂〉 接著性樹脂70，只要是能夠將在多層層積電路基板中 -13- 201014476 所被使用的樹脂薄膜1 〇〇彼此相互作貼合者，則係可使用 任意之物，例如，係可使用環氧系之樹脂、丙烯酸系之樹 脂以及聚醯亞胺系之樹脂等。 〈多孔導通部〉 構成本發明之多層層積電路基板1的各樹脂薄膜100 ，係具備有1個以上的多孔導通部110，且在此多孔導通 部處，係被設置有2個以上的導通貫孔120。於此，所謂 多孔導通部，在金屬電路之構成上，係指被形成於希望將 該當樹脂薄膜之表背兩面的金屬電路作導通之部位處者， 並爲藉由形成2個以上之將樹脂薄膜之表背面作貫通的導 通貫孔，來對於表背面之導通作保障者。 而，該當多孔導通部，係指包含有在所期望之部位處 而近接關連地被形成之複數的導通貫孔之全部、且其之剖 面積係成爲最小的圓柱狀區域，該當剖面積，在樹脂薄膜 上，係以佔據直徑l〇ym以上3000 m以下之區域爲理 想。亦即是，例如，如圖2中所示一般，當近接關連之導 通貫孔120係存在有3個的情況時，則多孔導通部11〇, 係指包含有此3個的導通貫孔之全部，且圓柱狀區域之剖 面的面積成爲最小之區域。 此多孔導通部之直徑，如同上述一般，係以以 上3000 "m以下爲理想。若是多孔導通部之直徑未滿10 //m，則係會有無法對於被形成在樹脂薄膜之表背面的金 屬電路之導通作充分保障的情形，又，若是超過3000 /zm 201014476 ，則金屬電路所佔據之面積本身會變得過大，而成爲與所 期望之目的背道而馳。 藉由如此這般地在多孔導通部處設置2個以上的導通 貫孔，當適用有熱時，起因於樹脂薄膜與導通貫孔內之金 屬電路間的熱膨脹係數之差異而被施加在導通貫孔內之金 屬電路處的壓縮或是拉張應力，係能夠分散至此些之各導 通貫孔中，而能夠對於金屬電路之斷線作抑制。 φ 並且，若是如此這般地而設置2個以上的導通貫孔， 則例如就算是在1個的導通貫孔中而產生有金屬電路之斷 線，亦可藉由其他之導通貫孔來保持導通，因此，亦具備 有不會使被形成在樹脂薄膜上之金屬電路完全地被斷線的 效果。 進而，相較於如同先前技術一般地而僅形成1個的導 通貫孔的情況，由於係能夠將導通貫孔之內徑縮小’因此 ，亦具備有能夠將被施加在導通貫孔內之金屬電路處的壓 φ 縮或是拉張應力的影響更進一步地降低之效果。本發明’ 係經由此些作用之相輔相成，而能夠對於金屬電路之斷線 大幅度的作抑制。 〈導通貫孔〉 被包含於本發明之多孔導通部110中的導通貫孔120 ，係爲以將樹脂薄膜100之表背面貫通的方式而被設置之 孔，藉由在此導通貫孔內形成金屬電路’能夠將樹脂薄膜 100之表背面的金屬電路作導通。 -15- 201014476 於此，所謂在導通貫孔內形成金屬電路，係指在導通 貫孔之內壁面上形成金屬電路一事，如此這般而被形成之 金屬電路，係能夠以將導通貫孔之全體作塡充的方式來形 成之，亦能夠以在導通貫孔內殘留有空洞的方式來形成爲 通孔（through hole)狀。 又，此導通貫孔，從對於樹脂薄膜之表背面的金屬電 路之導通作保障的觀點來看，其內徑係以設爲較大爲理想 ，但是，若是越將該內徑增大，則由於在如同前述一般而 被施加有熱時，施加於導通貫孔內之金屬電路處的壓縮或 是拉張之應力會越集中，因此，金屬電路之斷線係成爲容 易產生。 故而，導通貫孔，係以設爲5/zm以上300/zm以下 之內徑爲理想，又以設爲10/zm以上50/zm以下之內徑 爲更理想，又以設爲15/zm以上20ym以下之內徑爲更 加理想。又，從對於在被施加有熱時之導通貫孔之切斷作 防止的觀點來看，其剖面，係以0.2mm2以下爲理想。 若是導通貫孔之內徑爲較3 00 /zm更大，則由於上述 之理由，導通貫孔內之金屬電路係成爲容易斷線，故並不 理想。又，若是導通貫孔之內徑爲較5#m更小，則不只 是導通貫孔之加工會成爲困難，且在爲了於導通貫孔內形 成電鍍層而進行電鍍時，電鍍液亦成爲難以浸入至導通貫 孔中，因此，亦並不理想。 又，導通貫孔120之形成個數，係以對於1處的多孔 導通部而形成2〜7個左右爲理想，又以形成3〜5個左右 -16- 201014476 爲更理想。相對於此，如前述一般，若是對於1個的導通 部而僅形成1個的導通貫孔，則由於前述之理由，金屬電 路之斷線係成爲容易產生，故並不理想。又，若是將導通 貫孔形成8個以上，則在多孔導通部之面積成爲過廣一點 上，係並不理想，且導通貫孔之加工時間係變長，而使成 本變高，在這點上，亦並不理想。 導通貫孔之內徑與在多孔導通部中所包含之導通貫孔 φ 的個數間之關係，例如，當導通貫孔之內徑爲5 # m以上 未滿50/zm的情況時，係以形成2〜7個的導通貫孔爲理 想，而，當導通貫孔之內徑爲50/zm以上SOOym以下的 情況時，係以形成2個或3個的導通貫孔爲理想。 但是，當導通貫孔之大小係由於構造上的因素而不得 不增大的情況等時，則僅限於該部位，亦可代替多孔導通 部，而如同先前技術一般地來藉由1個的導通貫孔而形成 導通部。但是，若是從避免熱應力所致之金屬電路的斷線 φ 之觀點來看，則當然的，係以對於1個的多孔導通部而在 上述之範圍內來盡可能地設置更多的導通貫孔爲理想。 又，若是將上述樹脂薄膜之厚度設爲T，並將上述導 通貫孔之內徑設爲d，則係以成爲0<d/TS60爲理想， 又以成爲0.01<d/TS6爲更理想，而又以成爲0.3<d/ T $ 2爲更加理想。如此這般，藉由將d/ T之値控制在特 定之數値範圍內，能夠對於熱應力所致之導通貫孔內的金 屬電路之斷線，作極爲有效的防止。另外，若是d/T之 値成爲較60更大，則相對於樹脂薄膜之厚度，由於導通 -17- 201014476 貫孔之內徑係變得過大，因此，當被施加有熱時，被施加 在導通貫孔內之金屬電路處的壓縮或是拉張應力係變得過 大，而使導通貫孔內之金屬電路成爲容易斷線，故並不理 想。 〈樹脂薄膜之熱膨賬係數〉 在本發明之多層層積電路基板中所使用的樹脂薄膜之 熱膨脹係數，係以lppm/°C以上300ppm/°C以下爲理想 ，又以2ppm/°C以上200ppm/°C以下爲更理想，而又以 3ppm/ °C以上150ppm/ °C以下爲更加理想。若是樹脂薄 膜之熱膨脹係數成爲較1 ppm/ °C更小，則樹脂薄膜係變 得脆弱，故並不理想，又，若是變得較300ppm/°C更大 ，則當被施加有熱時.，由於樹脂薄膜之膨脹，多層層積電 路基板係會變形，並在導通貫孔內之金屬電路處施加應力 ，而成爲容易在金屬電路處產生斷線，故並不理想。於此 ，在本發明中，所謂熱膨脹係數，係設爲相對於樹脂薄膜 之寬幅方向的垂直方向（亦即是長度方向）上之熱膨脹係 數。 另外，在多層層積電路基板之容易變形的部分處，係 以使用熱膨脹係數爲大之樹脂薄膜爲理想，並以將樹脂薄 膜之厚度增厚爲理想。 又，在本發明之多層層積電路基板所包含的樹脂薄膜 中，係以使任1層之樹脂薄膜的熱膨脹係數成爲與其他之 至少1層的樹脂薄膜之熱膨脹係數相異爲理想。如此這般 -18- 201014476 ，藉由在至少1層之樹脂薄膜處使用具備有與其他之樹脂 薄膜相異的熱膨脹係數者’能夠對於在此些之樹脂薄膜之 間的因應於與熱源間的距離所產生之膨脹差作緩和，故而 ，能夠對於導通貫孔內之金屬電路的斷線作抑制。 〈多層層積電路基板之使用態樣〉 本發明之多層層積電路基板，例如，係可如圖3中所 φ 示一般，作爲下述一般之構成來使用：將多層層積電路基 板之最下面的金屬電路50與硬基板301，藉由接著金屬 401來作貼合，並將多層層積電路基板之最上面的金屬電 路50與Si基板302，藉由密著金屬402來作貼合。於此 情況，接著金屬401與密著金屬4 02，係均以藉由銲錫來 形成爲理想，但是，關於密著金屬402，係並不被限定於 藉由銲錫來形成，而亦可經由焊接（bonding )或是經由 柱螺栓銷（stud pin )與銲錫凸塊之組合來形成。又，在 Si基板302處’係亦可使用硬基板或是銅基板，而在硬基 板301處，係亦可使用Si基板或是銅基板。又，從對於 在被施加有熱時之此些之切斷作防止的觀點來看，接著金 屬401以及密著金屬402之剖面，係以〇.2mm2以下爲理 想。 在此種多層層積電路基板之使用態樣的情況時，最上 層之S i基板3 0 2 ’其熱膨脹係數係爲小，而最下層之硬基 板3 01 ’其熱膨脹係數係爲大，因此，被層積在此些之間 之樹脂薄膜的熱膨脹係數’係以使越靠S i基板3 0 2側之 -19- 201014476 樹脂薄膜的熱膨脹係數越小，而越靠硬基板3 0 1側之樹脂 薄膜的熱膨脹係數越大的方式，來對樹脂薄膜作選定爲理 想。 更具體而言，被層積在接近Si基板3 02處之樹脂薄 膜的熱膨脹係數，係以2Ppm/°C以上10Ppm/t：以下爲 理想，又以3ppm/°C以上5ppm/°C以下爲更理想。若是 熱膨脹係數爲較2ppm/ °C更小，則多層層積電路基板係 變得過度脆弱，而使處理變得困難，故並不理想，而若是 熱膨脹係數成爲較10ppm/°C更大，則Si基板3 02之熱 膨脹係數與樹脂薄膜之熱膨脹係數間的差異係變得過大， 而使多層層積電路基板產生變形，並容易在導通貫孔內之 金屬電路處產生斷線，故並不理想。 又，被層積在接近於硬基板301處之樹脂薄膜，係以 使用熱膨脹係數爲接近於硬基板301之熱膨脹係數的材料 爲理想。又，當硬基板有被作彎曲的情況時，係以使用能 夠與此彎曲相對應之樹脂薄膜爲理想。又，當在上述之Si 基板或是硬基板之任一者或是雙方處而使用有銅基板的情 況時，在銅基板之附近所被層積之樹脂薄膜，係以使用熱 膨脹係數爲接近於銅基板之熱膨脹係數（16.8Ppm/ t ) 的材料爲理想，而該値，係以l〇ppm/°C以上20ppm/t 以下爲理想，又以15ppm/°C以上18ppm/°C以下爲更理 想。 〈構件或製品〉 -20- 201014476 本發明之多層層積電路基板，係被使用在一般性之構 件或是製品中。於此製品中，例如係可列舉有電性製品、 電子製品、半導體製品、天線電路基板、1C卡、太陽電池 、汽車或者是機器人等。 〈多層層積電路基板之製造方法> 本發明之多層層積電路基板之製造，首先，係在樹脂 Φ 薄膜100之各多孔導通部處，形成將表背面作貫通一般之 2個以上的導通貫孔120，而後，涵蓋樹脂薄膜100之表 面全體（包含導通貫孔之內壁面）地來形成基底層130, 並於其上藉由電鍍來形成電鍍層140。 而後，將基底層130與電鍍層140之一部分除去，而 形成金屬電路50，並經由接著性樹脂70，來將另外的樹 脂薄膜1 〇〇作貼附。接著，在此新貼附之樹脂薄膜1 00的 多孔導通部之位置處，形成2個以上的導通貫孔，而後， • 與上述相同的而形成金屬電路。藉由對於以上之操作而使 用長尺狀之樹脂薄膜來連續性地反覆進行，而製造本發明 之多層層積電路基板。 如同上述一般，若是藉由以電鍍所形成之電鍍層來構 成金屬電路50，則在導通貫孔內之金屬電路處係難以產生 斷線，並且，就算是將樹脂薄膜多層化，亦能夠對於成本 之上升作抑制，故爲理想。 另外，本發明之多層層積電路基板1的金屬電路50, 例如係亦可藉由餓刻法與半加成（Semi-Additive )法的任 -21 - 201014476 一者之方法來形成。蝕刻法，係在樹脂薄膜之 導通貫孔之內壁面）上而藉由電鍍來形成電鍍 將成爲不必要之部分的電鍍層與基底層藉由蝕 並藉由此來形成金屬電路之方法。 另一方面，半加成法，係對於樹脂薄膜表 通貫孔之內壁面）上之並不會成爲電路的部分 隔劑而進行遮蔽，而後，藉由電鍍來形成必要 鍍層’之後，將阻隔劑剝離，而形成金屬電路, 以下’作爲金屬電路之形成方法，係以半 例子’來對於多層層積電路基板之製造方法作 造方法’係將導通貫孔形成工程、基底層形成 劑形成工程、曝光工程、顯像工程、活性化工 形成工程、阻隔劑剝離工程、軟蝕刻工程以及 積工程依上述順序而反覆進行，並藉由此而製 電路基板之方法。以下，對於此些之工程作說 〈導通貫孔形成工程〉 首先，對於樹脂薄膜100，以形成多孔導 ’來形成3個的導通貫孔120(圖4)。於此 夠以使導通貫孔之深度與樹脂薄膜之厚度成爲 來對於導通貫孔的形成作調節之裝置，則係可 裝置，但是，從能夠以小口徑且低成本地形成 觀點來看，係以使用UV-YAG雷射爲理想。 表面（包含 層，而後， 刻來除去， 面（包含導 ，來藉由阻 之厚度的電 之方法。 加成法作爲 說明。該製 工程、阻隔 程、電鍍層 樹脂薄膜層 造多層層積 明。 通部的方式 ，只要是能 相等的方式 使用任意之 導通貫孔的 201014476 〈基底層形成工程〉 接著，藉由離子槍來對樹脂薄膜100之表面（包含導 通貫孔之內壁面）進行預備處理，而後，在樹脂薄膜100 之表面（包含導通貫孔之內壁面）上形成氧化防止層，並 在氧化防止層上更進而形成基底金屬層，藉由此，而能夠 形成基底層130(圖5)。被包含於基底層130中之氧化 防止層與基底金屬層，例如係可藉由無電解電鍍、蒸鍍、 φ 濺鍍等來形成之。另外，氧化防止層或是基底金屬層，亦 會有其中一方或者是雙方並未被形成的情況。 〈阻隔劑形成工程〉 對於經由上述工程而被形成在樹脂薄膜100上之基底 層130的表面，藉由酸來作洗淨，並使被包含於基底層 130中之基底金屬層的表面活性化，而後，形成阻隔劑（ 未圖示）。此阻隔劑，係可藉由貼合將阻隔劑作了薄膜化 Φ 的乾薄膜之方法來形成，亦可藉由將阻隔劑墨水作塗布的 方法來形成。 將乾薄膜作貼合之方法之優點在於，由於係適合於少 量生產，因此，係能夠對應於多種類之製品，並且，貼合 作業之工程亦並不繁雜，但是，係具備有會使製造成本變 高的問題。 另一方面，將阻隔劑墨水作塗布之方法的優點在於， 由於係適合於大量生產，因此能夠將製造成本降低，但是 ’係具備有塗布工程會成爲繁雜的問題。以下，係對於由 -23- 201014476 貼合乾薄膜之方法所致的阻隔劑之形成作說明。 首先，將圖5中所示之被形成有基底層130的樹脂薄 膜100，安裝於層壓捲繞裝置之送出軸上，並將樹脂薄膜 100之前端安裝在捲繞軸上，而一面將乾薄膜貼附在樹脂 薄膜100之基底層130上，一面使捲繞軸旋轉，而進行捲 繞。如此這般，乾薄膜係被貼附在樹脂薄膜100上，而在 樹脂薄膜之基底層上，係被形成阻隔劑（未圖示）。 上述之層壓時的溫度，係以3 0〜1 5 (TC爲理想，又以 · 60〜110 °C爲更理想。又，層壓時的壓力，係以0.3〜5kg /cm2爲理想，又以2〜3kg/cm2爲更理想。又，層壓了 的樹脂薄膜之捲繞時的線速，係以0.1〜l〇m/分鐘爲理想 ，又以0.5〜3m /分鐘爲更理想。 〈曝光工程〉 接著，在藉由上述工程而形成了阻隔劑之樹脂薄膜上 ，重合與所期望之金屬電路的圖案相對應之遮罩，之後， © 進行UV曝光，並使未被遮罩所覆蓋的部分感光。於此， 被遮罩所覆蓋之部分，係在後續之顯像工程中被除去，並 在後述之電鍍層形成工程中，藉由形成電鍍層而被形成有 金屬電路。 在此曝光中所使用之曝光裝置，係可使用平行光曝光 裝置，亦可使用直接曝光裝置。但是，在形成細微電路之 觀點上，係以使用平行光曝光裝置爲理想，而從能夠對應 於樹脂薄膜之收縮來對曝光之位置作調整的觀點來看，係 -24- 201014476 以使用直接曝光裝置爲理想。 〈顯像工程〉 接著，藉由弱鹼性溶液，來將上述曝光工程之被遮罩 所覆蓋的部分之阻隔劑1 7 〇作顯像。藉由此，能夠得到如 圖6中所示一般之被形成有阻隔劑170的樹脂薄膜100。 在顯像中所被使用之弱鹼性溶液，係以使用碳酸蘇打或是 φ 胺系之材料爲理想。又，弱鹼性溶液之ρ Η，係以7以上 1 3以下爲理想，又以8.5以上1 0.0以下爲更理想。若是 弱鹼性溶液之pH爲較7更小，則由於阻隔劑係並不會被 除去，故並不理想，而若是Ph較13爲更高，則連在上述 曝光工程中之未被遮罩所覆蓋的部分之阻隔劑170亦會全 部被剝離，故並不理想。 又，弱鹼性溶液的溫度，係以1 0〜7 0 °C爲理想，又以 20〜35°C爲更理想。若是弱鹼性溶液之溫度爲較l〇°C更低 φ ，則由於阻隔劑1 70係並不會被除去，故並不理想，而若 是弱鹼性溶液之溫度較70°C爲更高，則連作了 UV曝光的 部分之阻隔劑1 70亦會被剝離，故並不理想。另外，顯像 之時間，由於係依存於阻隔劑之種類而有所不同，因此， 並無法一律性地作規定，但是，通常係以設爲20秒以上 3 0 0秒以下左右爲理想。 〈活性化工程〉 接著，將顯像後之樹脂薄膜100上的基底層130 (基 -25- 201014476 底金屬層）之表面，藉由酸系之溶液來活性化。藉由此， 能夠防止電鍍層與基底層（基底金屬層）間之密著不良。 在此活性化中所被使用之酸系溶液，只要是展現有酸性者 ，則係可爲任意之物，但是，從能夠以低成本來作活性化 的觀點來看，係以使用HC1、H2S04、過硫酸銨等爲理想 〇 又，在酸系之溶液中所包含的酸之濃度，係以0.5〜 20質量％爲理想，又以3〜10質量％爲更理想。若是酸系 之溶液的濃度爲較0.5質量％更低，則由於基底層（基底 金屬層）之表面係難以被活性化，故並不理想，而若是酸 系之溶液的濃度爲較20質量％更高，則由於會有在基底層 (基底金屬層）之表面上產生異常之虞，故並不理想。 又’進行活性化時之酸系的溶液之溫度，係以10〜70 °C爲理想’又以30〜50°C爲更理想。若是將酸系之溶液的 溫度設爲較10 °C更低，則會在基底層之活性化中耗費過多 的時間’故並不理想，而若是將酸系之溶液的溫度設爲較 70 °C更高’則由於會產生環境面上的問題，故並不理想。 又’處理時間，由於係依存於基底層（基底金屬層）之表 面狀態而有所不同，因此，並無法一律性地作規定，但是 ’通常係以設爲3秒以上3 00秒以下左右爲理想。 〈電鍍層形成工程〉 接著’在藉由上述工程而活性化了的基底層130上， 經由進行電銨，而形成如圖7中所示一般之電鍍層140。 -26- 201014476 在此電鍍中所使用之電鍍液，只要是包含有形成電鍍層之 金屬的酸性之溶液’則係可爲任意之物，但是，從電鑛液 本身係爲安定且能夠以低成本來進行電鍍的觀點來看，係 以使用硫酸銅、焦磷酸銅等爲理想。另外，當在電鍍液中 使用硫酸銅的情況時，硫酸銅之濃度，係以30〜300g/1 爲理想’又以70〜150g/l爲更理想。又，此電鍍液之氯 離子濃度’係以10〜lOOppm爲理想，又以40〜70ppm爲 φ 更理想。 又，作爲在電鍍液中所使用之酸性溶液，係以使用硫 酸爲理想’當使用硫酸的情況時，硫酸之濃度，係以50〜 300g/l爲理想，又以80〜200g/l爲更理想。 又，進行電鍍時的電流密度，係以0.1〜10A/dm2爲 理想’又以0.5〜4A/dm2爲更理想。又，進行電鍍時之 電鍍液的溫度，係以2 0〜6 0 °C爲理想，又以3 0〜4 0。(：爲 更理想。另外，關於電鍍時間，由於係依存於電鍍層之厚 φ 度而有所不同，因此，並無法一律性地作規定，但是，通 常係以設爲600秒以上6000秒以下左右爲理想。 〈阻隔劑剝離工程〉 接著，在藉由上述之電鍍工程而形成了金屬電路後， 使用鹼性溶液來進行阻隔劑之剝離。在阻隔劑之剝離中所 使用的鹼性液，只要是展現有鹼性之溶液，則係可爲任意 之物，但是，從鹼性液本身之安定性或是鹼性液之成本的 觀點來看，係以使用氫氧化鈉或是醇系之物爲理想。 -27- 201014476 又，當在鹼性液中使用氫氧化鈉的情況時，氫氧化鈉 之濃度，係以0.1〜50質量％爲理想，又以1〜10質量％爲 更理想。又，在阻隔劑剝離中所使用之鹼性液的溫度，係 以30〜90°c爲理想，又以50〜70°C爲更理想。另外，阻 隔劑剝離之時間，由於係依存於阻隔劑之剝離狀態而有所 不同，因此，並無法一律性地作規定，但是，通常係以設 爲2 0秒以上120秒以下左右爲理想。 〈軟蝕刻工程〉 接著，經由以軟蝕刻來將基底層130剝離除去，而得 到如圖8中所示一般之被形成有金屬電路50的樹脂薄膜 。在被包含於基底層中之基底金屬層的剝離時所使用的藥 品，係可使用任意之物，但是，從低成本的觀點來看，係 以使用過硫酸銨爲理想。當使用此過硫酸銨的情況時，過 硫酸銨之濃度，係以1〜20%爲理想，又以5〜10%爲更理 想。 又，在對基底金屬層進行軟飩刻時之處理溫度，係以 20〜60 °C爲理想，又以30〜40 °C爲更理想。另外，在此軟 蝕刻之剝離中所耗費的時間，由於係依存於基底金屬層之 厚度或是藥品之濃度而有所不同，因此，並無法一律性地 作規定，但是，通常係以設爲30秒以上200秒以下左右 爲理想。 又，作爲在氧化防止層之剝離中所使用的藥品，係以 使用鎳鉻剝離液（商品名：NC (日本化學工業股份有限公 -28- 201014476 司製））爲理想。又，當使用此藥品的情況時，此藥品之 濃度，係以60〜100%爲理想。若是此藥品之濃度較60% 更低，則會耗費剝離時間，故並不理想。 又，在對氧化防止層進行軟蝕刻時之處理溫度，係以 3 5〜5 5 °C爲理想。另外，在此軟蝕刻之剝離中所耗費的時 間，由於係依存於氧化防止層之厚度或是藥品之濃度而有 所不同，因此，並無法一律性地作規定，但是，通常係以 φ 設爲20秒以上300秒以下左右爲理想。 〈樹脂薄膜層積工程〉 接著，作爲對於如同上述一般而得到了的附有電路之 樹脂薄膜（被形成有金屬電路之樹脂薄膜）的表、背面之 其中一面或是雙面而層積其他之樹脂薄膜的方法，係存在 有：將附加了接著性樹脂70之樹脂薄膜藉由層壓來貼合 在附有電路之樹脂薄膜的一面上之方法、以及先對於附有 • 電路之樹脂薄膜的金屬電路形成面來塗布接著性樹脂7〇, 再將尙未被形成有金屬電路之樹脂薄膜藉由層壓來作貼合 之方法等，不論經由何者之方法，均能夠如同圖9中所示 一般地而將樹脂薄膜作層積。 另外，若藉由後者之樹脂薄膜之層積方法，則當金屬 電路之厚度爲厚的情況時，係能夠將金屬電路所致之樹脂 薄膜的表面凹凸減少，因此，係具有能夠更進而提升接合 強度的優點。 又，在對於上述之附有電路之樹脂薄膜的表背面之任 -29- 201014476 一面或是兩面而層積其他之樹脂薄膜100時的溫度，係以 30〜300°C爲理想，而在層積時所施加之壓力，係以0.1〜 20kg/cm2爲理想。又，在此樹脂薄膜之層積中所耗費的 時間，係以1秒以上3小時以下爲理想。 而後，進行導通貫孔形成工程，如此這般，藉由反覆 進行上述所說明了的各工程，能夠製造如圖1中所示一般 之本發明的多層層積電路基板。以下，列舉出實施例，來 對於本發明作更爲詳細之說明，但是，本發明係並不被限 定於此些之實施例。 〔實施例〕 〈實施例1〉 在實施例1中，作爲金屬電路之形成方法，係採用蝕 刻法，並藉由以下之各工程，而製作了多層層積電路基板 〈導通貫孔形成工程〉 作爲在多層層積電路基板中所使用之樹脂薄膜100, 係使用被捲繞爲筒狀之長尺狀的聚醯亞胺薄膜（長度5 0m ，厚度 38μιη，商品名：KAPTON EN150(TORAY.杜邦 股份有限公司製）。此樹脂薄膜之熱膨脹係數，係爲 l6ppm/ °C以上17ppm/ °C以下，並使用以250mm寬幅而 作了細縫加工者。將此樹脂薄膜100安裝在UV-YAG雷射 裝置上，並對UV-YAG雷射裝置之程式作設定，來對於1 -30- 201014476 個的多孔導通部而在3個場所處形成內徑Ι5μπι之 孔 120 (圖 4)。 〈洗淨工程〉 將藉由上述工程而形成了導通貫孔120之樹脂 1〇〇安裝在洗淨裝置上，並爲了對於在基底層之形成 中的針孔之產生作抑制，而將樹脂薄膜100之表面作 淨。 〈基底層形成工程〉 接著，將藉由上述工程而將表面作了洗淨的樹脂 1〇〇投入至濺鍍裝置中，並藉由真空幫浦來設定爲 3Pa之壓力，再將Ν2氣體注入至離子槍中，而藉由以 槍進行照射來對於樹脂薄膜之表面作了預備處理。而 藉由濺鍍法，而在Ar氣體氛圍下來在樹脂薄膜上形 φ Ni與Cr之合金（Ni與Cr之重量比，係爲Ni : Cr = 20)所成的氧化防止層，並於其上形成由Cu所成之 金屬層，藉由此，而形成了基底層130(圖5)。 而後，將濺銨裝置之真空狀態解除，並將被形成 底層130之樹脂薄膜100取出，而對於樹脂薄膜100 部分作了取樣。而後，藉由對於該樣本照射聚焦離子 FIB ： Focused Ion Beam)，而對剖面作了觀察。其結 係確認了：氧化防止層之厚度係爲1 ，而基底金 厚度係爲3 5 0nm。進而，係確認了 ：在導通貫孔120 通貫 薄膜 工程 了洗[Technical Field] The present invention relates to a multilayer laminated circuit board, in particular, a multilayer laminated circuit board in which disconnection of a metal circuit is difficult. [Prior Art] Products that exist around us (such as electrical products, electronic products φ, semiconductor products, antenna circuit boards, 1C cards, robots, etc.) are popular with small products that do not occupy too much space. 'There are products that are expected to be further miniaturized. In order to cope with the needs of such products, it has been advantageous to develop the technology for miniaturization of products in an attempt to miniaturize the products and to try to miniaturize the inside of the products. However, it has been said that the miniaturization of the product in the direction of miniaturization of the product can be said to have reached the limit, and it has been desired to further miniaturize the inside of the product. Φ In this case, the direction in which the inside of the product is miniaturized has been attracting attention in recent years in the method of making the circuit board used in the product a light and thin circuit structure. The circuit board of the prior art has been reviewed as follows: a circuit of one or two layers is formed on a plane, and the circuit substrate is miniaturized by minimizing the circuit itself, but if it is formed only by In the miniaturization of the circuit on the plane, there is still a limit to miniaturization. Therefore, it has been reviewed for a multilayer laminated circuit board in which a circuit board is multilayered and a circuit is formed in a three-dimensional manner. Such a multilayer laminated circuit substrate is generally produced by a build-up (-5-201014476 build up) method. The build-up method is performed by partially etching a conductive layer formed on an insulating resin film to form a metal circuit, and then applying an adhesive to the metal circuit. Further, a resin film on which a conductive layer is formed is bonded. Then, a via hole is formed in the conductive portion of the bonded resin film, and a plating or paste or the like is formed inside the via hole. Then, the conductive layer of the bonded resin film is partially removed by etching, and a metal circuit is formed. After that, the above work is repeated, and the metal circuit is multilayered. However, the multilayer laminated circuit substrate formed by the build-up method has a problem that if a heat is applied to itself, a disconnection occurs at the metal circuit. Japanese Patent Laid-Open Publication No. 2005-2439 No. 1 (Patent Document 1), JP-A-2007-26648 (Patent Document 2), JP-A-2008-060582 (Patent Document 3), and JP-A 2007 In order to solve such problems, Japanese Patent Laid-Open No. Hei. No. 2005-22309 (Patent Document 5) and Japanese Patent Laid-Open Publication No. 2008-091 439 (Patent Document No. 5) There have been various attempts, but neither of the multilayer laminated circuit boards has been able to adequately solve the above problems. Hereinafter, the outline of the multilayer laminated circuit substrate shown in Patent Documents 1 to 6 will be briefly described. In the multilayer laminated circuit board of Patent Document 1, by using a solder having a low melting point which does not contain lead in the connection of a metal circuit of a resin film of two layers, the bonding strength between the resin films is improved, and the metal circuit is prevented. Broken line. However, in the multilayer laminated circuit substrate, when heat is applied, the low melting point solder of -6-201014476 is melted again, and the metal circuit is broken. In Patent Document 2, it is described that the conductive via hole is bored in a through hole that is penetrated from the metal circuit on the front side to the metal circuit on the back side, and is flexible. The bonding strength between the substrate and the reinforcing substrate is increased and joined, thereby preventing the disconnection of the metal circuit. However, as in Patent Document 1, when heat is applied, the metal circuit is easily broken. φ In Patent Document 3, a multilayer laminated circuit board in which resin films are joined to each other by solder bumps is described. However, since it is difficult to reduce the diameter of the solder bumps, there is a problem that it is not possible to cope with the miniaturization of the multilayer laminated circuit board. Patent Document 4 discloses a multilayer laminated circuit board in which a conductive resin is filled in a through hole of a multilayer laminated circuit board, but in a metal circuit due to heat generated by conduction during a long period of time. Breaking the line - in fact, there are still concerns. Φ In Patent Document 5, when the resin film is laminated, the conductive paste is filled in the through-holes to improve the adhesion between the resin films on the front and back surfaces, but the conductive paste and the resin are used. The degree of adhesion between the films is not sufficient. Further, Patent Literature 6 describes a multilayer laminated circuit board in which the positional deviation of the laminated resin films is prevented by using an adhesive agent in the bonding between the resin films. The prevention of positional deviation alone does not mean that the disconnection of the metal circuit can be sufficiently prevented. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 [Patent Document 4] JP-A-2007-33 563 1 (Patent Document 5) Japanese Laid-Open Patent Publication No. 2005-223010 (Patent Document 6) JP-A-2008-091439A SUMMARY OF INVENTION [Invention] MEANS TO SOLVE THE INVENTION As described above, in Patent Documents 1 to 6, all of them are provided by a method of improving the adhesion between the resin films and the subsequent materials, thereby providing a multilayer laminate in which it is difficult to cause breakage of the metal circuit. Circuit board. However, in any of the above-described multilayer laminated circuit boards, since the conductive portions are formed by one through-hole, there is a problem in common, that is, if it is itself When the heating is applied, since the thermal expansion coefficient of the resin film is different from the thermal expansion coefficient of the metal circuit in the through-hole, the metal circuit in the through-hole is applied by the difference in thermal expansion. The compression or tensile stress causes the metal circuit in the through hole to be broken. Further, as another problem, for example, when heat is applied to the multilayer laminated circuit substrate, the distance between the plurality of resin films included in the multilayer laminated circuit substrate is determined by the distance from the heat source. In the case of -8-201014476, a difference in expansion occurs between the resin films, and the multilayer laminated circuit substrate is deformed, and a stress is applied to the metal circuit formed in the through hole formed in the resin film. The problem of disconnecting the metal circuit. The present invention has been made in view of the above general circumstances, and an object thereof is to provide a multilayer laminated circuit board in which disconnection of a metal circuit is hard to occur. [Means for Solving the Problem] The multilayer laminated circuit board of the present invention is a multilayer laminated circuit board including a laminated structure in which a resin film and a circuit layer are alternately laminated, and the resin film is characterized by The porous conductive portion has one or more porous conductive portions, and the porous conductive portion has a diameter of 10/zm or more and 3000#m or less, and has two or more through-holes, and the through-hole is provided with 5ΜΠ1 Above 300//m inner diameter. Further, if the thickness of the resin film is T and the inner diameter of the through-hole is d, it becomes 0. <d/TS60 is preferable. Further, the above-mentioned resin film is preferably used for processing a long-sized object. Further, the present invention is a skid or article using a multilayer laminated circuit board. Further, preferably, the product is any one of an electrical product, an electronic product, a semiconductor product, an antenna circuit board, a 1C card, a solar battery, a car, or a robot. [Effects of the Invention] The multilayer laminated circuit board of the present invention has the effect of making it difficult to cause disconnection of the metal circuit by providing each of the above-described configurations. [Embodiment] <Multilayer laminated circuit board> Hereinafter, a multilayer laminated circuit board of the present invention will be described with reference to Fig. 1 . Fig. 1 is a schematic cross-sectional view showing an example of a multilayer laminated circuit substrate of the present invention. In the drawings, the same reference numerals are used to refer to the same or equivalent parts. The multilayer laminated circuit board 1 of the present invention, as shown in Fig. 1, generally has a laminated structure in which a resin film 100 and a circuit layer 200 are alternately laminated. Further, although Fig. 1 shows a structure in which the resin film 100 is laminated in three layers, the minimum number of layers in the laminated structure in the present invention is that the resin film 1 is laminated in two layers. Construction. In this case, the number of layers of the circuit layer 200 can be two or three. On the other hand, the maximum number of layers of the laminated structure in the present invention is not particularly limited, and may be laminated in accordance with the use, but generally, generally, the resin film 100 is laminated. It is 2 to 30 layers or so. Here, the resin film 100 of the multilayer laminated circuit board 1 of the present invention is characterized in that it has one or more porous conductive portions 110, and a surface of the resin film is provided at the porous conductive portion 110. Two or more through holes 12 are formed through the back surface. In this manner, it is possible to prevent the occurrence of disconnection of the metal circuit by providing two or more through-holes 120, -10-201014476 through which the front and back surfaces of the resin film 100 are penetrated. Hereinafter, each component included in the multilayer laminated circuit board of the present invention will be described. <Resin film> The multilayer laminated circuit board of the present invention contains two or more resin films. Further, these resin films are made of an insulating material, and any of the resin films known in the prior art which are used in such applications can be used. As such a resin film, for example, polyimine (PI), acrylic, liquid crystal polymer (LCP), polyethylene terephthalate (PET), polyethylene naphthalate (for polyethylene naphthalate) can be used. A resin film such as PEN). Such a resin film is preferably used for processing a long-sized object. The resin film of such a long shape is preferably, for example, preferably having a length of about 1 to 1000 m, and more preferably about 1 to 3000 m. By using a long-sized person, it is possible to carry out continuous processing φ and to improve production efficiency. If it is less than lm, it is difficult to use it as a package, and it is unsatisfactory to reduce the processing efficiency. If it is more than 1000 μm, in the formation of a base layer to be described later, There is a hindrance to continuous processing, so it is not ideal. In addition, the term "the resin film is long-sized" means that it has a length as described above, and is suitable for use as a shape that is wound into a cylindrical shape. However, even if the above-mentioned general length is not satisfied, If it is handled by laminating a plurality of resin films as a long-sized one, it is also included in the scope of the present invention. -11 - 201014476 Further, the thickness of the resin film 100 is preferably 3/zm or more and 200/zm or less. If the thickness of the resin film 1 is thinner, the workability of the resin film is too poor, so it is not preferable, and if it is thicker than 200 m, it is difficult to turn on the through hole 12 Processing is not ideal. <Circuit Layer> A metal circuit 50 is included in the circuit layer 200 formed on the resin film 100 of the present invention. Further, the portion other than the metal circuit 50 of the circuit layer 200 may be filled with the insulating adhesive resin 70, and the resin film 1 may be bonded to each other via the adhesive resin 70. . As described above, the circuit layer 200 of the present invention can be constituted only by the metal circuit 50, or can be constituted by the metal circuit 50 and the adhesive resin 70. <Metal Circuit> The metal circuit 50 includes the electrode layer 140, and may further include a base layer 130 between the plating layer 140 and the resin film 100. Further, in the present invention, it is convenient to refer to the case where the underlayer 130 and the plating layer 140 formed in the via hole 120 are referred to as the metal circuit 50. Here, the underlayer 130 has a function of improving the adhesion between the shovel layer 140 and the resin film 100, and can be formed into one layer or two or more layers. When the base layer 130 is formed into two or more layers of -12 to 201014476, it is preferable to include the oxidation preventing layer and the base metal layer. Such a base layer can be formed by any method, but can be formed, for example, by electroless plating, evaporation, sputtering, or the like. In particular, from the viewpoint of being able to accurately control the film thickness, it is preferably formed by sputtering. The oxidation preventing layer is made of at least one metal selected from the group consisting of Ni, Cr, Ti, Co, and Si, or an alloy containing at least one of the gold Φ genus. The thickness is preferably 2 to 20 nm. Further, the underlying metal layer is preferably formed on the oxidation preventing layer, and is formed by a group consisting of 〇\1, human\1, human giant, 811, :!, 81, and B11. It is preferable that at least one of the selected metals or an alloy containing at least one of the metals is included. Further, the thickness of the underlying metal layer is preferably about 50 to 500 nm. Further, the plating layer 140 is a layer formed by electroplating, and is made of at least one metal selected from the group consisting of Cu, Au, Ag, Sn, Ni, Bi, and Zn, or It is preferable that the metal contains at least one type of alloy, and it is more preferably composed of Cu or an alloy containing Cu. Further, in the case of forming the aforementioned underlying metal layer, it is preferable that the underlying metal layer and the plating layer 140 are made of the same material. <Adhesive Resin> The following resin 70 can be used as long as it can bond the resin film 1 used in the multilayer laminated circuit board-13-201014476 to each other. An epoxy resin, an acrylic resin, a polyimide resin, or the like can be used. <Porous Conduction Portion> Each of the resin films 100 constituting the multilayer laminated circuit board 1 of the present invention includes one or more porous conductive portions 110, and two or more conductive members are provided at the porous conductive portions. Through hole 120. Here, the porous conductive portion refers to a portion formed of a metal circuit that is intended to be electrically connected to the front and back surfaces of the resin film, and is formed by forming two or more resins. The back surface of the film is made to pass through the through hole to ensure the conduction of the front and back sides. In addition, the porous conductive portion refers to a cylindrical region including a plurality of through-holes formed at a desired portion and closely adjacent to each other, and the cross-sectional area thereof is minimized, and the sectional area is The resin film is preferably in a region occupying a diameter of not less than 3,000 m and not more than 3,000 m. That is, for example, as shown in FIG. 2, when there are three adjacent through-holes 120, the porous conductive portion 11〇 refers to the three conductive through-holes. All, and the area of the cross section of the cylindrical region becomes the smallest area. The diameter of the porous conducting portion is preferably 3,000 " m or less as described above. If the diameter of the porous conducting portion is less than 10 //m, there is a case where the conduction of the metal circuit formed on the front and back surfaces of the resin film cannot be sufficiently ensured, and if it exceeds 3000 /zm 201014476, the metal circuit The area occupied itself becomes too large and becomes contrary to the desired purpose. By providing two or more through-holes in the porous conducting portion as described above, when heat is applied, it is applied to the conduction through the difference in thermal expansion coefficient between the resin film and the metal circuit in the through-hole. The compression or tensile stress at the metal circuit in the hole can be dispersed into each of the through vias, and the disconnection of the metal circuit can be suppressed. φ Further, if two or more through-holes are provided in such a manner, for example, even if a metal circuit is broken in one of the through-holes, it can be held by other through-holes. Since it is turned on, there is also an effect that the metal circuit formed on the resin film is not completely broken. Further, in the case where only one through hole is formed as in the prior art, since the inner diameter of the through hole can be reduced, "the metal which can be applied in the through hole is also provided. The effect of the pressure φ at the circuit or the tensile stress further reduces the effect. The present invention is capable of suppressing the disconnection of the metal circuit largely by the complementary phase of these effects. <Connecting through hole> The through hole 120 included in the porous conducting portion 110 of the present invention is a hole that is provided to penetrate the front and back surfaces of the resin film 100, and is formed therein through the through hole. The metal circuit 'can electrically connect the metal circuit on the front and back sides of the resin film 100. -15- 201014476 Here, the formation of a metal circuit in the through hole refers to the formation of a metal circuit on the inner wall surface of the through hole, and the metal circuit thus formed can be used to conduct the through hole. It is also possible to form a through hole in such a manner as to fill the hole in the through hole. Moreover, it is preferable that the through-hole is made larger from the viewpoint of ensuring the conduction of the metal circuit on the front and back surfaces of the resin film, but if the inner diameter is increased, When heat is applied as described above, the stress applied to the metal circuit in the through-hole is more concentrated, so that the disconnection of the metal circuit is likely to occur. Therefore, the through-hole is preferably an inner diameter of 5/zm or more and 300/zm or less, and more preferably an inner diameter of 10/zm or more and 50/zm or less, and is set to 15/zm. The inner diameter of 20 ym or less is more desirable. Further, from the viewpoint of preventing the cutting of the through-holes when heat is applied, the cross-section is preferably 0.2 mm 2 or less. If the inner diameter of the through hole is larger than 300 / zm, the metal circuit in the through hole is easily broken due to the above reasons, which is not preferable. Further, if the inner diameter of the through hole is smaller than 5 #m, it is difficult to process not only the through hole but also the plating solution in order to form a plating layer in the through hole. Immersion into the through-holes is therefore not ideal. Further, the number of the through-holes 120 is preferably 2 to 7 for one porous conductive portion, and more preferably 3 to 5 -16 to 201014476. On the other hand, as described above, when only one through-hole is formed for one conductive portion, the disconnection of the metal circuit is likely to occur, which is not preferable. In addition, when eight or more through-holes are formed, the area of the porous conductive portion is too large, which is not preferable, and the processing time of the conductive through-hole is long, and the cost is increased. It is not ideal. The relationship between the inner diameter of the through hole and the number of the through holes φ included in the porous conducting portion, for example, when the inner diameter of the through hole is 5 # m or more and less than 50/zm It is preferable to form 2 to 7 through-holes, and when the inner diameter of the through-holes is 50/zm or more and SOOym or less, it is preferable to form two or three through-holes. However, when the size of the through hole is increased due to structural factors, etc., it is limited to this portion, and it is also possible to replace the porous conductive portion, and as in the prior art, one conduction is generally used. The through hole forms a conduction portion. However, from the viewpoint of avoiding the disconnection φ of the metal circuit due to thermal stress, it is of course possible to provide as many conduction paths as possible within the above range for one porous conduction portion. The hole is ideal. Further, if the thickness of the resin film is T and the inner diameter of the through-hole is d, it becomes 0. <d/TS60 is ideal, and becomes 0.01 <d/TS6 is more ideal, but to become 0.3 <d/ T $ 2 is more desirable. In this way, by controlling the d/T within a specific range of 値, it is possible to effectively prevent the breakage of the metal circuit in the via hole due to thermal stress. In addition, if the d/T becomes larger than 60, the inner diameter of the through hole -17-201014476 becomes too large with respect to the thickness of the resin film, and therefore, when heat is applied, it is applied to The compression or tensile stress at the metal circuit in the through hole is too large, and the metal circuit in the through hole is easily broken, which is not preferable. <The thermal expansion coefficient of the resin film> The thermal expansion coefficient of the resin film used in the multilayer laminated circuit board of the present invention is preferably 1 ppm/° C. or more and 300 ppm/° C. or less, and is 2 ppm/° C. or more. More preferably, it is 200 ppm/°C or less, and more preferably 3 ppm/°C or more and 150 ppm/°C or less. If the thermal expansion coefficient of the resin film is smaller than 1 ppm/°C, the resin film becomes weak, which is not preferable, and if it is larger than 300 ppm/° C., when heat is applied. In the expansion of the resin film, the multilayer laminated circuit substrate is deformed, and stress is applied to the metal circuit in the through hole, which is liable to cause breakage in the metal circuit, which is not preferable. Here, in the present invention, the coefficient of thermal expansion is a coefficient of thermal expansion in a direction perpendicular to the width direction of the resin film (i.e., in the longitudinal direction). Further, in the portion where the multilayer laminated circuit board is easily deformed, it is preferable to use a resin film having a large thermal expansion coefficient, and it is preferable to increase the thickness of the resin film. Further, in the resin film included in the multilayer laminated circuit board of the present invention, it is preferable that the thermal expansion coefficient of the resin film of any one layer is different from the thermal expansion coefficient of at least one other resin film. Thus, -18-201014476, by using a thermal expansion coefficient different from that of other resin films at at least one layer of the resin film, can be applied between the resin films and the heat source. Since the difference in expansion caused by the distance is moderated, it is possible to suppress the disconnection of the metal circuit in the through hole. <Usage Pattern of Multilayer Laminated Circuit Board> The multilayer laminated circuit board of the present invention can be used, for example, as shown in Fig. 3, as the following general configuration: the most multilayer laminated circuit board The lower metal circuit 50 and the hard substrate 301 are bonded together by the metal 401, and the uppermost metal circuit 50 of the multilayer laminated circuit substrate and the Si substrate 302 are bonded together by the adhesion metal 402. In this case, it is preferable that the metal 401 and the adhesion metal 403 are formed by soldering. However, the adhesion metal 402 is not limited to being formed by soldering, but may be soldered. (bonding) is formed either by a combination of stud pins and solder bumps. Further, a hard substrate or a copper substrate may be used for the Si substrate 302, and a Si substrate or a copper substrate may be used for the hard substrate 301. Further, from the viewpoint of preventing the cutting of the heat when the heat is applied, the cross section of the metal 401 and the adhesion metal 402 is preferably 2 mm 2 or less. In the case of using the multilayer laminated circuit substrate, the thermal conductivity coefficient of the uppermost Si substrate 3 0 2 ' is small, and the thermal conductivity coefficient of the lowermost hard substrate 310 ' is large. The thermal expansion coefficient of the resin film laminated between the two is such that the smaller the thermal expansion coefficient of the -19-201014476 resin film on the side of the S i substrate 3 0 2 side, the more the hard substrate 3 0 1 side It is preferable to select a resin film in such a manner that the coefficient of thermal expansion of the resin film is larger. More specifically, the thermal expansion coefficient of the resin film laminated on the Si substrate 302 is preferably 2 Ppm/° C. or more and 10 Ppm/t: or less, and is preferably 3 ppm/° C. or more and 5 ppm/° C. or less. More ideal. If the coefficient of thermal expansion is smaller than 2 ppm/° C., the multilayer laminated circuit board becomes excessively fragile and the processing becomes difficult, so that it is not preferable, and if the coefficient of thermal expansion becomes larger than 10 ppm/° C., The difference between the thermal expansion coefficient of the Si substrate 312 and the thermal expansion coefficient of the resin film is excessively large, and the multilayer laminated circuit substrate is deformed, and it is easy to cause breakage at the metal circuit in the through-hole, which is not preferable. . Further, the resin film laminated on the hard substrate 301 is preferably a material having a thermal expansion coefficient close to that of the hard substrate 301. Further, when the hard substrate is bent, it is preferable to use a resin film which can correspond to the bending. Further, when a copper substrate is used in either or both of the Si substrate or the hard substrate, the resin film laminated in the vicinity of the copper substrate is close to the thermal expansion coefficient. The material of the copper substrate has a thermal expansion coefficient (16.8 Ppm/t), and the enthalpy is preferably 1 〇 ppm/° C. or more and 20 ppm/t or less, and 15 ppm/° C. or more and 18 ppm/° C. or less. ideal. <Component or product> -20- 201014476 The multilayer laminated circuit substrate of the present invention is used in a general member or article. Examples of the product include an electric product, an electronic product, a semiconductor product, an antenna circuit board, a 1C card, a solar battery, a car, or a robot. <Manufacturing Method of Multilayer Laminated Circuit Board> In the production of the multilayer laminated circuit board of the present invention, first, two or more conduction paths are formed in the respective porous conductive portions of the resin Φ film 100. The through hole 120 is then formed to cover the entire surface of the resin film 100 (including the inner wall surface of the through hole) to form the base layer 130, and the plating layer 140 is formed thereon by electroplating. Then, the base layer 130 and one portion of the plating layer 140 are partially removed to form a metal circuit 50, and the additional resin film 1 is attached via the adhesive resin 70. Next, two or more through-holes are formed at the position of the porous conductive portion of the resin film 100 which is newly attached, and then, a metal circuit is formed in the same manner as described above. The multilayer laminated circuit board of the present invention is produced by continuously repeating the resin film of a long shape by the above operation. As described above, if the metal circuit 50 is formed by a plating layer formed by electroplating, it is difficult to cause disconnection in the metal circuit in the through-hole, and even if the resin film is multilayered, the cost can be reduced. The rise is suppressed, so it is ideal. Further, the metal circuit 50 of the multilayer laminated circuit board 1 of the present invention can be formed, for example, by the method of any one of -21 - 201014476 by a hungry method and a semi-additive method. The etching method is performed on the inner wall surface of the through hole of the resin film to form a method in which plating is performed on the plating layer and the underlying layer by etching to form a metal circuit. On the other hand, the semi-additive method is to cover the inner wall surface of the resin film through-hole and does not become a partial spacer of the circuit, and then, after forming the necessary plating layer by electroplating, it will block The agent is peeled off to form a metal circuit. The following is a method for forming a metal circuit, and a method for manufacturing a multilayer laminated circuit substrate by a half example is a method of forming a through-hole forming process and a base layer forming agent. The exposure engineering, the development engineering, the active chemical formation engineering, the barrier stripping engineering, the soft etching engineering, and the product engineering are carried out in the above-described order, and the method of manufacturing the circuit substrate is thereby performed. In the following, the conductive through hole forming process is first described. First, in the resin film 100, three conductive vias 120 are formed by forming a porous conductive member (Fig. 4). In this case, it is sufficient to adjust the depth of the through-hole and the thickness of the resin film to adjust the formation of the through-hole. However, from the viewpoint of being able to form a small diameter and at a low cost, Ideal for use with UV-YAG lasers. The surface (including the layer, and then, removed, the surface (including the conduction, the method of electricity by the thickness of the resistance. The addition method is used as an explanation. The process, the barrier, the plating resin film layer is multi-layered The method of the through portion is as follows: 201014476 <Base layer formation process> which can use any of the through holes in an equal manner. Next, the surface of the resin film 100 (including the inner wall surface of the through hole) is prepared by an ion gun. After the treatment, an oxidation preventing layer is formed on the surface of the resin film 100 (including the inner wall surface of the via hole), and the underlying metal layer is further formed on the oxidation preventing layer, whereby the base layer 130 can be formed (Fig. 5) The oxidation preventing layer and the underlying metal layer included in the underlying layer 130 may be formed, for example, by electroless plating, evaporation, φ sputtering, etc. Further, the oxidation preventing layer or the underlying metal layer, There is also a case in which one or both of them are not formed. <Resistant forming process> The base layer formed on the resin film 100 through the above-described process The surface of 130 is washed with an acid and the surface of the underlying metal layer contained in the underlayer 130 is activated, and then a barrier agent (not shown) is formed. The barrier agent can be attached by means of a paste. The barrier agent is formed by thin filming a dry film of Φ, and can also be formed by coating a barrier ink. The advantage of the method of bonding a dry film is that it is suitable for small production. Therefore, it is possible to correspond to a variety of products, and the engineering of the bonding industry is not complicated, but it has a problem that the manufacturing cost becomes high. On the other hand, the method of coating the barrier ink The advantage is that since it is suitable for mass production, it is possible to reduce the manufacturing cost, but it is a problem that the coating process is complicated. The following is a barrier to the method of laminating a dry film by -23-201014476. First, the resin film 100 on which the base layer 130 is formed as shown in FIG. 5 is mounted on the feed shaft of the laminate winding device, and the resin film 100 is placed before The end is attached to the winding shaft, and the dry film is attached to the base layer 130 of the resin film 100, and the winding shaft is rotated to be wound. Thus, the dry film is attached to the resin film. 100, and a barrier agent (not shown) is formed on the base layer of the resin film. The temperature at the time of lamination is 30 to 15 (TC is ideal, and 60 to 110 °) Further, the pressure at the time of lamination is preferably 0.3 to 5 kg / cm 2 and more preferably 2 to 3 kg / cm 2 , and the wire speed at the time of winding the laminated resin film. It is preferably 0.1 to 1 μm/min, and more preferably 0.5 to 3 m / min. <Exposure Engineering> Next, on the resin film on which the barrier agent is formed by the above-mentioned work, the metal is superposed and desired. The pattern of the circuit corresponds to the mask, after which, © UV exposure, and the portion not covered by the mask is exposed. Here, the portion covered by the mask is removed in the subsequent development process, and a metal circuit is formed by forming a plating layer in a plating layer forming process to be described later. For the exposure apparatus used in this exposure, a parallel light exposure apparatus or a direct exposure apparatus can be used. However, from the viewpoint of forming a fine circuit, it is preferable to use a parallel light exposure device, and from the viewpoint of being able to adjust the position of the exposure corresponding to the shrinkage of the resin film, the system uses -24-201014476 to use direct exposure. The device is ideal. <Photographic Engineering> Next, a portion of the barrier agent covered by the mask of the above exposure project was imaged by a weakly alkaline solution. Thereby, the resin film 100 in which the barrier agent 170 is formed as shown in Fig. 6 can be obtained. The weakly alkaline solution used in the development is preferably a material using a soda carbonate or a φ amine. Further, the ρ 弱 of the weakly alkaline solution is preferably 7 or more and 1 3 or less, and more preferably 8.5 or more and 1 0.0 or less. If the pH of the weakly alkaline solution is smaller than 7, the barrier agent is not removed, so it is not ideal, and if Ph is higher than 13, it is not masked in the above exposure project. The portion of the barrier agent 170 that is covered is also completely peeled off, which is not desirable. Further, the temperature of the weakly alkaline solution is preferably 10 to 70 ° C, and more preferably 20 to 35 ° C. If the temperature of the weakly alkaline solution is lower than l〇°C, then the barrier agent 70 is not removed, so it is not ideal, and if the temperature of the weakly alkaline solution is higher than 70 °C. Then, the barrier agent 1 70 which is partially exposed to UV light is also peeled off, which is not preferable. In addition, although the time of development differs depending on the type of the barrier agent, it is not always specified. However, it is usually preferably 20 seconds or more and 300 seconds or less. <Activation Process> Next, the surface of the underlayer 130 (the base metal layer of the base - 25 - 201014476) on the resin film 100 after development was activated by an acid solution. Thereby, it is possible to prevent adhesion defects between the plating layer and the underlying layer (base metal layer). The acid-based solution to be used for the activation may be any one as long as it exhibits acidity. However, from the viewpoint of being able to be activated at low cost, HC1 and H2S04 are used. Further, ammonium persulfate or the like is preferable, and the concentration of the acid contained in the acid solution is preferably 0.5 to 20% by mass, more preferably 3 to 10% by mass. If the concentration of the acid solution is lower than 0.5% by mass, the surface layer of the underlayer (base metal layer) is difficult to be activated, which is not preferable, and if the concentration of the acid solution is 20% by mass or more Higher is not preferable because of an abnormality in the surface of the underlying layer (base metal layer). Further, the temperature of the acid-based solution at the time of activation is preferably 10 to 70 ° C, and more preferably 30 to 50 ° C. If the temperature of the acid-based solution is lower than 10 °C, it will take too much time to activate the underlayer, which is not desirable, and if the temperature of the acid-based solution is set to 70 °. C is higher, which is not ideal because it causes problems on the environment. In addition, since the processing time differs depending on the surface state of the underlying layer (base metal layer), it cannot be uniformly defined, but 'normally, it is set to be about 3 seconds or more and 300 seconds or less. ideal. <Electroplating layer forming process> Next, a general plating layer 140 as shown in Fig. 7 was formed by performing electro-ammonium on the underlayer 130 activated by the above-described work. -26- 201014476 The plating solution used in the electroplating may be any solution as long as it is an acidic solution containing a metal forming a plating layer. However, the electroplating liquid itself is stable and can be low. From the viewpoint of costing electroplating, it is desirable to use copper sulfate, copper pyrophosphate or the like. Further, when copper sulfate is used in the plating solution, the concentration of copper sulfate is preferably 30 to 300 g/1, and more preferably 70 to 150 g/l. Further, the chlorine ion concentration of the plating solution is preferably 10 to 100 ppm, and more preferably 40 to 70 ppm. Further, as the acidic solution used in the plating solution, it is desirable to use sulfuric acid. When sulfuric acid is used, the concentration of sulfuric acid is preferably 50 to 300 g/l, and more preferably 80 to 200 g/l. ideal. Further, the current density at the time of electroplating is preferably 0.1 to 10 A/dm 2 and more preferably 0.5 to 4 A/dm 2 . Further, the temperature of the plating solution at the time of electroplating is preferably 20 to 60 ° C, and is preferably 30 to 40. (: It is more desirable. The plating time varies depending on the thickness φ of the plating layer. Therefore, it cannot be uniformly defined. However, it is usually set to 600 seconds or more and 6000 seconds or less. The left and right are ideal. <Resistant stripping process> Next, after the metal circuit is formed by the above electroplating process, the alkaline solution is used to peel off the barrier agent. The alkaline solution used in the peeling of the barrier agent, As long as it exhibits an alkaline solution, it may be any one, but from the viewpoint of the stability of the alkaline liquid itself or the cost of the alkaline liquid, sodium hydroxide or alcohol is used. -27- 201014476 In addition, when sodium hydroxide is used in an alkaline liquid, the concentration of sodium hydroxide is preferably 0.1 to 50% by mass, and more preferably 1 to 10% by mass. Further, the temperature of the alkaline liquid used in the peeling of the barrier agent is preferably 30 to 90 ° C, and more preferably 50 to 70 ° C. Further, the time during which the barrier agent is peeled off depends on The peeling state of the barrier agent does not Therefore, it is not always possible to make a rule. However, it is usually preferably about 20 seconds or more and 120 seconds or less. <Soft Etching Process> Next, the underlayer 130 is peeled off by soft etching to obtain A resin film which is generally formed with a metal circuit 50 as shown in Fig. 8. Any drug used in the peeling of the underlying metal layer contained in the underlayer may be used, but from a low cost In view of the above, it is preferable to use ammonium persulfate. When the ammonium persulfate is used, the concentration of ammonium persulfate is preferably 1 to 20%, and more preferably 5 to 10%. The processing temperature at the time of soft engraving of the underlying metal layer is preferably 20 to 60 ° C and more preferably 30 to 40 ° C. In addition, the time spent in the peeling of the soft etching is due to Depending on the thickness of the base metal layer or the concentration of the drug, it is not uniform. However, it is usually 30 seconds or more and 200 seconds or less. Prevent stripping The drug used is ideally based on the use of nickel-chromium stripping solution (trade name: NC (Nippon Chemical Industry Co., Ltd., Ltd.)). Also, when using this drug, the concentration of the drug, It is preferably 60 to 100%. If the concentration of the drug is lower than 60%, the peeling time is consumed, which is not preferable. Further, the processing temperature at the time of soft etching the oxidation preventing layer is 3 5 It is desirable to use ~5 5 ° C. In addition, the time taken for the peeling of the soft etching differs depending on the thickness of the oxidation preventing layer or the concentration of the drug, and therefore cannot be uniformly prescribed. However, it is preferable that the φ is set to be 20 seconds or more and 300 seconds or less. <Resin film lamination process> Next, as a circuit-attached resin film obtained as described above (formed with a metal circuit) A method of laminating another resin film on one surface or both sides of the front and back surfaces of the resin film is to laminate the resin film to which the adhesive resin 70 is attached by lamination a method of coating one side of a resin film of a circuit, and coating a contact resin 7 with a metal circuit forming surface of a resin film with a circuit, and laminating a resin film on which a metal circuit is not formed. As a method of bonding or the like, the resin film can be laminated as shown in Fig. 9 regardless of the method. In addition, when the thickness of the metal circuit is thick by the method of laminating the resin film of the latter, the surface unevenness of the resin film by the metal circuit can be reduced, and therefore, the bonding can be further improved. The advantage of strength. Further, the temperature at which the other resin film 100 is laminated on one or both sides of the front and back sides of the above-mentioned circuit-attached resin film is preferably 30 to 300 ° C, and is preferably in the layer. The pressure applied during the accumulation is preferably 0.1 to 20 kg/cm2. Further, the time required for the lamination of the resin film is preferably 1 second or longer and 3 hours or shorter. Then, the through-hole forming process is performed, and thus, the multilayer laminated circuit board of the present invention as shown in Fig. 1 can be manufactured by repeating the above-described various processes. Hereinafter, the present invention will be described in more detail by way of examples, but the present invention is not limited to the examples. [Embodiment 1] In the first embodiment, as a method of forming a metal circuit, an etching method was used, and a multilayer laminated circuit substrate (conducting via hole forming process) was produced by the following various processes. As the resin film 100 used in the multilayer laminated circuit board, a long-sized polyimide film (length 50 m, thickness 38 μm, trade name: KAPTON EN150 (TORAY. DuPont) which is wound into a cylindrical shape is used. Co., Ltd.) The resin film has a thermal expansion coefficient of 16 ppm/°C or more and 17 ppm/°C or less, and is used for a slit process with a width of 250 mm. This resin film 100 is mounted on UV-YAG. On the laser device, the UV-YAG laser device is programmed to form holes 120 with an inner diameter of μ5μπι at three locations for the 1 to 30-201014476 porous conductive portions (Fig. 4). [Net Engineering] The resin 1 which is formed by the above-mentioned process to form the through-holes 120 is mounted on the cleaning device, and the resin film 100 is used for suppressing the generation of pinholes in the formation of the underlying layer. The surface is clean. Underlayer forming process> Next, the surface of the resin which has been washed by the above-mentioned work is put into a sputtering apparatus, and a pressure of 3 Pa is set by a vacuum pump, and then Ν2 gas is injected into the ion. In the gun, the surface of the resin film is prepared by irradiation with a gun, and an alloy of Ni and Cr is formed on the resin film by a sputtering method in an Ar gas atmosphere (Ni and Cr). The weight ratio is an oxidation preventing layer formed of Ni: Cr = 20), and a metal layer made of Cu is formed thereon, whereby the underlying layer 130 is formed (Fig. 5). The vacuum state of the ammonium device is released, and the resin film 100 formed of the underlayer 130 is taken out, and the portion of the resin film 100 is sampled. Then, by irradiating the sample with the focused ion FIB: Focused Ion Beam, the profile is made. Observed. The relationship was confirmed to be that the thickness of the oxidation preventing layer was 1 and the thickness of the underlying gold was 305 nm. Further, it was confirmed that the through-hole 120 was passed through the film engineering and washed.
薄膜 χ10· 離子 後， 成由 80 ： 基底 了基 之一 束（ 果， 屬層 內， -31 - 201014476 亦係被形成有此些之基底層130。 〈電鍍層形成工程〉 接著，將被形成了基底層之樹脂薄膜100安裝在銅電 鍍裝置中，並在藉由硫酸而將基底層活性化後，進行了水 洗。而後，藉由將該當樹脂薄膜，浸漬在將電鍍液（由硫 酸200g/卜硫酸銅90g/l、氯離子濃度5 00ppm所成者 )作了塡充之電鍍浴中，而在基底層130上進行銅電鍍， 並再度作水洗而使其乾燥，而在樹脂薄膜100之表面上， 形成了電鍍層1 40 (圖1 0 )。對於如此這般所得到了的樹 脂薄膜之一部分進行了取樣。而後，藉由對於該樣本照射 FIB，而對剖面作了觀察，其結果，包含基底層130與電 鍍層140之合計的厚度，係爲18.5#m。 〈金屬電路形成工程〉 接著，對於如同上述一般而形成了電鍍層140之樹脂 薄膜的表背兩面，層壓被作了 250mm寬幅之細縫加工的 乾薄膜（商品名：NIT215 ( Nichigo-Morton股份有限公司 製）），並將金屬電路之圖案的遮罩作重合，而後，將其 安裝於滾筒式之曝光裝置中，並進行了曝光。 而後，將樹脂薄膜100安裝在能夠將顯像與蝕刻以及 阻隔劑剝離連續性進行之滾筒式的蝕刻裝置中，並進行蝕 刻處理，而形成了金屬電路50 (圖8 )。對此樹脂薄膜作 取樣，並以100倍之倍率的顯微鏡來進行了金屬電路50 -32- 201014476 之斷線、短路等的檢查。其結果，如圖8中所示一般，在 金屬電路50中係並未被觀察到有斷線、短路等之不良。 〈樹脂薄膜層積工程〉 接著’在如同上述一般而形成了金屬電路之樹脂薄膜 100的表背兩面處，貼附被塗布有接著性樹脂7〇之厚度 3 8 ^ m的聚醯亞胺薄膜（KAPTON EN150(TORAY·杜邦 φ 股份有限公司製）），而得到了由3層之樹脂薄膜100與 2層之電路層2 00所成的層積體（圖9)。 對於此層積體之上下的樹脂薄膜100之全面，使用5 倍之擴大鏡而進行了縐折、空氣侵入等之檢查。其結果， 在此層積體之上下的樹脂薄膜處，係並未被觀察到有綴折 、空氣侵入等之不良。 〈導通貫孔形成工程-2〉 φ 接著，藉由使用與上述之導通貫孔形成工程相同之方 法，而對於藉由上述工程所得到了的層積體之上下的樹脂 薄膜1〇〇，來在各多孔導通部處而形成3個的導通貫孔 120(圖11)。而後，將藉由上述工程而被形成了導通貫 孔之層積體的上述之樹脂薄膜100的表面作洗淨。 〈基底層形成工程-2〉 接著，將藉由上述工程所得到之層積體安裝在濺鍍裝 置中，並藉由與上述之基底層形成工程相同之條件以及方 -33- 201014476 法，而在此層積體之上下的樹脂薄膜100之表面上，藉由 濺鍍法而形成包含有由CNi-Cr所成之氧化防止層和由Cu 所成之基底金屬層的基底層130(圖12)。 而後，對於上述之被形成了基底層的層積體之一部分 作了取樣。而後，藉由對於該樣本照射FIB，而對剖面作 了觀察。其結果，係確認了：氧化防止層之厚度係爲 10nm，而基底金屬層厚度係爲3 50nm。 〈電鍍層形成工程-2〉 接著，將藉由上述工程所得到的被形成有基底層之層 積體安裝在Cu電鍍裝置中，並藉由與上述之電鍍層形成 工程相同之條件，而在上述所形成之基底層的全面上形成 了電鍍層140 (圖13)。而後，對於此層積體之一部分作 取樣並照射FIB，而對剖面作了觀察。其結果，此層積體 之上下的樹脂薄膜100上之電鍍層140與基底層130的合 計厚度，係均爲1 8.5 e m。 〈金屬電路形成工程-2〉 接著’對於以上述工程所得到的形成了電鍍層之層積 體的上下樹脂薄膜1〇〇，而層壓乾薄膜（商品名：NIT215 (Nichigo-Morton股份有限公司製）），而後，將其安裝 於滾筒式之曝光裝置中，並進行了曝光。 而後，將顯像與蝕刻以及阻隔劑剝離連續地進行，並 在此層積體之上下的樹脂薄膜100之表面上形成了金屬電 201014476 路50(圖1)。藉由以上，而製作了本發明之多層 路基板。 而後，對此多層層積電路基板作取樣’並對於 而使用100倍之倍率的顯微鏡來進行了金屬電路之 短路等的檢查。其結果，在此多層層積電路基板之 路中，係並未被觀察到有斷線、短路等之不良° φ 〈實施例2〜1 2〉 實施例2〜12之多層層積電路基板’相對於實 之多層層積電路基板，在1個的多孔導通部處之導 的個數上、以及導通貫孔的內徑上，係如同以下之; 所示一般而爲相異，除此之外’係藉由與實施例1 方法而進行了製作。例如，表1中之實施例3，係 :對於1個的多孔導通部，而形成了 5個的與實施 所形成之導通貫孔相同的導通貫孔’而實施例5 ’ φ 有：對於1個的多孔導通部，而形成了 3個的內徑 之導通貫孔。 〈比較例1〜3〉 比較例1〜3之多層層積電路基板’係並不形 導通部，而對於1個的導通部來形成1個的導通貫 此之外，係藉由與實施例1相同之方法而進行了製 考表1 )。例如，在表1中之比較例1中’係在每 部中各形成1個的內徑15/zni之導通貫孔、比較例 層積電 此樣本 斷線、 金屬電 施例1 通貫孔 良1中 相同的 展示有 例1中 係展示 5 0 // m 成多孔 孔，除 作（參 一導通 2係在 -35- 201014476 每一導通部中各形成1個的內徑5〇ym之導通貫孔、比較 例3係在每一導通部中各形成1個的內徑300ym之導通 貫孔。 〔表1〕 導通貫孔之內徑 (/m) 在多孔導通部（導通部）中所包含 之導通貫孔的個數（個） 實施例1 15 3 實施例2 15 2 實施例3 15 5 實施例4 15 7 實施例5 50 3 實施例ό 50 2 實施例7 50 5 實施例8 50 7 實施例9 300 3 實施例10 300 2 實施例11 300 5 實施例Π 300 7 比較例1 15 1 比較例2 50 1 比較例3 300 1After the film χ10· ions, a layer of 80: substrate is formed (in the genus layer, -31 - 201014476 is also formed with such a base layer 130. <Electroplating layer formation engineering> Next, it will be formed The resin film 100 of the underlayer is mounted in a copper plating apparatus, and after the base layer is activated by sulfuric acid, it is washed with water. Then, the resin film is immersed in a plating solution (from a sulfuric acid 200 g/ Copper sulphate 90 g / l, chloride ion concentration of 500 00 ppm) in the plating bath, and copper plating on the base layer 130, and again washed with water to dry, and in the resin film 100 On the surface, a plating layer 140 (Fig. 10) was formed. One portion of the resin film thus obtained was sampled. Then, the profile was observed by irradiating the sample with FIB, and as a result, The total thickness of the base layer 130 and the plating layer 140 is 18.5 #m. <Metal circuit formation process> Next, for the front and back sides of the resin film on which the plating layer 140 is formed as described above, lamination is performed. A dry film of a 250 mm wide slit (trade name: NIT215 (manufactured by Nichigo-Morton Co., Ltd.)), and a mask of a pattern of a metal circuit is superposed, and then mounted in a drum type exposure apparatus Then, the resin film 100 is mounted in a drum type etching apparatus capable of performing development and etching and peeling continuity of the barrier agent, and etching treatment is performed to form the metal circuit 50 (FIG. 8). The resin film was sampled, and the metal circuit 50-32-201014476 was inspected for disconnection, short circuit, etc. at a magnification of 100 times. As a result, as shown in Fig. 8, generally, in the metal circuit 50. In the middle, the defects such as the disconnection and the short circuit are not observed. <Resin film deposition engineering> Next, at the front and back sides of the resin film 100 in which the metal circuit is formed as described above, the adhesion is applied and then A resin film having a thickness of 3 8 μm of 3 8 μm (KAPTON EN150 (manufactured by TORAY·DuPont φ Co., Ltd.)) was obtained, and a resin layer of three layers of resin film 100 and two layers was obtained. A laminate of 00 (Fig. 9). The entire resin film 100 above and below the laminate is inspected with a 5x magnification mirror and collapsed, air intrusion, etc. In the resin film above and below the laminate, defects such as gusseting and air intrusion were not observed. <Conduction through hole forming process-2> φ Next, by using the same method as the above-mentioned through hole forming process In the method, the resin film 1 之上 above and below the laminate obtained by the above-described process is used to form three through-holes 120 in each of the porous conductive portions (FIG. 11). Then, the surface of the above-mentioned resin film 100 in which the laminate of the through-holes is formed by the above-described process is washed. <Base layer forming process-2> Next, the layered body obtained by the above-mentioned work is mounted in a sputtering apparatus, and the same conditions as those of the above-mentioned underlying layer are formed, and the method is -33-201014476 On the surface of the resin film 100 above the laminate, a base layer 130 containing an oxidation preventing layer made of CNi-Cr and a base metal layer made of Cu is formed by sputtering (Fig. 12) ). Then, a part of the above-mentioned laminated body in which the underlayer was formed was sampled. Then, the cross section was observed by irradiating the sample with the FIB. As a result, it was confirmed that the thickness of the oxidation preventing layer was 10 nm, and the thickness of the underlying metal layer was 3 50 nm. <Electroplating layer forming process-2> Next, the layered body on which the underlying layer obtained by the above-mentioned engineering is formed is mounted in a Cu plating apparatus, and is formed under the same conditions as the above-described plating layer forming process. The plating layer 140 (Fig. 13) is formed over the entire underlying substrate layer. Then, a portion of this laminate was sampled and irradiated with FIB, and the profile was observed. As a result, the total thickness of the plating layer 140 and the base layer 130 on the resin film 100 above the laminate was 1 8.5 e m. <Metal Circuit Formation Engineering-2> Next, the upper and lower resin films of the laminated body in which the plating layer was obtained by the above-mentioned work were laminated, and the dry film was laminated (trade name: NIT215 (Nichigo-Morton Co., Ltd.) Then), it was mounted in a drum type exposure apparatus and exposed. Then, development and etching and peeling of the barrier are continuously performed, and metal electric power 201014476 is formed on the surface of the resin film 100 above the laminate (Fig. 1). From the above, the multilayer substrate of the present invention was produced. Then, the multilayer laminated circuit substrate was sampled', and a short circuit of the metal circuit or the like was inspected using a microscope having a magnification of 100 times. As a result, in the path of the multilayer laminated circuit board, no defects such as disconnection or short-circuit were observed. φ <Examples 2 to 1 2> Multilayer laminated circuit substrates of Examples 2 to 12 With respect to the actual multilayer laminated circuit substrate, the number of leads at one porous conductive portion and the inner diameter of the conductive through hole are as follows; generally shown to be different, except The exterior was produced by the method of Example 1. For example, in the third embodiment in Table 1, five conductive vias are formed for one porous via portion and that are the same as the through vias formed. The embodiment 5 'φ has: for 1 Each of the porous conductive portions forms three through-holes of the inner diameter. <Comparative Examples 1 to 3> The multilayer laminated circuit board of Comparative Examples 1 to 3 does not have a conductive portion, and one conductive portion is formed for one conductive portion, and is the same as the embodiment. 1 The same method was used to make the test table 1). For example, in Comparative Example 1 in Table 1, a through-hole of an inner diameter of 15/zni is formed in each of the sections, a comparative example is laminated, and the sample is broken, and the metallurgical embodiment 1 is passed through the hole. The same display in the case of the first one shows that the example shows that the 50 0 / m m is a porous hole, except that (the one of the conduction lines 2 is formed in each of the conduction portions of -35-201014476, and the inner diameter is 5 〇 ym. The through hole and the comparative example 3 each formed one through hole having an inner diameter of 300 μm in each of the conduction portions. [Table 1] The inner diameter (/m) of the through hole was in the porous conduction portion (conduction portion). Number of conductive vias included (Example 1) 15 3 Example 2 15 2 Example 3 15 5 Example 4 15 7 Example 5 50 3 Example ό 50 2 Example 7 50 5 Example 8 50 7 Example 9 300 3 Example 10 300 2 Example 11 300 5 Example Π 300 7 Comparative Example 1 15 1 Comparative Example 2 50 1 Comparative Example 3 300 1
〈導通檢查〉 對於實施例1〜12以及比較例1〜3之多層層積電路 基板，使用LCR計（型號：NDH-2000 ( CUSTOM股份有 限公司製）），而進行了多層層積電路基板之端子兩端處 的導通檢查。其結果，在實施例1〜12以及比較例1〜3 之任一的多層層積電路基板中，係均未被觀察到導通之異 -36- 201014476 常。 . 實施例1〜12以及比較例1〜3之多層層積電路基板 的金屬電路，係被設置有約200個的多孔導通部（在比較 例中，係爲導通部），但是，由於只要在該些之多孔導通 部（在比較例中，係爲導通部）中的1個場所處而產生有 斷線，便會被計測到導通之異常，因此，明顯的，在製作 了多層層積電路基板的階段時，金屬電路係並未斷線。 〈溫度變化循環試驗〉 對於實施例1〜12以及比較例1〜3之多層層積電路 基板’使用循環試驗機（型號：TSA-41L-ACESPEC股份 有限公司製）），而進行了將2個的相異之設定溫度以一 定的時間間隔來交互反覆保持的溫度變化循環試驗。具體 而言，係在-40°C下保持30分鐘，之後，在120。(：下保持 3〇分鐘’並將此作爲1個循環，而在每進行了 500循環時 Φ ’進行了導通檢查。在被包含於電路內的複數之多孔導通 部中，只要在1個場所有產生導通不良，便在該時間點而 結束循環試驗’並將試驗一直進行到了 3 000循環。 實施例1〜12之多層層積電路基板，係就算在3000 循環結束時，亦並未被發現到有導通不良。相對於此，比 較例1之多層層積電路基板，係在20 00循環結束時確認 到導通不良，比較例2之多層層積電路基板，係在1500 循環結束時確認到導通不良’比較例3之多層層積電路基 板，係在1 000循環結束時確認到導通不良。 -37- 201014476 由以上結果，可明顯得知，實施例1〜1 2之多層層積 電路基板，相較於比較例1〜3之多層層積電路基板，在 被施加有熱時之金屬電路的斷線，係非常難以產生。明顯 的，其原因係因爲在實施例1〜12之多層層積電路基板中 設置了多孔導通部所致者。 如上述一般，而針對本發明之實施型態以及實施例來 作了說明，但是，將上述之實施型態以及實施例之構成作 適宜組合一事，係在初始時即已有所預定。 在此處所揭示之實施型態以及實施例，係全部爲例示 ，而並不應將其考慮爲對於本發明作限制者。本發明，係 並非藉由上述之說明而被限制，而係藉由申請專利範圍而 被展示，且係包含有在與申請專利範圍均等之意義以及範 圍內的所有之變更。 〔產業上之利用可能性〕 若藉由本發明，則能夠提供一種難以產生金屬電路之 斷線的多層層積電路基板。 【圖式簡單說明】 〔圖1〕對於本發明之多層層積電路基板的其中一例 作展示之模式性剖面圖。 〔圖2〕圖1之多孔導通部的從上面視之的擴大平面 圖。 〔圖3〕對於本發明之多層層積電路基板的使用型態 -38- 201014476 之其中一例作展示的模式性剖面圖。 〔圖4〕對於形成了多孔導通部後之樹脂薄膜作展示 的模式性剖面圖。 〔圖5〕對於形成了基底層後之樹脂薄膜作展示的模 式性剖面圖。 〔圖6〕對於將光阻劑作了顯像後之樹脂薄膜作展示 的模式性剖面圖。 I 〔圖7〕對於形成了電鍍層後之樹脂薄膜作展示的模 式性剖面圖。 〔圖8〕對於進行了軟鈾刻後之樹脂薄膜作展示的模 式性剖面圖。 〔圖9〕對於在形成了金屬電路之樹脂薄膜的表、背 兩面處而進而層積了樹脂薄膜的狀態作展示之模式性剖面 圖。 〔圖10〕對於在基底層上形成了電鍍層後之樹脂薄膜 φ 作展示的模式性剖面圖。 〔圖11〕對於在將樹脂薄膜作了 3層層積的層積體之 上下面處形成了導通貫孔後之狀態作展示的模式性剖面圖 〇 〔圖12〕對於在將樹脂薄膜作了 3層層積的層積體之 上下面處形成了基底層後之狀態作展示的模式性剖面圖。 〔圖13〕對於在將樹脂薄膜作了 3層層積的層積體之 上下面處形成了電鍍層後之狀態作展示的模式性剖面圖。 -39- 201014476 【主要元件符號說明】 1:多層層積電路基板 5 0 :金屬電路 70 :接著性樹脂 100 :樹脂薄膜 1 1 〇 :多孔導通部 1 2 0 :導通貫孔 130 :基底層 140 :電鍍層 1 7 0 :阻隔劑 200 :電路層 3 0 1 :硬基板 302 : Si基板 401 :接著金屬 402 :密著金屬<Conductivity inspection> The multilayer laminated circuit board of the examples 1 to 12 and the comparative examples 1 to 3 was subjected to a multilayer laminated circuit board using an LCR meter (model: NDH-2000 (manufactured by CUSTOM Co., Ltd.)). Conduction check at both ends of the terminal. As a result, in the multilayer laminated circuit boards of any of Examples 1 to 12 and Comparative Examples 1 to 3, the conduction was not observed to be constant - 36 - 201014476. The metal circuits of the multilayer laminated circuit boards of Examples 1 to 12 and Comparative Examples 1 to 3 are provided with about 200 porous conductive portions (in the comparative example, the conductive portions), but In some of the porous conductive portions (in the comparative example, the conductive portions), a disconnection occurs, and an abnormality in conduction is measured. Therefore, it is apparent that a multilayer laminated circuit is fabricated. At the stage of the substrate, the metal circuit is not broken. <Temperature Change Cycle Test> Two layers of the multilayer circuit board of Examples 1 to 12 and Comparative Examples 1 to 3 were subjected to a cycle tester (model: TSA-41L-ACESPEC Co., Ltd.), and two were carried out. The different set temperatures are cyclically tested at a certain time interval to alternately maintain the temperature change. Specifically, it was kept at -40 ° C for 30 minutes, and then at 120 °. (: hold for 3 minutes and use this as one cycle, and Φ ' is checked for conduction every 500 cycles. In the porous conductive portion included in the circuit, as long as it is in one place If there is a poor conduction, the cycle test is terminated at this point of time' and the test is continued until 3 000 cycles. The multilayer laminated circuit substrate of Examples 1 to 12 is not found even at the end of the 3000 cycle. On the other hand, in the multilayer laminated circuit board of Comparative Example 1, the conduction failure was confirmed at the end of the 200 00 cycle, and the multilayer laminated circuit substrate of Comparative Example 2 was confirmed to be turned on at the end of the 1500 cycle. In the multilayer laminated circuit board of Comparative Example 3, the conduction failure was confirmed at the end of the 1 000 cycle. -37- 201014476 From the above results, the multilayer laminated circuit substrate of Examples 1 to 12 was apparent. Compared with the multilayer laminated circuit board of Comparative Examples 1 to 3, the disconnection of the metal circuit when heat is applied is extremely difficult to produce. Obviously, the reason is because of the multilayer layers in Examples 1 to 12. The porous conductive portion is provided in the integrated circuit board. As described above, the embodiment and the embodiment of the present invention have been described. However, the above-described embodiment and the configuration of the embodiment are appropriately combined. The present invention has been described in the prior art. The embodiments and examples disclosed herein are all illustrative and are not to be considered as limiting the invention. The above description is intended to be limited by the scope of the patent application, and all modifications are included within the meaning and scope of the application. Further, it is possible to provide a multilayer laminated circuit board in which it is difficult to generate a broken line of a metal circuit. [Schematic Description] Fig. 1 is a schematic cross-sectional view showing an example of a multilayer laminated circuit board of the present invention. Figure 2 is an enlarged plan view of the porous conducting portion of Figure 1 as viewed from above. [Fig. 3] The use type of the multilayer laminated circuit substrate of the present invention - 38- A model cross-sectional view showing one of the examples of 201014476. [Fig. 4] A schematic cross-sectional view showing a resin film formed by forming a porous conductive portion. [Fig. 5] A display of a resin film after forming a base layer. Modeal cross-sectional view. Fig. 6 is a schematic cross-sectional view showing a resin film on which a photoresist is developed. I [Fig. 7] A schematic cross section showing a resin film formed by plating Fig. 8 is a schematic cross-sectional view showing a resin film after soft uranium engraving. [Fig. 9] A resin film is laminated on the front and back surfaces of a resin film on which a metal circuit is formed. The state of the display is a schematic cross-sectional view. [Fig. 10] A schematic cross-sectional view showing a resin film φ after a plating layer is formed on a base layer. [Fig. 11] A schematic cross-sectional view showing a state in which a through-hole is formed in a lower portion of a laminate in which a resin film is laminated in three layers (Fig. 12) for the resin film A schematic cross-sectional view showing the state after the base layer is formed on the lower layer of the three-layer laminated laminate. [Fig. 13] A schematic cross-sectional view showing a state in which a plating layer is formed on the upper and lower surfaces of a laminate in which three layers of a resin film are laminated. -39- 201014476 [Description of main component symbols] 1: Multi-layer laminated circuit substrate 50: Metal circuit 70: Adhesive resin 100: Resin film 1 1 〇: Porous conduction portion 1 2 0 : Through-hole 130: Base layer 140 : plating layer 170: barrier agent 200: circuit layer 3 0 1 : hard substrate 302: Si substrate 401: followed by metal 402: close metal