TWI460818B - 半導體積體電路基板之絕緣結構及其製造方法 - Google Patents

半導體積體電路基板之絕緣結構及其製造方法 Download PDF

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Publication number
TWI460818B
TWI460818B TW095146069A TW95146069A TWI460818B TW I460818 B TWI460818 B TW I460818B TW 095146069 A TW095146069 A TW 095146069A TW 95146069 A TW95146069 A TW 95146069A TW I460818 B TWI460818 B TW I460818B
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Taiwan
Prior art keywords
trench
forming
layer
dielectric material
substrate
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TW095146069A
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English (en)
Chinese (zh)
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TW200733297A (en
Inventor
Richard K Williams
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Advanced Analogic Tech Inc
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Publication of TW200733297A publication Critical patent/TW200733297A/zh
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Publication of TWI460818B publication Critical patent/TWI460818B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
TW095146069A 2005-12-09 2006-12-08 半導體積體電路基板之絕緣結構及其製造方法 TWI460818B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/298,075 US20070132056A1 (en) 2005-12-09 2005-12-09 Isolation structures for semiconductor integrated circuit substrates and methods of forming the same

Publications (2)

Publication Number Publication Date
TW200733297A TW200733297A (en) 2007-09-01
TWI460818B true TWI460818B (zh) 2014-11-11

Family

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Family Applications (2)

Application Number Title Priority Date Filing Date
TW103103967A TWI544573B (zh) 2005-12-09 2006-12-08 半導體積體電路基板之絕緣結構及其製造方法
TW095146069A TWI460818B (zh) 2005-12-09 2006-12-08 半導體積體電路基板之絕緣結構及其製造方法

Family Applications Before (1)

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TW103103967A TWI544573B (zh) 2005-12-09 2006-12-08 半導體積體電路基板之絕緣結構及其製造方法

Country Status (7)

Country Link
US (5) US20070132056A1 (enExample)
EP (1) EP1958249A1 (enExample)
JP (4) JP5438973B2 (enExample)
KR (4) KR20110079861A (enExample)
CN (1) CN101366112B (enExample)
TW (2) TWI544573B (enExample)
WO (1) WO2007070311A1 (enExample)

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US9012300B2 (en) * 2012-10-01 2015-04-21 United Microelectronics Corp. Manufacturing method for a shallow trench isolation
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US20140213034A1 (en) * 2013-01-29 2014-07-31 United Microelectronics Corp. Method for forming isolation structure
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CN109216256B (zh) * 2017-07-03 2021-01-05 无锡华润上华科技有限公司 沟槽隔离结构及其制造方法
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Also Published As

Publication number Publication date
TW200733297A (en) 2007-09-01
KR20110111549A (ko) 2011-10-11
KR20110081909A (ko) 2011-07-14
WO2007070311A1 (en) 2007-06-21
US7994605B2 (en) 2011-08-09
US7923821B2 (en) 2011-04-12
KR20080098481A (ko) 2008-11-10
CN101366112A (zh) 2009-02-11
JP2016164998A (ja) 2016-09-08
KR20110079861A (ko) 2011-07-08
JP6026486B2 (ja) 2016-11-16
US20070132056A1 (en) 2007-06-14
US20100055864A1 (en) 2010-03-04
JP6263569B2 (ja) 2018-01-17
TWI544573B (zh) 2016-08-01
US7955947B2 (en) 2011-06-07
JP5438973B2 (ja) 2014-03-12
US20080203543A1 (en) 2008-08-28
TW201419444A (zh) 2014-05-16
US20080254592A1 (en) 2008-10-16
EP1958249A1 (en) 2008-08-20
JP2013168662A (ja) 2013-08-29
JP2015062239A (ja) 2015-04-02
US7915137B2 (en) 2011-03-29
US20080203520A1 (en) 2008-08-28
JP2009518867A (ja) 2009-05-07
KR101323497B1 (ko) 2013-10-31
CN101366112B (zh) 2011-05-04

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