US20070132056A1 - Isolation structures for semiconductor integrated circuit substrates and methods of forming the same - Google Patents

Isolation structures for semiconductor integrated circuit substrates and methods of forming the same Download PDF

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Publication number
US20070132056A1
US20070132056A1 US11/298,075 US29807505A US2007132056A1 US 20070132056 A1 US20070132056 A1 US 20070132056A1 US 29807505 A US29807505 A US 29807505A US 2007132056 A1 US2007132056 A1 US 2007132056A1
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United States
Prior art keywords
dielectric material
trench
layer
substrate
field oxide
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US11/298,075
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English (en)
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Richard Williams
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Skyworks Solutions Inc
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Advanced Analogic Technologies Inc
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Priority to US11/298,075 priority Critical patent/US20070132056A1/en
Application filed by Advanced Analogic Technologies Inc filed Critical Advanced Analogic Technologies Inc
Assigned to ADVANCED ANALOGIC TECHNOLOGIES, INC. reassignment ADVANCED ANALOGIC TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WILLIAMS, RICHARD K.
Priority to KR1020117014788A priority patent/KR20110079861A/ko
Priority to PCT/US2006/046579 priority patent/WO2007070311A1/en
Priority to JP2008544483A priority patent/JP5438973B2/ja
Priority to EP06844906A priority patent/EP1958249A1/en
Priority to KR1020117022767A priority patent/KR101323497B1/ko
Priority to CN2006800525978A priority patent/CN101366112B/zh
Priority to KR1020087014965A priority patent/KR20080098481A/ko
Priority to KR1020117014787A priority patent/KR20110081909A/ko
Priority to TW095146069A priority patent/TWI460818B/zh
Priority to TW103103967A priority patent/TWI544573B/zh
Publication of US20070132056A1 publication Critical patent/US20070132056A1/en
Priority to US12/150,704 priority patent/US7923821B2/en
Priority to US12/150,609 priority patent/US7955947B2/en
Priority to US12/150,727 priority patent/US7915137B2/en
Priority to US12/150,732 priority patent/US7994605B2/en
Priority to JP2013076644A priority patent/JP2013168662A/ja
Priority to JP2014224436A priority patent/JP6026486B2/ja
Priority to JP2016075672A priority patent/JP6263569B2/ja
Assigned to SKYWORKS SOLUTIONS, INC. reassignment SKYWORKS SOLUTIONS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Definitions

  • This invention relates to semiconductor chip fabrication and in particular to methods of fabricating structures to isolate electrically the active or passive devices formed on a semiconductor chip.
  • isolation structures early in the process because they can also act as barriers or stops to the lateral diffusion of dopants, thereby allowing a more closely packed device population on the surface of the chip.
  • a dielectric-filled trench can function as a diffusion stop as well as an electrical isolation structure.
  • FIGS. 1A-1C This problem is illustrated in FIGS. 1A-1C .
  • a trench 101 has been etched in a semiconductor substrate 100 .
  • trench 101 has been filled with a dielectric material 102 and the top surface has been planarized (e.g., by chemical-mechanical polishing) to form an isolation structure.
  • FIG. 1C shows the isolation structure after further processing, with part of the dielectric material 102 removed or eroded so as to form a recess or gap 103 on the top surface of the structure.
  • Dielectric materials that are resistant to etching in normal semiconductor processes e.g., silicon nitride
  • a second problem stems from the fact that chips are generally divided into two general areas: broad or wide “field” areas and more densely-packed device areas, sometimes referred to as “active” areas. It is preferable to form relatively narrow, deep trenches in the active areas to maintain a tight packing density and to form relatively wide trenches in the field areas to space out the devices over larger distances. This creates a problem in filling the trenches.
  • the narrow trenches may be filled while the wide trenches are difficult to fill.
  • using numerous narrow trenches to cover large distances in the field areas can complicate the topography of the chip.
  • an isolation structure is formed by filling a trench in a semiconductor substrate with a “dielectric fill.”
  • the dielectric fill includes a first dielectric material and a second dielectric material.
  • the first dielectric material is located in a lower portion of the trench; the second dielectric material is located in an upper portion of the trench, the lower portion typically being larger in the vertical dimension than the upper portion.
  • the surface of the second dielectric material is substantially coplanar with a surface of the substrate.
  • the first and second dielectric materials are dissimilar in the sense that the second dielectric material is not etched by a chemical which etches the first dielectric material. Thus in subsequent processing the second dielectric material forms a protective cap over the first dielectric material.
  • the first dielectric material is a relatively soft, low-stress material and the second dielectric material is a relatively hard, etch-resistant material. Cracking problems can be avoided by limiting the thickness of the second dielectric layer to a value that provides protection during later etching processes but does not create stress problems.
  • the trench may be filled with a “graded” dielectric, wherein the proportion of the second dielectric material in the dielectric fill increases gradually as one moves upward towards the mouth of the trench.
  • the sidewalls of the trench may be lined with an oxide layer to prevent dopants from the dielectric fill from migrating into the semiconductor substrate.
  • the first dielectric material is a silicon oxide and silicate glass, either doped or undoped.
  • the second dielectric can be silicon nitride, a polyimide or any dielectric material containing little or no silicon oxide.
  • the substrate may also include the lower portion of a field oxide region, typically formed by a local oxidation of silicon (LOCOS) process.
  • LOC local oxidation of silicon
  • the surface of the field oxide region is also substantially coplanar with the surface of the substrate.
  • a protective cap may be formed over the field oxide.
  • the substrate contains two isolation structures, the first formed in a relatively shallow, wide trench, the second formed in a relatively narrow, deep trench. Both trenches are filled with a dielectric fill and the surface of the dielectric fill is substantially coplanar with the surface of the substrate.
  • a protective cap of the kind described above may be formed at the mouth of each trench.
  • one or more field oxide regions are formed in the same substrate as one or more trench isolation structures.
  • Field doping regions of predetermined conductivity type and doping concentration may be formed under the field oxide regions.
  • protective dielectric caps may be formed where the trenches and field oxide regions meet the plane of the surface of the substrate.
  • the surface of the entire structure is substantially coplanar. The surface mab be planarized by using a chemical etchback, a plasma-enhanced or reactive ion etch (RIE), chemical-mechanical polishing (CMP) or some combination thereof.
  • RIE reactive ion etch
  • CMP chemical-mechanical polishing
  • the invention also includes methods of fabricating isolation structures.
  • One such method includes forming a trench in the semiconductor substrate; depositing a first dielectric material in the trench; removing a portion of the first dielectric material such that a surface of the first dielectric material is located at a first level below a second level of a top surface of the substrate, thereby forming a recess; depositing a second dielectric material in the recess; and removing a portion of the second dielectric material such that a surface of the second dielectric material is substantially coplanar with the surface of the substrate, thereby forming a protective cap in the trench.
  • Another method includes thermally forming a field oxide region at a surface of the semiconductor substrate; forming a trench in the substrate; depositing a first dielectric material in the trench; removing a portion of the first dielectric material such that a surface of the first dielectric material is located at a first level below a second level of the surface of the substrate, thereby forming a recess; depositing a second dielectric material in the recess; and removing portions of the field oxide region and the second dielectric material such that a surface of the field oxide region and a surface of the second dielectric material are substantially coplanar with the surface of the substrate, thereby forming a protective cap in the trench.
  • the methods of this invention are highly flexible and can be used to form isolation regions necessary meet the varying demands of different regions and devices in a semiconductor substrate.
  • the topography of the substrate is maintained extremely flat, or at least sufficiently flat as not to interfere with or complicate the formation of fine line widths and submicron features or the interconnection thereof during subsequent processing.
  • Protective caps can be used to protect the dielectric materials from erosion during subsequent processing.
  • FIGS. 1A-1C illustrate the problem that occurs when the dielectric in a trench which serves as an isolation structure is eroded during later processing.
  • FIGS. 2A-2F illustrate a process for forming an isolation structure that includes a protective cap at the mouth of a dielectric-filled trench.
  • FIGS. 3A-3D illustrate a process for forming a modified version of the isolation structure of FIG. 2F where an oxide layer is formed on the walls of the trench adjacent the protective cap.
  • FIG. 4 illustrates how the oxide layer shown in FIG. 3D may be eroded in subsequent processing.
  • FIG. 5 is a flow chart, in “card” form, of the processes shown in FIGS. 2A-2F and 3 A- 3 D.
  • FIGS. 6A-6C illustrate a process for forming isolation structures that include a broad or wide field oxide region and a relatively narrow dielectric-filled trench.
  • FIGS. 7A-7H illustrate a processing for forming isolation structures which include a wide, shallow trench and a narrow, deep trench.
  • FIGS. 8A-8J illustrate another process for forming isolation structures that include a broad or wide field oxide region and a relatively narrow dielectric-filled trench, with a protective cap formed at the top of each structure.
  • FIGS. 9A-9E illustrate a process for forming isolation structures that include a pair of field oxide regions and a dielectric-filled trench, with field doping regions beneath the field oxide regions.
  • FIGS. 2A-2F illustrate a process for fabricating a trench isolation structure that avoids the formation of a gap or recess at the top of the trench, as shown in FIG. 1C .
  • an oxide or “hard mask” layer 121 is formed on the top surface of a semiconductor substrate 120 , and a photoresist layer 122 is deposited on top of hard mask layer 121 .
  • the term “hard mask” is used herein to refer to a thermally grown or deposited dielectric layer used as a mask during the etching of a trench in semiconductor substrate 120 .
  • the “hard mask” is distinguished from the organic photoresist layer 122 , for example, which is mechanically softer and therefore subject to erosion during the trench etch process.
  • An opening is formed in photoresist layer 122 by a normal photolithographic process, and an opening 123 is etched in hard mask layer 121 through the opening in photoresist layer 122 .
  • substrate 120 is etched through the opening 123 to form a trench 124 . It is generally preferably to remove photoresist layer 132 prior to the etching of the trench, since photoresist layer 132 may interfere with the trench etching process, change shape during the trench etching process, and possibly introduce undesirable organic contaminants into the trench.
  • a reactive ion etch (RIE) can be used to achieve an anisotropic etch, producing a trench 124 having vertical walls.
  • a relatively thin oxide layer 125 is grown thermally on the walls and floor of trench 124 .
  • a sacrificial oxide layer can be formed to remove crystal defects caused by the RIE process, the sacrificial oxide layer can be removed, and then a second oxide layer can be grown.
  • the thickness of oxide layer 125 could be from 100 to 1000 ⁇ , typically about 300-400 ⁇ . If trench 124 is later filled with a doped dielectric material, oxide layer 125 will prevent the dopant from entering the semiconductor material surrounding trench 124 .
  • a relatively thick layer 126 of a glass such as borophosphosilicate glass (BPSG) is spun onto the surface of substrate 120 , completely filling trench 124 .
  • the BPSG could be doped to reduce its viscosity, or it could be undoped.
  • the BPSG could be deposited by chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • oxide layer 125 acts as a barrier to prevent the dopant from entering and doping substrate 120 .
  • BGSG layer 126 is sufficiently thick (e.g., 0.5 to 1.0 ⁇ m thick) that its top surface is relatively planar, with only a small dent over the location of trench 124 . If desired, a high temperature reflow can be used to further planarize the surface of BPSG layer 126 .
  • BPSG layer 126 and sidewall oxide layer 125 are etched back until their top surfaces are below the surface of substrate 120 , forming a recess 130 .
  • the surface of BPSG layer 126 may be from 0.1 to 0.5 ⁇ m (typically about 0.2 to 0.3 ⁇ m) below the surface of substrate 120 .
  • a layer 131 of another dielectric is deposited, filling recess 130 and overflowing the surface of substrate 120 .
  • Layer 131 is then planarized by CMP or etchback to form a protective cap 132 , which completely covers and protects oxide layer 125 and BPSG layer 126 .
  • the top surface of cap 132 is preferably coplanar with the surface of substrate 120 , although it could vary by 0.1 ⁇ m in height across the wafer.
  • FIG. 2F shows the structure after cap 132 has been formed.
  • Layer 131 and cap 132 should be formed of a material that is not significantly etched by the cleaning and etching steps that are to take place later in the process.
  • layer 131 may be formed of silicon nitride.
  • the material of which layer 131 is formed does not etch at all, or etches substantially slower than BPSG layer 126 or oxide layer 125 , in the subsequent processing steps.
  • a protective cap according to this invention can be formed at any time during the process to protect the trench-fill material from subsequent erosion of the kind shown in FIG. 1C .
  • silicon nitride that can provide a protective shield against further etching typically do not deposit very uniformly and thus it is difficult to get them to fill a trench. Moreover, silicon nitride tends to crack when deposited thickly. These problems are overcome by filling the trench with a softer, less brittle material such as BPSG and then covering the material with a relatively thin protective cap of a harder, more brittle material such as silicon nitride.
  • Table 1 shows the relative removal rates of materials that can be used to fill the trench for several etchants or removal methods.
  • FIGS. 3A-3D There are numerous variations of the process illustrated in FIGS. 2A-2F .
  • FIGS. 3A-3D One such variation is shown in FIGS. 3A-3D .
  • FIG. 3A is similar to FIG. 2D and shows the structure after BPSG layer 126 and oxide layer 125 have been etched back until their top surfaces are below the surface of substrate 120 .
  • a thin oxide layer 140 is then thermally grown on the surface of substrate 120 and, as shown in FIG. 3C , nitride layer 131 is then deposited.
  • oxide layer 140 separates nitride layer 131 from semiconductor substrate 120 .
  • an oxynitride layer may be deposited using chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • nitride layer 131 When nitride layer 131 is planarized or etched back, as shown in FIG. 3D , the nitride cap that remains in the trench is not in contact with the sidewalls of the trench. While this cap may not provide as effective a seal as the embodiment show in FIG. 2F , the presence of oxide (or oxynitride) layer 140 on the walls of the trench tends to reduce the stress that is attributable to the different thermal expansion coefficients of nitride and silicon, respectively. Oxide (or oxynitride) layer 140 thus provides stress relief.
  • gap 150 is nonetheless much smaller than the recess 103 , shown in FIG. 1C , and much easier to fill with a subsequent layer of, for example, BPSG. It is preferable, however, not to remove all of oxide layer 140 .
  • FIG. 5 is a flow chart summarizing the processes described above, each step being represented by a “card” (the clipped cards denoting optional steps).
  • the trench is formed by depositing a hard mask layer (e.g., oxide or nitride), depositing a photoresist layer, patterning the photoresist layer to create a trench mask, etching the hard mask layer through an opening in the trench mask, optionally //the photoresist layer, and etching the trench through an opening in the hard mask layer.
  • a hard mask layer e.g., oxide or nitride
  • a sacrificial oxide layer can be formed on the walls of the trench and removed, a lining oxide layer is grown, the trench is filled with a dielectric (e.g., BPSG), and optionally the dielectric can be planarized by etching or CMP.
  • a dielectric e.g., BPSG
  • the dielectric fill is etched back into the trench, optionally an oxynitride or oxide layer is grown or deposited on the walls of the trench, and a nitride layer is deposited and etched back until it is substantially coplanar with the top surface of the substrate.
  • a non-planar structure 200 is illustrated in FIG. 6A .
  • a substrate 205 has a top surface 202 .
  • a trench 201 has been etched in substrate 205 and a field oxide region 203 has been thermally grown in the substrate such that field oxide region extends upward beyond the surface 202 as well as downward into the substrate.
  • a polysilicon layer 204 has been deposited on top of field oxide region 203 .
  • an etchback can be used to planarize the surface of the dielectric with surface 202 . Otherwise, if CMP is used to planarize the dielectric, it is clear that polysilicon layer 204 as well as a portion of field oxide region 203 will be removed.
  • FIG. 6B shows trench 201 lined with an oxide layer 206 and filled with BPSG 207 , both of which have been etched back into the trench. The entire structure is covered with a nitride layer 208 , which also fills the upper portion of the trench.
  • FIG. 6C the top surface has been planarized by CMP, leaving the bottom portion 209 of field oxide region 203 and a protective nitride cap 210 over the BPSG 207 and oxide layer 206 .
  • the top surface is totally flat. Since having a nonplanar top surface greatly complicates further processing, the flat structure shown in FIG. 6C is preferable to the structure shown in FIG. 6A . Furthermore, since field oxide region 203 is grown by thermal means, the remaining region 209 can be very wide, whereas the trench can be very narrow. To summarize, the structure shown in FIG. 6C includes a “capped” trench that is resistant to etching because of cap 210 and an “uncapped” field oxide region 209 .
  • FIGS. 7A-7H illustrate a process by which a wide isolation trench and a narrow isolation trench can be formed using a minimal number of steps.
  • a hard mask layer 252 has been deposited on a substrate 251 , and a photoresist layer 253 has been deposited on top of hard mask layer 252 .
  • Photoresist layer 253 is etched to form a wide opening and hard mask layer 252 is etched through the wide opening in photoresist layer 253 to form a wide opening 254 which exposes the surface of substrate 251 .
  • substrate 251 is etched by RIE to form a wide trench 260 .
  • Photoresist layer 253 is removed and a new photoresist layer 257 is deposited. If trench 260 is not too deep, photoresist layer 257 will cover the step between the bottom of trench 260 and the top surface of substrate 251 .
  • a relatively narrow opening is etched in photoresist layer 257 , and hard mask layer 252 is etched through the opening in photoresist layer 257 to form a narrow opening 256 which exposes the surface of substrate 251 .
  • layer 257 may represent a deposited hard mask dielectric layer patterned and etched by a photoresist layer (not shown).
  • substrate 251 is etched by RIE to form a narrow trench 261 .
  • Photoresist (or hard mask) layer 257 and hard mask layer 252 are then removed, or patterned and etched.
  • a sacrificial oxide layer (not shown) can be grown in trenches 260 and 261 and removed to repair any crystal damage resulting from the RIE processes.
  • a thin oxide layer 262 is grown as a barrier against the diffusion of dopants into substrate 251 , and a layer 263 of BPSG is deposited over the entire surface of the structure.
  • layer 263 could include any doped or undoped CVD-deposited or spin-on silicon oxide or silicate glass or any other dielectric “fill” material, provided that the dielectric fill material exhibits sufficiently low stress so as to avoid cracking during subsequent processing steps, during assembly, and during temperature variations encountered during device operation.
  • process sequence could be revised such that the narrower trench is formed before the wider trench.
  • the entire top surface of the structure is planarized by CMP or by a short chemical etchback followed by CMP.
  • oxide layer 262 and BPSG layer 263 are etched back (e.g., by an acid or dry etch) into trenches 260 and 261 to form depressions 270 and 271 , as shown in FIG. 7F .
  • a dielectric dissimilar to silicon dioxide, silicate glass, or BPSG e.g., nitride or polyimide
  • FIG. 7G A dielectric dissimilar to silicon dioxide, silicate glass, or BPSG (e.g., nitride or polyimide) is deposited over the top surface of the structure, as shown in FIG. 7G , and the top surface is again planarized to form protective caps 280 in the mouths of trenches 260 and 261 , shown in FIG. 7H .
  • the material used to form caps 280 may comprise a brittle or high stress material, provided that the material is not eroded by the normal etches encountered during subsequent wafer processing in IC manufacturing and provided that caps 280 are made sufficiently thin to avoid cracking.
  • FIGS. 8A-8J illustrate a process for forming a capped isolation trench and capped field oxide region.
  • a pad oxide layer 302 is grown on silicon substrate 301 , and as in a typical local oxidation of silicon (LOCOS) sequence, a nitride layer 303 is deposited on pad oxide layer 302 .
  • Pad oxide layer can be 300 to 1000 ⁇ thick, for example.
  • Nitride layer 303 is etched through a mask layer (not shown) to form a wide opening 304 which exposes pad oxide layer 302 .
  • the structure is heated (for example, to 900-1100° C. for 1 to 4 hours) to form a thick field oxide region 305 in opening 304 .
  • nitride layer 303 is lifted up by the expanding oxide at the edge of opening 304 , forming the familiar “bird's beak” shape.
  • the remaining portion of nitride layer 303 is etched ( FIG. 8C ), and the top surface is planarized by a CMP process, yielding the result shown in FIG. 8D , with a smooth transition between the remaining portion 306 of field oxide region 305 and pad oxide layer 302 .
  • a photoresist layer 308 is deposited and patterned to form a narrow opening 309 .
  • Oxide layer 307 is etched through opening 309 and, as shown in FIG. 8F , substrate 301 is etched by an RIE process to form a narrow trench 310 , with oxide layer 307 acting as a hard mask. The remains of oxide layer 307 may be removed in a short cleaning step.
  • a thin oxide layer 311 is grown on the walls of trench 310 and a layer 312 of BPSG or any other dielectric filler is deposited.
  • the top surface of substrate 301 is planarized by etching or CMP.
  • oxide layer 311 and BPSG layer 312 in trench 310 and the remaining portion 306 of field oxide region 305 are etched back until the top surfaces of these elements are below the top surface of substrate 301 .
  • a layer 315 of a dissimilar dielectric such as nitride is deposited over the structure ( FIG. 8I ), and the structure is again subjected to a CMP process to planarize the top surface and create protective caps 316 over trench 310 and field oxide 306 ( FIG. 8J ).
  • FIGS. 9A-9E illustrate a process that produces a structure having field doping regions under the field oxide isolation regions but not under the trench isolation structures.
  • a pad oxide layer 351 has been grown on silicon substrate 350 , and a nitride layer 352 and photoresist layer 353 have been deposited in that order on top of pad oxide layer 351 .
  • Photoresist layer 353 is patterned to form two openings 354 A and 354 B, and nitride layer 352 is etched through openings 354 A and 354 B to expose pad oxide layer 351 .
  • Phosphorus (P+) is implanted through openings 354 A and 354 B to form N-type regions 356 A.
  • the dose of the phosphorus implant is typically in the range of 5 ⁇ 10 12 to 3 ⁇ 10 13 cm ⁇ 2 and the implant energy is typically from about 80 to 120 keV.
  • a layer of polyimide may be substituted for nitride layer 352 and may be used to form the hard mask for etching trench 374 .
  • photoresist layer 353 is removed, and a new photoresist layer 355 is deposited and patterned to form an opening that includes the location of former opening 354 B in photoresist layer 353 .
  • Boron (B+) is implanted through the opening in photoresist layer 355 to form a P-type region 356 B. Since the dose of the boron implant is typically an order of magnitude greater than the phosphorus implant (e.g., 8 ⁇ 10 13 to 2 ⁇ 10 14 cm ⁇ 2 ) the boron counterdopes the phosphorus region under opening 354 B to form P-type region 356 B.
  • the energy of the boron implant is typically 60 to 120 keV.
  • Field oxide regions 370 A and 370 B could be from 2000 ⁇ to 2 ⁇ m in thickness (typically about 0.8 ⁇ m). This thermal process also activates the phosphorus and boron dopants and forms an N-type field doping region 358 A under field oxide region 370 A and a P-type field doping region 358 B under field oxide region 370 B.
  • nitride layer 352 are removed ( FIG. 9D ), and optionally a sacrificial oxidation may be preformed.
  • a trench 374 is etched and oxidized to form an oxide layer 371 , followed by a dielectric fill with a material such as BPSG 372 in the manner described previously.
  • the top surface of the structure is planarized by CMP or etchback, and oxide layer 371 , BPSG 372 and the remains of field oxide regions 370 A and 370 B are etched back in the manner described above.
  • a layer of nitride (or another dielectric dissimilar to the material used to fill trench 374 ) is deposited on the top surface, and the surface is then planarized to form protective caps 373 .
  • This process yields a relatively narrow trench with no field doping which might be used to isolate low-voltage devices, for example, and wide field oxide regions with field doping which might be used to isolate high-voltage CMOS devices, for example.
  • the process gives the designer the ability to form isolation regions of different widths and different field dopings in the same semiconductor substrate, with a flat top surface to simply any further processing.
  • the isolation regions can be formed with protective caps, if desired.
  • the material in the trench is protected by a graded dielectric fill in lieu of a discrete trench cap.
  • the trench is at least partially filled with a mixture of a relatively soft, low stress dielectric and a relatively hard, etch resistant dielectric.
  • the proportion of the relatively hard, etch resistant dielectric in the mixture increases as one approaches the mouth of the trench.
  • a mixture of silicon dioxide and silicon nitride may be deposited in the trench, with the percentage of silicon nitride in the mixture being increased near the mouth of the trench.

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US11/298,075 2005-12-09 2005-12-09 Isolation structures for semiconductor integrated circuit substrates and methods of forming the same Abandoned US20070132056A1 (en)

Priority Applications (18)

Application Number Priority Date Filing Date Title
US11/298,075 US20070132056A1 (en) 2005-12-09 2005-12-09 Isolation structures for semiconductor integrated circuit substrates and methods of forming the same
KR1020117014788A KR20110079861A (ko) 2005-12-09 2006-12-07 반도체 집적회로 기판용 분리 구조체와 형성 방법
PCT/US2006/046579 WO2007070311A1 (en) 2005-12-09 2006-12-07 Isolation structures for semiconductor integrated circuit substrates and methods of forming the same
JP2008544483A JP5438973B2 (ja) 2005-12-09 2006-12-07 半導体集積回路基板の絶縁構造およびその製作方法
EP06844906A EP1958249A1 (en) 2005-12-09 2006-12-07 Isolation structures for semiconductor integrated circuit substrates and methods of forming the same
KR1020117022767A KR101323497B1 (ko) 2005-12-09 2006-12-07 반도체 집적회로 기판용 분리 구조체와 형성 방법
CN2006800525978A CN101366112B (zh) 2005-12-09 2006-12-07 用于半导体集成电路基板的隔离结构及其形成方法
KR1020087014965A KR20080098481A (ko) 2005-12-09 2006-12-07 반도체 집적회로 기판용 분리 구조체와 형성 방법
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TW103103967A TWI544573B (zh) 2005-12-09 2006-12-08 半導體積體電路基板之絕緣結構及其製造方法
US12/150,704 US7923821B2 (en) 2005-12-09 2008-04-30 Semiconductor integrated circuit substrate containing isolation structures
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JP2013076644A JP2013168662A (ja) 2005-12-09 2013-04-02 半導体集積回路基板の絶縁構造およびその製作方法
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WO2007070311A1 (en) 2007-06-21
US7994605B2 (en) 2011-08-09
US7923821B2 (en) 2011-04-12
KR20080098481A (ko) 2008-11-10
CN101366112A (zh) 2009-02-11
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KR20110079861A (ko) 2011-07-08
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US20100055864A1 (en) 2010-03-04
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US7955947B2 (en) 2011-06-07
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US20080203543A1 (en) 2008-08-28
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US7915137B2 (en) 2011-03-29
US20080203520A1 (en) 2008-08-28
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KR101323497B1 (ko) 2013-10-31
CN101366112B (zh) 2011-05-04

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