CN109216256A - 沟槽隔离结构及其制造方法 - Google Patents

沟槽隔离结构及其制造方法 Download PDF

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CN109216256A
CN109216256A CN201710534677.7A CN201710534677A CN109216256A CN 109216256 A CN109216256 A CN 109216256A CN 201710534677 A CN201710534677 A CN 201710534677A CN 109216256 A CN109216256 A CN 109216256A
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silica
side wall
nitrogenous compound
silicon oxide
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祁树坤
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CSMC Technologies Corp
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Abstract

本发明涉及一种沟槽隔离结构及其制造方法，所述方法包括：在晶圆表面形成上宽下窄的浅槽；通过淀积向浅槽内填充氧化硅；通过刻蚀去除掉一部分氧化硅；通过热氧化在浅槽顶部的拐角处形成氧化硅拐角结构；在晶圆表面淀积氮化硅，覆盖浅槽内的氧化硅表面及氧化硅拐角结构表面；干法刻蚀氮化硅，将浅槽内的氧化硅表面的氮化硅去除，氧化硅拐角结构表面形成向沟槽内延伸的氮化硅残留；以氮化硅残留为掩膜，继续向下刻蚀形成深槽；在深槽的侧壁和底部形成氧化硅层；向浅槽和深槽内淀积多晶硅；去除氮化硅；在浅槽内形成氧化硅将多晶硅覆盖。本发明的浅槽有较大的尺寸，形成的沟槽隔离结构能够降低沟槽隔离结构上方的高压走线导致的漏电可能性。

Description

沟槽隔离结构及其制造方法
技术领域
本发明涉及半导体制造领域，特别是涉及一种沟槽隔离结构的制造方法，还涉及一种沟槽隔离结构。
背景技术
在智能电源管理、显示以及马达驱动和汽车电子等领域，对高效、节能的要求日趋提高。高压功率领域也衍生出诸如LDMOS(横向双扩散金属氧化物半导体场效应管)、LIGBT(横向绝缘栅双极型晶体管)、power-DMOS(功率-双扩散金属氧化物半导体场效应管)等不同电压等级、不同结构的器件结构，耐压由几十伏至上百伏，因此各种各样的场板、场环等终端结构和RESURF(降低表面电场)技术被开发出来，以辅助这些高压功率器件能保证较低的比导通电阻，这对器件隔离技术提出了很高的要求。
这其中，深槽隔离(DTI)技术作为通用的技术，以其尺寸小、低漏电、双向隔离得以广泛应用。但由于高压功率器件的性能相当依赖于隔离技术，特别是器件雪崩击穿时形成大量的热电子/空穴，其中一部分克服Si/SiO2势垒进入DTI的氧化层、被DTI中氧化层/多晶硅界面处的陷阱(陷阱的面密度大概为E+10/cm2量级)俘获，并在多晶硅中受电场影响漂移，使得器件之间发生互扰(cross-talk)，极易导致隔离失效、耐压性能降低。因此持续改进深槽隔离的工艺技术，是高压功率器件领域的重点之一。
发明内容
基于此，有必要提供一种不容易产生漏电的沟槽隔离结构的制造方法。
一种沟槽隔离结构的制造方法，包括：在晶圆表面形成上宽下窄的第一沟槽；通过淀积向所述第一沟槽内填充氧化硅；通过刻蚀去除掉第一沟槽内的氧化硅表面的一部分；通过热氧化在第一沟槽顶部的拐角处形成氧化硅拐角结构，所述氧化硅拐角结构为从拐角处往下、位于第一沟槽内部的氧化硅逐渐变厚的结构；在晶圆表面淀积含氮化合物，覆盖所述第一沟槽内的氧化硅表面及所述氧化硅拐角结构表面；干法刻蚀所述含氮化合物，将第一沟槽内的氧化硅表面的含氮化合物去除，所述氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留；以所述含氮化合物侧壁残留为掩膜，继续向下刻蚀氧化硅和晶圆形成第二沟槽；在所述第二沟槽的侧壁和底部形成氧化硅层；向所述第一沟槽和第二沟槽内淀积多晶硅；去除所述含氮化合物；在第一沟槽内形成氧化硅将多晶硅覆盖。
在一个实施例中，所述第一沟槽的深度为1～2微米，所述第二沟槽的深度为10微米以上。
在一个实施例中，所述在所述第二沟槽的侧壁和底部形成氧化硅层的步骤是采用热氧化工艺，形成的氧化硅层厚度为1000埃以上。
在一个实施例中，所述在所述第二沟槽的侧壁和底部形成氧化硅层的步骤之后、所述向所述第一沟槽和第二沟槽内淀积多晶硅的步骤之前，还包括分别向所述第二沟槽内注入N型离子和P型离子，在所述第二沟槽的底部周围形成N型环和P型环的步骤。
在一个实施例中，所述去除所述含氮化合物侧壁残留的步骤之前，还包括刻蚀所述多晶硅至所述含氮化合物侧壁残留下方的步骤。
在一个实施例中，所述通过淀积向所述第一沟槽内填充氧化硅的步骤之前还包括对所述第一沟槽进行侧壁氧化的步骤。
在一个实施例中，所述在晶圆表面形成上宽下窄的第一沟槽的步骤之前还包括在晶圆表面形成氮化硅层的步骤，所述在晶圆表面形成上宽下窄的第一沟槽的步骤是将所述氮化硅层刻穿形成所述第一沟槽。
在一个实施例中，所述通过热氧化在第一沟槽顶部的拐角处形成氧化硅拐角结构的步骤中，氧化温度为800～950摄氏度。
在一个实施例中，所述在晶圆表面形成上宽下窄的第一沟槽的步骤，和所述干法刻蚀所述含氮化合物的步骤，是采用CHCl3和/或CH2Cl2作为刻蚀剂。
在一个实施例中，所述含氮化合物是氮化硅。还有必要提供一种不容易产生漏电的沟槽隔离结构。
一种沟槽隔离结构，包括沟槽，填充于所述沟槽内的氧化硅，以及位于所述沟槽内、被所述氧化硅包围的多晶硅，其特征在于，所述沟槽包括上宽下窄的瓶口结构和从所述瓶口结构向下延伸的瓶身结构。
在一个实施例中，还包括位于所述瓶身结构底部周围的N型环和P型环，所述P型环位于所述N型环上方。
上述沟槽隔离结构及其制造方法，采用第一沟槽+第二沟槽的结构，沟槽隔离结构的上部具有较大的尺寸(即第一沟槽)，这样最终形成的沟槽隔离结构相对于窄沟槽能够降低沟槽隔离结构上方的高压走线导致的漏电可能性。
附图说明
图1是一实施例中沟槽隔离结构的制造方法的流程图；
图2至图7是一实施例中采用沟槽隔离结构的制造方法制造的器件在制造过程中的剖视图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中沟槽隔离结构的制造方法的流程图，包括下列步骤：
S110，在晶圆表面形成上宽下窄的第一沟槽。
可以采用本领域习知的工艺在晶圆(本实施例中为硅片)表面刻蚀出上宽下窄的第一沟槽(浅槽)。在本实施例中，刻蚀形成第一沟槽之前可以先在晶圆表面形成一层氮化硅膜，再于氮化硅膜上通过光刻胶图案化出刻蚀窗口，再通过刻蚀窗口刻穿氮化硅膜形成第一沟槽，刻蚀完成后第一沟槽顶部的周围形成有氮化硅层。在本实施例中，第一沟槽的刻蚀是采用CHCl3和/或CH2Cl2作为刻蚀剂进行干法刻蚀，在其他实施例中也可以采用其他本领域习知的沟槽刻蚀工艺进行刻蚀。
第一沟槽的上部的宽度较宽，这样最终形成的沟槽隔离结构相对于窄沟槽能够降低沟槽隔离结构上方的高压走线导致的漏电可能性。在一个实施例中，第一沟槽的深度为1～2微米。
在一个实施例中，通过外延工艺在高掺杂浓度的衬底上外延出低掺杂浓度的外延层，步骤S110刻蚀得到的沟槽是形成于外延层中。
S120，通过淀积向第一沟槽内填充氧化硅。
通过淀积工艺形成氧化硅(SiOx)层的速度远大于传统的通过热氧化生长氧化硅层的速度。在本实施例中，步骤S120是采用高密度等离子化学气相淀积(HDPCVD)工艺进行氧化硅的淀积，可以获得较好的形貌。在其他实施例中也可以根据实际需求采用其他本领域习知的淀积工艺淀积氧化硅层。
淀积完后可以通过化学机械研磨(CMP)将多余的氧化硅层去除，即将露出于沟槽外面的氧化硅层去除。对于步骤S110采用氮化硅作为硬掩膜刻蚀出第一沟槽的实施例，CMP是将氧化硅层研磨至该氮化硅层。
在一个实施例中，步骤S120之前还包括对第一沟槽进行侧壁氧化，形成侧壁氧化层204的步骤。侧壁氧化可以起到修复步骤S110的沟槽刻蚀在第一沟槽内壁和底部的硅表面产生的缺陷(例如因反应离子刻蚀的高能粒子撞击产生的缺陷)的作用，消除该缺陷对栅氧产生的负面影响。
S130，通过刻蚀去除掉第一沟槽内的氧化硅表面的一部分。
可以采用干法刻蚀，利用其各向异性获得合适的形貌。图2是本实施例中步骤S130完成后器件的剖视图。在其中一个实施例中，步骤S130选用高密度等离子刻蚀的工艺进行刻蚀。
S140，通过氧化在第一沟槽顶部的拐角处形成氧化硅拐角结构。
为了后续步骤中得到的含氮化合物侧壁残留能形成本方案所需的形貌，在刻蚀后通过氧化形成特殊的拐角形貌，即在沟槽内的氧化硅表面形成类似于半球形的凹面。从拐角处往下、位于沟槽内部的氧化硅逐渐变厚，从而形成圆滑的拐角，如图3所示。图3中在硅片的表面形成有第一沟槽，第一沟槽内填充有氧化硅202，第一沟槽顶部的周围形成有氮化硅层302。在本实施例中通过800～950摄氏度的低温氧化来得到该氧化硅拐角结构。采用低温氧化是因为发明人发现若采用较高的温度(例如1000摄氏度的牺牲氧化)，则晶圆的高浓度衬底中的掺杂离子容易反扩至低浓度的外延层102中，对器件性能产生负面影响。
S150，在晶圆表面淀积氮化硅，覆盖第一沟槽内的氧化硅表面及氧化硅拐角结构表面。
在本实施例中是通过化学气相淀积形成一层薄的含氮化合物，后续作为刻蚀的硬掩膜。该含氮化合物可以是氮化硅、氮氧化硅、氮化硼、氮化钛等，考虑到普适性，可以采用本领域常用的氮化硅。
S160，干法刻蚀含氮化合物，氧化硅拐角结构表面形成向第一沟槽内延伸的含氮化合物侧壁残留。
参见图3，利用干法刻蚀的各向异性，将沟槽内的氧化硅202表面的含氮化合物去除，同时在氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留304。含氮化合物侧壁残留304与沟槽内的一部分氧化硅202共同作为沟槽的侧壁结构。
S170，以含氮化合物侧壁残留为掩膜，继续向下刻蚀氧化硅和晶圆形成第二沟槽。
参见图4，含氮化合物侧壁残留304只会覆盖第一沟槽的一部分，因此没被含氮化合物侧壁残留304覆盖的区域就会被向下刻蚀掉(即部分氧化硅202、侧壁氧化层204及外延层102被刻蚀去除)形成第二沟槽201(深槽)。第二沟槽201的宽度受含氮化合物侧壁残留304限制，显然地，第二沟槽201的宽度小于第一沟槽的上部的宽度。采用含氮化合物侧壁残留304作为第二沟槽刻蚀的硬掩膜，可以不需要光刻版，能够节省成本。
在一个实施例中，第二沟槽201的深度为10微米以上。
S180，在第二沟槽的侧壁和底部形成氧化硅层。
在本实施例中，是通过热氧化的工艺形成氧化硅层206，被含氮化合物侧壁残留304覆盖的位置不会形成氧化硅层206，参见图5。
在本实施例中，步骤S180后还包括分别向第二沟槽201内注入N型离子和P型离子，在第二沟槽201的底部周围形成N型环104和P型环106的步骤。在一个实施例中，是先注入N型离子，注入深度较深，形成N型环104；后注入P型离子，注入深度较浅，在N型环104上方形成P型环106。在一个实施例中，注入的N型离子为磷离子、注入的P型离子为硼离子，由于硼离子的扩散速度较快故P型环106比N型环104宽。N型环104和P型环106能够形成纵向耗尽，同时较浅的P型环106起到降低来自于沟槽隔离结构的两侧P阱区漏电的作用。
S190，向第一沟槽和第二沟槽内淀积多晶硅。
在一个实施例中，是淀积多晶硅至所需的厚度以后就停止淀积。在本实施例中，是淀积过量的多晶硅后，再以含氮化合物残留304作为掩膜进行回刻，将多晶硅404刻蚀至所需的厚度，例如含氮化合物残留304下方，如图6所示。采用回刻多晶硅404的方式，能够尽量避免器件的多晶硅工艺导致的残留，从而降低表面漏电的可能性。在一个实施例中，淀积的多晶硅是本征多晶硅。
S200，去除含氮化合物。
为了将含氮化合物去除干净，可以采用湿法刻蚀，例如以浓磷酸为刻蚀剂进行刻蚀。本实施例中通过浓磷酸将氮化硅层302和含氮化合物侧壁残留304一并去除。
S210，在第一沟槽内形成氧化硅将多晶硅覆盖。
在本实施例中，是采用高密度等离子化学气相淀积(HDPCVD)工艺进行氧化硅的淀积。步骤S210完成后可以通过化学机械研磨对露出第一沟槽的氧化硅进行平坦化处理，参加图7。
上述沟槽隔离结构的制造方法，采用第一沟槽+第二沟槽的结构，沟槽隔离结构的上部具有较大的尺寸(即第一沟槽)，这样最终形成的沟槽隔离结构相对于窄沟槽能够降低沟槽隔离结构上方的高压走线导致的漏电可能性。采用含氮化合物残留作为硬掩膜刻蚀深槽，节省了达到同等隔离效果所需的光刻版(mask)数量。
上述沟槽隔离结构的制造方法适用于各种使用深槽隔离结构进行隔离的半导体器件。
本发明还相应提供一种沟槽隔离结构。参见图7，包括沟槽，填充于沟槽内的氧化硅206，以及位于沟槽内、被氧化硅206包围的多晶硅404。沟槽包括上宽下窄的瓶口结构和从瓶口结构向下延伸的瓶身结构。
在一个实施例中，沟槽隔离结构还包括位于瓶身结构底部周围的N型环104和P型环106，P型环106位于N型环104上方。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

1.一种沟槽隔离结构的制造方法，包括：
在晶圆表面形成上宽下窄的第一沟槽；
通过淀积向所述第一沟槽内填充氧化硅；
通过刻蚀去除掉第一沟槽内的氧化硅表面的一部分；
通过热氧化在第一沟槽顶部的拐角处形成氧化硅拐角结构，所述氧化硅拐角结构为从拐角处往下、位于第一沟槽内部的氧化硅逐渐变厚的结构；
在晶圆表面淀积含氮化合物，覆盖所述第一沟槽内的氧化硅表面及所述氧化硅拐角结构表面；
干法刻蚀所述含氮化合物，将第一沟槽内的氧化硅表面的含氮化合物去除，所述氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留；
以所述含氮化合物侧壁残留为掩膜，继续向下刻蚀氧化硅和晶圆形成第二沟槽；
在所述第二沟槽的侧壁和底部形成氧化硅层；
向所述第一沟槽和第二沟槽内淀积多晶硅；
去除所述含氮化合物侧壁残留；
在第一沟槽内形成氧化硅将多晶硅覆盖。
2.根据权利要求1所述的制造方法，其特征在于，所述第一沟槽的深度为1～2微米，所述第二沟槽的深度为10微米以上。
3.根据权利要求1所述的制造方法，其特征在于，所述在所述第二沟槽的侧壁和底部形成氧化硅层的步骤是采用热氧化工艺，形成的氧化硅层厚度为1000埃以上。
4.根据权利要求1所述的制造方法，其特征在于，所述在所述第二沟槽的侧壁和底部形成氧化硅层的步骤之后、所述向所述第一沟槽和第二沟槽内淀积多晶硅的步骤之前，还包括分别向所述第二沟槽内注入N型离子和P型离子，在所述第二沟槽的底部周围形成N型环和P型环的步骤。
5.根据权利要求1所述的制造方法，其特征在于，所述去除所述含氮化合物侧壁残留的步骤之前，还包括刻蚀所述多晶硅至所述含氮化合物侧壁残留下方的步骤。
6.根据权利要求1所述的制造方法，其特征在于，所述通过淀积向所述第一沟槽内填充氧化硅的步骤之前还包括对所述第一沟槽进行侧壁氧化的步骤。
7.根据权利要求1所述的制造方法，其特征在于，所述在晶圆表面形成上宽下窄的第一沟槽的步骤之前还包括在晶圆表面形成氮化硅层的步骤，所述在晶圆表面形成上宽下窄的第一沟槽的步骤是将所述氮化硅层刻穿形成所述第一沟槽。
8.根据权利要求1所述的制造方法，其特征在于，所述通过热氧化在第一沟槽顶部的拐角处形成氧化硅拐角结构的步骤中，氧化温度为800～950摄氏度。
9.一种沟槽隔离结构，包括沟槽，填充于所述沟槽内的氧化硅，以及位于所述沟槽内、被所述氧化硅包围的多晶硅，其特征在于，所述沟槽包括上宽下窄的瓶口结构和从所述瓶口结构向下延伸的瓶身结构。
10.根据权利要求9所述的沟槽隔离结构，其特征在于，还包括位于所述瓶身结构底部周围的N型环和P型环，所述P型环位于所述N型环上方。
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