TWI375326B - Methods of fabricating nitride-based transistors with a cap layer and a recessed gate - Google Patents
Methods of fabricating nitride-based transistors with a cap layer and a recessed gate Download PDFInfo
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- TWI375326B TWI375326B TW094112478A TW94112478A TWI375326B TW I375326 B TWI375326 B TW I375326B TW 094112478 A TW094112478 A TW 094112478A TW 94112478 A TW94112478 A TW 94112478A TW I375326 B TWI375326 B TW I375326B
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- Prior art keywords
- layer
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- ohmic contact
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Links
- 238000000034 method Methods 0.000 title claims description 48
- 150000004767 nitrides Chemical class 0.000 title description 24
- 239000010410 layer Substances 0.000 claims description 391
- 230000004888 barrier function Effects 0.000 claims description 79
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- 238000004519 manufacturing process Methods 0.000 claims description 15
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052681 coesite Inorganic materials 0.000 claims description 6
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- 238000000059 patterning Methods 0.000 claims description 6
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- 238000011065 in-situ storage Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
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- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims 3
- 238000010952 in-situ formation Methods 0.000 claims 1
- 239000011229 interlayer Substances 0.000 claims 1
- 239000007787 solid Substances 0.000 claims 1
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- 229910002601 GaN Inorganic materials 0.000 description 51
- 229910002704 AlGaN Inorganic materials 0.000 description 17
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 6
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 6
- 229910003468 tantalcarbide Inorganic materials 0.000 description 6
- 230000007704 transition Effects 0.000 description 6
- -1 GaN) Chemical class 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
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- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910000420 cerium oxide Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
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- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 241000894007 species Species 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
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- 239000000969 carrier Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- AHICWQREWHDHHF-UHFFFAOYSA-N chromium;cobalt;iron;manganese;methane;molybdenum;nickel;silicon;tungsten Chemical compound C.[Si].[Cr].[Mn].[Fe].[Co].[Ni].[Mo].[W] AHICWQREWHDHHF-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
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- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000011066 ex-situ storage Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical group [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
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- 238000005240 physical vapour deposition Methods 0.000 description 1
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- 229910052594 sapphire Inorganic materials 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- 230000026683 transduction Effects 0.000 description 1
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- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Recrystallisation Techniques (AREA)
Description
1375326 九、發明說明: ' 【發明所屬之技術領域】 本發明係關於半導體裝置,且更特定言之係關於倂入氮 化物基活性層之電晶體。 【先前技術】 經發現諸如矽(Si)及砷化鎵(GaAs)之材科已在用於較低 功率及(對於Si之狀況)較低頻率應用之半導體裝置中得到 廣泛應用。然而,因為此等(較常見之)半導體材料相對小 •之帶隙(例如,在室溫下以為1.12 ev,及GaAs為1>42 eV) - 及/或相對小之擊穿電壓,所以其不太適用於較高功率及/ 或高頻應用。 考慮到Si及GaAS所呈現之困難,高功率、高溫及/或高 頻應用及裝置已轉向諸如碳化石夕(在室溫下α加為2州 eV)及III族氮化物(例如,在室溫下GaN為3 36 π)之寬帶 隙半導體材料。通常’此等材料與砰化鎵及石夕相比具有較 ^高之電場擊穿強度及較高之電子飽和速度。 用於问功率及/或高頻率應用之特定裝置為高電子遷移 率電晶體(HEMT) ’在特定狀況下其亦稱為調變掺雜場效 電晶體_DFET)。此等裝置可在多種環境下提供操作優 勢’因為在具有不同帶隙能之兩種半導體材料之異質接面 處形成—維電子氣(2DEG),且其中較小帶隙之#料具有較 * 冑電子親和力。2卿為未摻雜之("非故意推雜”)較小帶隙 …材料:之累積層且可含有超過(例如)1〇13載流子/平方公分 之很问的薄片電子濃度。另外,源於較寬帶隙半導體中之 100909.doc 13.75326 電子轉移至2DEG,規因於減少之離子化雜質散射從而允 '許高電子遷移率。 ’ 高載流子濃度及高載流子遷移率之此組合可使HEMT產 生很大之轉導且可與用於高頻應用之金屬半導體場效電晶 體(MESFET)相比提供強效能優勢。 製造於氮化鎵/氮化鋁鎵(GaN/AlGaN)材料系統中之高電 子遷移率電晶體由於材料特點之組合而具有產生大量RF功 率之潛力,該組合包括上述高擊穿場、其寬帶隙、高導帶 偏移及/或高度飽和之電子漂移速度(electron drift velocity)。2DEG中電子之主要部分歸因於AlGaN中之極 化。GaN/AlGaN系統中之HEMT已被證明。美國專利第 5,192,987號及第 5,296,395號描述了 GaN/AlGaN HEMT結構 及製造方法。共同讓渡並以引用的方式倂入本文之 Sheppard等人的美國專利第6,316,793號描述了一種HEMT 裝置,其具有一半絕緣碳化矽基板、一位於該基板上之氮 化紹缓衝層、一位於該緩衝層上之絕緣氮化鎵層、一位於 該氮化鎵層上之氮化鋁鎵障壁層及一位於該氮化鋁鎵活性 結構上之鈍化層。 某些氮化物基電晶體之製造中之一步驟為在一凹槽中形 成閘極接觸。在達成高電流能力及低分散時可需要電晶體 之厚蓋結構。然而,可需要一穿過覆蓋層之閘極凹槽以達 * 成高擊穿電壓、低RF分散及/或高轉導同時伴隨高頻效 , 能。另一方面,用於形成凹陷閘極結構之蝕刻處理可能會 損壞產生電子之下方障壁層。2004年1月16日申請且題為 100909.doc 1375326 "NITRIDE-BASED TRANSISTORS WITH A CAP LAYER AND A LOW-DAMAGE RECESS AND METHODS OF FABRICATION THEREOF"之美國專利申請案第 10/758,871 號描述了用以經由SiN鈍化提供低損害凹槽之裝置及技 術,該申請案之揭示内容以如同本文完全陳述的方式倂入 本文中。 用以減輕蝕刻之GaN及AlGaN表面上之高洩漏的其它嘗 試包括在沉積肖特基金屬之後使用高溫退火。此等嘗試已 使用400-600°C之退火溫度。後肖特基/AlGaN高溫退火似 乎可將高洩漏肖特基/AlGaN接觸改良為適度洩漏之肖特基 /AlGaN接觸。 【發明内容】 本發明之某些實施例提供製造高電子遷移率電晶體 (HEMT)之方法’該方法包括形成一通道層、在該通道層 上形成一障壁層、在該障壁層上形成一覆蓋層及在該覆蓋 層中形成一延伸至障壁層之閘極凹槽。退火障壁層、通道 層及具有閘極凹槽之覆蓋層且接著在經退火之閘極凹槽中 形成閘極接觸。該閘極接觸可為肖特基接觸。 在本發明之其它實施例中,退火障壁層、通道層及具有 閘極凹槽之覆蓋層包括在至少約700°C之溫度下退火障壁 層、通道層及具有閘極凹槽之覆蓋層。可在於覆蓋層上及 閘極凹槽中形成封裝層之後退火。可在退火之後移除封裝 層且可在移除封裝層之後形成肖特基閘極接觸。該封裝層 可包括AIN。 I00909.doc I3J5326 在本發明之額外實施例中’該等方法進_步包括在閉極 凹槽之相對侧上之覆蓋層中形成歐姆接觸凹槽及在該等歐 姆接觸凹槽中形成歐姆接觸材料圖案。在某些實施例中, 退火障壁層、通道層及具有閘極凹槽之覆蓋層包括退火障 壁層、通道層、歐姆接觸材料圖案及具有閘極凹槽之覆蓋 層。此外,可在形成歐姆接觸材料圖案之後且可在退火之 前,在覆蓋層、歐姆接觸材料圖案上及閘極凹槽中形成封 裝層。可在退火之後且在形成閘極接觸之前移除封裝層。 該封裝層可包括A1N。 在本發明之又一些實施例中,形成一閘極凹槽包括:在 覆蓋層上圖案化一遮罩層以具有一對應於閘極凹槽之開 口;及將圖案化之遮罩層用作蝕刻遮罩來蝕刻覆蓋層以提 供閘極凹槽。可在於圖案化之遮罩層及閘極凹槽上形成封 農層之後退火。該封裝層可包括A1N。可在退火之後利用 自對準起離技術移除遮罩層及封裝層以便提供餘留於閘極 凹槽中之封裝層之一部分。可在形成閘極接觸之前移除該 閘極凹槽中之封裝層之部分。 在本發明之某些實施例中,在覆蓋層上及閘極凹槽中形 成一絕緣層。可在閘極凹槽中之絕緣層上形成閘極接觸。 閘極接觸亦可延伸至覆蓋層上之絕緣層上。 在本發明之某些實施例中’形成覆蓋層包括在障壁層上 形成GaN層。舉例而言’ GaN層可為未摻雜之GaN層、屬 於GaN級別之AlGaN層、属於GaN級別之AKJaN層及摻雜 之GaN層及/或摻雜之GaN層。形成覆蓋層亦可包括在障壁 100909.doc U75326 層上形成GaN層及在GaN層上形成㈣層。此外,形成間極 凹槽亦可包括形成延伸穿過覆蓋層且進入但不穿過障壁層 之閉極凹槽。在本發明之特定實施例中,覆蓋層包括GaN 基半導體材料。 在本發明之額外實施例中,製造高電子遷移率電晶體之 方法包括.在基板上第一層形成GaN基半導體材料,·在第 層上形成第二層A1GaN基半導體材料,該第二層經組態 馨為在接近第^與第二層間之介面之區域中感應二維電子 氣;及在第二層GaN基半導體材料上形成第三層<3aN基半 導體材料。該等方法進一步包括:在第三層中形成一延伸 至第二層之閘極凹槽;$火第-層、第二層及具有閘極凹 槽之第三層;及接著在經退火之閘極凹槽中形成閘極接 觸。該閘極接觸可為肖特基閘極接觸。 在本發明之其它實施例中,在於第三層GaN基半導體材 料上及閘極凹槽中形成封裝層之後退火。在退火之後可移 _除封裝層。可在移除封裝層之後形成閘極接觸。 在本發明之又一些實施例中,該等方法進一步:包括在 閘極凹槽之相對側上之第三層GaN基丰導體材料中形成歐 姆接觸凹槽;及在歐姆接觸凹槽中形成歐姆接觸材料圖 案。在此狀況下,退火第一層、第二層及具有閘極凹槽之 第二層包括退火第一層、第二層、歐姆接觸材料圖案及具 有閘極凹槽之第三層。 在本發明之額外實施例中,形成一閘極凹槽包括:在第 三層GaN基半導體材料上圖案化一遮罩層以具有一對應於 100909.doc 13.75326 • 間極凹槽之開口;及將圖案化之遮罩層用作蝕刻遮罩來蝕 刻第三層GaN基半導體材料以提供閘極凹槽。在此狀況 下’退火可在於圖案化之遮罩層及間極凹槽上形成封裝層 之後進行’且在利用自對準起離技術移除遮罩層及封裝層 以便提供餘留於閘極凹槽中之封裝層之一部分之前進行。 該封裝層可包括A1N、Si〇2及氮氧化物、ΟΝΟ結構及/或 SiN。 在本發明之某些實施例中,在形成閘極接觸之前移除餘 留於閘極凹槽中之封裝層之部分。此外,可在第三層 基材料上及凹槽中形成絕緣層,且在閘極凹槽中之絕緣層 上形成閘極接觸β亦可在第三層GaN基材料上之絕緣層上 形成閘極接觸。 【實施方式】 現將參看展示本發明之實施例之附圖在下文中更充分地 描述本發明。然而,不應將本發明解釋為限於本文所陳述 •之實施例。相反,提供此等實施例以使得此揭示内容將全 面且完整,並將完全傳送本發明之範疇至熟習此項技術 者。在s玄等圖式中,出於清晰之目的將層及區域之厚度放 大。整篇文中相同數字係指相同元件。本文所用之術語 ,,及/或"包括一或多個相關聯之列出項之任意及全部組合。 本文所用之術語為僅用於描述特定實施例之目的且並不 意欲限制本發明。本文所用之單數形式"一"及•,該"意欲同 樣包括複數形式,除非本文另外明確指出。應進—步瞭解 術語”包含,,在用於此說明書中時,其指定存在規定特徵、 100909.doc •10· 丄 J·/ 整體、步驟、操作、元件及/或組件,但不排除存在及添 加—或多個其它特徵、整體、步驟、操作、元件、組件及 /或其群。 應瞭解當諸如層、區域或基板之元件被稱為位於另一元 件上或延仲i其上"時,該元件可直接位於該另一元件 上或直接延伸至該另一元件上’或亦可存在介入元件。相 反·,,當—元件被稱為"直接,,位於另—元件"上"或"直接"延 t至其上時,不存在介入元件。亦應瞭解,當一元件被 稱為”連接"或’,耦接,,至另一元件時,該元件可直接連接或 耦接至該另一元件或可存在介入元件。相反,當一元件被 稱為"直料接”或"直_接"至另—元料,不存在介入 凡件。在整篇說明書中相同數字係指相同元件。 應瞭解’儘管在本文可使用術語第―、第二等等來摇述 各種兀件、组件、區域、層及/或區段,但是此等元件、 、-且件區域、層及/或區段不應受此等術語限制。此等術 語僅用於區別一元件、組件、區域、層或區段與另一區 域、層或區段。因此,在不背離本發明之教示的狀況下, 可將下文討論之第一元件、組件、區域、層或區段稱為第 二元件、組件、區域、層或區段。 此外在本文中可使用諸如"下,,或底部"與"上,,或”頂部I, 之相對術語來描述如圖式+所說明之—元件與另_元件之 關係。應瞭解相對術語除了包含圖式中所描繪之裝置之定 向之外還意欲包含不同定向。舉例而t,若將圖中之裝置 翻轉’則描述為位於其它元件之,,下,,側上之元件將被定向 100909.doc -II - 為位於其它元妹" 上側上。因此,例示性術語"m 广疋向可包含"下"及"上"兩者之定向。類似地若 =等圖之一中之裝置翻轉,則描述為位於其它元件"下 或下面之7C件將被定向為位於其它元件”上方"。因 :’例示性術語"下方,’或"下面”可包含上方及下方兩者之 定向。 在本文參看橫截面說明來描述本發明之實施例,該等橫 φ 。說月為本發明之理想化實施例之示意性說明。因而’ 可預期由(例如)製造技術及/或容限所導致之該等說明之形 狀變化。因此,不應將本發明之實施例解釋為限於本文所 說明區域之特定形狀’而應包括由(例如)製造所導致之形 狀偏差。舉例而言,一圖示為矩形之韻刻區域將通常具有 錐形、圓形或彎曲特徵。因此’該等圖式中所說明之區域 實質上是示意性的,且其形狀並不意欲說明一裝置之區域 之精確形狀且並不意欲限制本發明之範嘴。 春▲除非另外界定,否則本文所用之所有術語(包括技術術 語及科學術語)均具有本發明所屬之普通熟習此項技術者 通吊瞭解之相同含意。應進一步瞭解,應將諸如通用字典 中所定義之彼等術語解釋為具有與其在相關技術之内容^中 之含意一 S的含意,且除非在本文明顯地如此定義否則不 應從理想化或過度形式之意義上解釋。 熟習此項技術者亦將瞭解,對一結構或特徵("鄰近,,另— 特徵安置)之參考可具有重疊該鄰近特徵或位於該鄰近特 徵下面的部分。 100909.doc 12 13.75326 本發明之某些實施例在形成肖特基接觸之前使用一凹槽 退火以在諸如電晶體之半導體裝置中減少閘極洩漏及/或 ' 提供高品質肖特基接觸。在本發明之某些實施例中’凹槽 之退火亦可恢復經蝕刻之凹槽區域下之2DEG通道之傳導 性。在退火期間使用封裝層可防止對電晶體之閘極凹槽中 之半導體進一步損害。該退火可(例如)由該裝置之歐姆接 觸之退火來提供。因此,可提供具有減少之閘極區域之降 級的高品質閘極及歐姆接觸,此可由提供由在形成凹槽時 • ® 之蝕刻損害引起之凹陷閘極結構而導致。 本發明之實施例可尤其良好適用於諸如第III族氮化物基 裝置之氮化物基HEMT。本文所用之術語"第III族氮化物" 係指彼等由氮與元素週期表之第III族中之元素形成的半導 體化合物,通常為鋁(A1)、鎵(Ga)及/或銦(In) »該術語亦 指諸如AlGaN及AlInGaN之三元及四元化合物。如熟習此 項技術者所良好瞭解,第III族元素可結合氮以形成二元化 合物(例如GaN)、三元化合物(例如AlGaN)及四元化合物 (例如AlInGaN)。此等化合物全部具有實驗式,其中一莫 耳之氮結合總共一莫耳之第III族元素。通常使用諸如 AlxGa丨·XN(其中OSxSl)之式子來描述其。
可使用本發明之實施例之GaN基HEMT之適當結構描述 於(例如)共同讓渡之美國專利第6,316,793號及2001年7月 , 12日申請並於2002年6月6日公開之題為"ALUMINUM
GALLIUM NITRIDE/GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTORS HAVING A GATE CONTACT ON A 100909.doc 13 13.75326
GALLIUM NITRIDE BASED CAP SEGMENT AND METHODS OF FABRICATING SAME"之美國專利公開案第 • 2002/0066908A1 號、2001 年 5 月 11 日申請之題為"GROUP III NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER" 之美國臨時專利申請案第60/290,195號、2002年11月14曰 公開之題為"GROUP-III NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER"之 Smorchkova等人的美國專利 公開案第2002/01 67023 A1號、2003年7月11日申請之題為 "NITRIDE-BASED TRANSISTORS AND METHODS OF FABRICATION THEREOF USING ΝΟΝ-ETCHED CONTACT RECESSES”之美國專利申請案第10/617,843號及2002年7月 23日申請並於2003年1月30日公開之題為"INSULATING GATE ALGAN/GAN HEMT”之美國專利公開案第 2003/0020092號中,該等專利案之揭示内容全文以引用的 方式倂入本文中。 根據本發明之某些實施例的製造方法示意性說明於圖 1A-1F中。如圖1A中可見,提供一基板1〇,在其上可形成 氮化物基裝置。在本發明之特定實施例中’基板10可為半 絕緣碳化矽(SiC)基板,其可為(例如)碳化矽之4H多型》其 ,它碳化矽候選多型包括3C、6H及15R多型。術亨"半絕緣" -為描述性地使用而非以絕對意義使用。在本發明之特定實 施例中,碳化矽塊狀結晶在室溫下具有等於或大於約ΐχΐ〇5 100909.doc 13.75326 Ω-cm之電阻率。 可選之缓衝、長晶及/或過渡層(未圖示)可提供於基板10 上。舉例而言,可提供一 A1N緩衝層以提供碳化矽基板與 裝置之剩餘部分間之適當晶體結構過渡。另外,亦可提供 應變平衡過渡層,如描述於(例如)共同讓渡之2002年7月19 日申請並於2003年6月5日公開且題為"STRAIN BALANCED NITRIDE HETROJUNCTION TRANSISTORS AND METHODS OF FABRICATING STRAIN BALANCED NITRIDE HETEROJUNCTION TRANSISTORS"之美國專利 公開案第2003/0102482A1號及2001年12月3日申請且題為 "STRAIN BALANCED NITRIDE HETEROJUNCTION TRANSISTOR"之美國臨時專利申請案第60/337,687號中, 該等專利案之揭示内容以如同本文完全陳述之引用的方式 倂入本文中。 適當之SiC基板由本發明之受讓人(例如N.C.之Durham之 Cree有限公司)製造,且用於製造之方法描述於(例如)美國 再頒專利第Re. 34,861號、美國專利第4,946,547號、第 552005022號及第6:218,680號中,該等專利案之内容全文以 引用的方式倂入本文中。類似地,用於第ΙΠ族氮化物之蟲 晶成長的技術已描述於(例如)美國專利第5,21〇,〇51號、第 5,393,993號、第5,523,5 89號及第5,592,501號中’該等專 利案之内容全文亦以引用的方式倂入本文中。 儘管碳化矽可用作基板材料,本發明之實施例可使用任 何適當基板,諸如藍寶石、氮化鋁、氮化鋁鎵、氮化鎵、 100909.doc •15- 13.75326 碎、GaAs、LGO、ZnO、LAO、InP及類似物。在某些實 « 施例中,亦可形成一適當緩衝層。 轉向圖1Α,一通道層20提供於基板10上。利用如上所述 之緩衝層、過渡層及/或長晶層可將通道層20沉積於基板 10上》通道層20可處於壓縮應變下。此外,可藉由 MOCVD或熟習此項技術者已知之其它技術(諸如ΜΒΕ或 H VPE)來沉積通道層及/或緩衝長晶層及/或過渡層。 在本發明之某些實施例中,通道層20為第III族氮化物, 諸如AlxGa^N(其中0 $ X < 1),假定在通道層與障壁層之 間的介面處,通道層20之導帶邊緣之能量小於障壁層22之 導帶邊緣之能量。在本發明之某些實施例中,X = 0,表明 通道層20為GaN。通道層20亦可為其它第III族氮化物,諸 如InGaN、AlInGaN或其類似物。通道層20可為未摻雜的 ("非故意摻雜")且可成長至大於約20 A之厚度。通道層20 亦可為多層結構,諸如超晶格或GaN、AlGaN或其類似物 之組合。
障壁層22提供於通道層20上。通道層20可具有小於障壁 層22之帶隙的帶隙,且通道層20亦可具有大於障壁層22之 電子親和力。障壁層22可沉積於通道層20上。在本發明之 某些實施例中,障壁層22為AIN、AlInN、AlGaN或 AlInGaN,其具有介於約0.1 nm與約40 nm之間的厚度。根 •據本發明之某些實施例的層之實例描述於Smorchkova等人 • 之題為"GROUP-III NITRIDE BASED HIGH ELECTRON
MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER 100909.doc 16· 1375326 LAYER"之美國專利公開案第20〇2/0167〇23Α1號中,該案 之揭示内容以如同本文完全陳述之引用方式倂入本文中。 在本發明之特定實施例中,障壁層22足夠厚且具有足夠高 之A1成份並摻雜以在通道層20與障壁層22之間的介面處經 由極化效應來感應較大之載流子濃度。而且,障壁層Μ庳 足夠厚以減少或最小化由於沉積於障壁層22與覆蓋層24之 間的介面處之離子化雜質或瑕疵所導致的通道中電子之散 射(圖1Β)。
障壁層22可為第III族氮化物且具有大於通道層2〇之帶隙 及小於通道層20之電子親和力。因此,在本發明之某些實 施例中,障壁層22為AlGaN、AlInGaN及/或Α1Ν或其層之 組合。障壁層22可(例如)為約^ nm至約4〇 ,但;應 太厚而導致裂化或其中形成實質缺陷。在本發明之某些實 施例中,障壁層22為未摻雜的或摻雜η型摻雜物至小於約 10 9 cm 3之濃度。在本發明之某些實施例中,障壁層a為
AlxGa】_xN ’其中〇 < X < j。在特定實施例中 紹濃度為約 25%。然而,在本發明之其它實施例中,障壁層22包含 A1GaN,其中銘漠度介於約外與約1〇〇%之間。在本發明 之特定實施例中,鋁濃度大於約1〇%。 圖1B說明在障壁層22上形成相對厚之覆蓋層24。覆蓋層 24可為第⑽氮化# ’且在某些實施例中其可為諸如 GaN、滿撕/或化㈣之㈣基半導體材料。在本發明 :特定實施例中,覆蓋層為GaN。此外,覆蓋層以可:單 層或具有均勻及/或非均勻成份及/或厚度之多個層。在 I00909.doc •17· 1375326
本發明之某些實施例中,覆蓋層24可為分級之AlGaN層及 GaN層,如描述於2004年1月IEEE電子裝置期刊(IEEE Electron Device Letters)第 1期第 25 卷第 7-9 頁 Shen 等人的 "High-Power Polarization-Engineered GaN/AlGaN/GaN HEMTs Without Surface Passivation"中,其揭示内容以如 同完全陳述之引用的方式倂入本文中。舉例而言,在本發 明之某些實施例中,覆蓋層24可為GaN層,其中一 SiN層 位於該GaN層上。覆蓋層24移動裝置之頂面使其實體遠離 通道,此可減少表面之效應。 覆蓋層24可為形成於障壁層22上之覆蓋物且可磊晶地成 長及/或藉由沉積而形成。舉例而言,覆蓋層可藉由在GaN 覆蓋層上SiN之原位成長或在GaN覆蓋層之頂部SiN或Si02 之非原位PECVD(電漿增強化學氣體沉積)而形成。通常, 覆蓋層24可具有約2 nm至約500 nm之厚度。舉例而言, SiN及GaN之覆蓋層24可具有約300 nm之厚度。根據本發 明之某些實施例的覆蓋層之實例描述於Smorchkova等人的 題為"GROUP-ΠΙ NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER"之美國專利公開案第2002/0167023A1號中。 如圖1C中所說明,在遮罩層中打開窗口以提供用於形成 歐姆接觸30之第一遮罩圖案40。在本發明之某些實施例 中,第一遮罩層可為習知微影遮罩材料。在本發明之某些 實施例中,遮罩材料可為SiN、Si02或其類似物。可使用 圖案化遮罩及蝕刻處理以曝露下方障壁層22來形成窗口。 100909.doc • 18 - 13.75326 在本發明之某些實施例中,該蝕刻可為低損害蝕刻。在本 發明之某些實施例中’該蝕刻為利用強鹼(諸如具有uv照 明之KOH)之濕式蝕刻。在其它實施例中,該蝕刻為乾式 姓刻。用於第III族氮化物之低損害蝕刻技術之實例包括不 同於反應性離子蝕刻之蝕刻技術,諸如利用Cl2、BC13、 CChF2及/或其它氯化物質之感應耦合電漿或電子迴旋共振 (ECR)及/或下游電漿蝕刻(電漿中無DC分量)。用於SiN之 低損害蝕刻技術之實例包括不同於反應性離子蝕刻之蝕刻 •技術,諸如利用CFJO2、NFs/O2及/或其它氟化物質之感應 耦合電漿或電子迴旋共振(ECR)及/或下游電漿蝕刻(電漿 中無DC分量)。 如圖1C中進一步說明,舉例而言,藉由隨後之微影步驟 及蒸鏟’圖案化歐姆金屬以提供歐姆接觸材料圖案,該等 歐姆接觸材料圖案在退火時提供歐姆接觸3〇。在覆蓋層24 中使用SiN及/或Si〇2之本發明之某些實施例中,歐姆接觸 φ 30與覆蓋層24之SiN及/或Si〇2部分間隔充分大之距離以允 許歐姆接觸金屬之形成及圖案化中之未對準容限。若歐姆 接觸金屬接觸覆蓋層24之SiN及/或Si〇2部分,則該金屬可 在隨後之加熱步驟期間擴散至覆蓋層24中,此可導致閑極 接觸與歐姆接觸30之間的短路。 圖1D說明了閘極凹槽之形成。如圖id中所見,第二遮 罩圖案42形成於歐姆接觸及覆蓋層24上並經圖案化以形成 曝露覆蓋層24之一部分的窗口.。在本發明之某些實施例 中,第二遮罩圖案42可為習知微影遮罩材料。在本發明之 100909.doc •19· 1375326 某些實施例中,該遮罩材料可為氮化矽、二氧化矽或其類 似物。然後形成穿過覆蓋層24之凹槽36以曝露障壁層22之 一部分。在本發明之某些實施例中,形成凹槽36以延伸至 障壁層22中。凹槽36可延伸至障壁層22中以(例如)調整裝 置之效能特點,諸如臨限電壓、頻率效能等等。可利用遮 罩42及如上所述之蝕刻處理來形成該凹槽。在歐姆接觸30 提供源極及汲極接觸之特定實施例中,凹槽可在源極接觸 與汲極接觸間存在偏移,從而使得凹槽及隨後閘極接觸32 與源極接觸間的距離比汲極接觸更小。 圖1E說明了在移除第二遮罩圖案42之後形成一光學封裝 層44。封裝層44可形成於覆蓋層24上及凹槽36中。封裝層 44可為氮化矽(SixNy)、氮化鋁(AIN)、ΟΝΟ結構及/或其它 適當之保護材料,諸如二氧化矽(Si02)及/或氮氧化物。其 它材料亦可用於封裝層44,只要該材料可被移除而不會顯 著損害下方障壁層22。舉例而言,封裝層44亦可包括氧化 鎂、氧化銃、氧化鋁及/或氧氮化鋁。此外,封裝層44可 為單一層或均勻及/或非均勻成份之多個層。 在本發明之特定實施例中,封裝層44可為SiN、A1N、 ΟΝΟ結構及/或Si02。SiN、A1N及/或Si02可藉由PVD及/或 CVD形成且可為非化學計量的。參考2004年1月16日申請 且題為"NITRIDE-BASED TRANSISTORS WITH A CAP LAYER AND A LOW-DAMAGE RECESS AND METHODS OF FABRICATION THEREOF"之美國專利申請案第 10/75 8,871號中之保護層進一步詳細描述適當之封裝材 100909.doc •20· 1375326 料’遠案之揭示内容以如同本文完全陳述之引用的方式倂 入本文中。 封裝層44可為形成於覆蓋層24上及凹槽36中以便定位於 凹槽36中之障壁層22上之覆蓋物且可藉由沉積而形成。舉 例而a ’氮化矽層可藉由高品質濺鍍及/或pEcvD來形 成。封裝層44通常可具有約30 nm之厚度,然而,亦可使 用其匕厚度之層。舉例而言,封裝層應足夠厚以便在隨後 歐姆接觸之退火期間保護下方層。出於此等目的,與兩個 或三個單層一樣薄的層可為足夠的。然而,封裝層44 一般 可具有約10 nm至約500 nm之厚度。而且,高品質siN保護 層可藉由第III族氮化物層2M〇VCD成長而在原位成長。 在形成閘極凹槽36及封裝層44(若存在)之後,但在形成 閘極接觸之前,退火歐姆接觸材料以提供歐姆接觸3〇。該 退火可為高溫退火。舉例而言,退火可在約7〇〇〇c至約 900°C之溫度下,且在某些實施例中該溫度大於約9〇(rc。 舉例而言’退火可在利用快速熱退火系統中之習知量測技 術所量測之約700°C至約900°C之環境溫度下進行約3〇秒至 約5分鐘,該等習知量測技術諸如利用嵌於固持晶圓之晶 座中之熱電偶及/或光學高溫測量學。藉由使用歐姆接觸 退火,可將歐姆接觸之電阻自高電阻降低至小於約 1 Ω-mm 0 因此’本文所用之術語"歐姆接觸,,係指具有小於約1 n_mm 之接觸電阻的非整流接觸。已钱刻之閘極凹槽3 6之退火可 將可由閘極凹槽36之製造所引起之損害移除至障壁層22。 因此舉例而5 ’在兩溫歐姆接觸退火之後接近閘極凹槽 100909.doc -21 > 1375326 材料形成。在本發明之特定實施例中,封裝層耗為A丨N。 在本發明之其它實施例中,封裝層46可為任何惰性陶瓷材 料。此外,第二遮罩42可為siN。 在本發明之實施例中,第二遮罩42為可實質上受到隨後 退火損害之光阻或其它材料,第二遮罩42及封裝層46之部 分(例如)利用自對準起離技術被移除,以便在閘極凹槽中 提供封裝層46之一部分26。然後如上所述對圖2A之結構退 火。在本發明之某些實施例中,封裝層46可具有約1 至 約500 nm之厚度。 如圖2B中所見,第二遮罩42及封裝層46之部分(例如)利 用自對準起離技術被移除,以便在閘極凹槽中提供封裝層 46之一部分26。然後閘極接觸32形成於餘留在閘極凹槽中 之部分26上。在某些實施例中,在形成閘極接觸32之前移 除部分26。在圖2B中所說明之實施例中,閘極接觸可由上 述之材料形成。 圖3說明了根據本發明之其它實施例之電晶體之形成。 如圖3中所見,圖2B之結構可移除部分26且一絕緣層13〇形 成於包括於閘極凹槽中之所得結構上》然後閘極接觸32可 形成於絕緣層130上。絕緣層130可為一或多個層且可包括 (例如)SiN、AIN、Si02及/或ΟΝΟ結構。因此,在本發明之 某些實施例中,可提供絕緣閘極ΗΕΜΤ,例如描述於 Parikh 等人的題為"INSULATING GATE ALGAN/GAN ΗΕΜΤ"之美國專利公開案第2003/0020092號中,該案之揭 示内容以如同本文完全陳述之引用的方式倂入本文中。 100909.doc -23· 1375326 θ雖然已參照操作之特定序列來描述本發明之實施例,但 是可在該序列中進行某些修改或亦可包括其它操作而同 時仍受益於本發明之教示。舉例而言,可忽略在歐姆金屬 沉積之前覆蓋層24之形成,且歐姆金屬可沉積及圖案化於 障壁層22上以在障壁層22上提供歐姆接觸材料區域3〇。然 後在歐姆接觸材料之沉積及圖案化之後形成覆蓋層。然後 可蝕刻覆蓋層以提供閘極凹槽且在形成閘極接觸之前進行 歐姆接觸退火。 提供於單一步驟中之上述操作可提供於多個步驟中,同 樣地,描述為多個步驟之操作可組合於單一步驟中。舉例 而δ,雖然已將自閘極凹槽蝕刻移除損害之退火描述為由 歐姆接觸退火提供,但是亦可提供單獨退火。若將退火提 供為單獨退火,則該退火可在(例如)約6〇(rc至約9〇〇它之 溫度下進行約30秒至約20分鐘。另外,可利用單一遮罩而 非如上所述之兩個單獨遮罩來進行歐姆接觸凹槽及間極凹 槽之蝕刻。 雖然已參照特定HEMT結構在本文描述了本發明之實施 例,但是不應將本發明解釋為限於此等結構◊舉例而言, 額外層可包括於HEMT裝置令而同時仍受益於本發明之教 示。此等額外層可包括GaN覆蓋層,例如描述於1998年應 用物理期刊(Applied Physics Letters)第13期第73卷中Yu等 人的"Schottky barrier engineering in m_v nitddes 化加 piezoelectric effect”中,或描述於2〇〇1年7月12日申請且 2002年6月6日公開之題為"aluminum GALUUm 100909.doc ·24· 1375326 NITRIDE/GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTORS HAVING A GATE CONTACT ON A GALLIUM NITRIDE BASED CAP SEGMENT AND METHODS OF FABRICATING SAME"之美國專利公開案第 2002/0066908A1 號中,其揭示内容以如同本文完全陳述之引用的方式倂入 本文中。在某些實施例中,可沉積諸如SiN、ΟΝΟ結構或 相對高品質Α1Ν之絕緣層以製造MISHEMT及/或鈍化表 面。額外層亦可包括在成份上分級之過渡層。 此外,障壁層22亦可具有多個層,如描述於Smorchkova 等人的題為”GROUP-ΠΙ NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER”之美國專利公開案第 2002/0167023A1號中,該案之揭示内容以如同本文完全陳 述之引用的方式倂入本文中。因此,不應將本發明之實施 例解釋為限制該障壁層為單一層,而應可包括(例如)具有 GaN、AlGaN及/或A1N層之組合之障壁層。舉例而言,可 使用GaN、Α1Ν結構以減少或防止合金散射。因此,本發 明之實施例可包括氮化物基障壁層,此等氮化物基障壁層 可包括AlGaN基障壁層、A1N基障壁層及其組合。 在該等圖式及說明書中,已揭示本發明之典型實施例, 且儘管已使用了特定術語,但是該等術語僅以通用及描述 之意義來使用且並非用於限制之目的。 【圖式簡單說明】 圖1A-1F為說明根據本發明之某些實施例之電晶體之製 100909.doc -25·
Claims (1)
1375326 第094112478號專利申請案 • ·'· 中文申請專利範圍替換本(101年4月) 十、申請專利範圍: 1. 一種製造一高電子遷移率電晶體(HEMT)之方法,其包 含: 形成一障壁層; 於該障壁層上形成一覆蓋層; 於該覆蓋層中形成歐姆接觸凹槽; 於該等歐姆接觸凹槽令形成歐姆接觸材料圖案; 於該覆蓋層中形成一延伸至該障壁層之閘極凹槽; ^ 於該覆蓋層上、該等歐姆接觸材料圖案上及該閘極凹 槽中形成一封裝層; 退火該障壁層、該等歐姆接觸材料圖案及該具有該閘 極凹槽之覆蓋層,該等歐姆接觸材料圖案係第一次退 火; 移除該封裝層;及然後 於該退火之閘極凹槽中形成一閘極接觸。 φ "^凊求項1之方法,纟中退火該障壁層、該等歐姆接觸 材料圖案及該具有該閘極凹槽之覆蓋層包含在一至少約 700 (:之/现度下退火該障壁層、該等歐姆接觸材料圖案及 該具有該閘極凹槽之覆蓋層。 3. 如請求項1之方法,其中該封裝廣包含A1N。 4. 如請求項1之方法,其中形成-閘極凹槽包含: 於該覆蓋層上圖案化一遮罩層以具有一對應於該閘極 凹槽之開口;及 將該圖案化遮罩層用作一蚀刻遮罩來触刻該覆蓋層以 100909-1010416.doc 1375326 提供該閘極凹槽。 5. 如請求項1之方法,其中該閘極接觸包含一肖特基 (Schottky)接觸 β 6. 如請求項1之方法,其中形成一覆蓋層包含於該障壁層 上形成一 GaN層。 7·如請求項1之方法,其中形成一覆蓋層包含: 於該障壁層上形成一GaN層;及 於該GaN層上形成一siN層。 8.如請求項7之方法,其中該SiN層係於原位形成。 9·如請求項1之方法,其中形成一閘極凹槽包含形成一延 伸穿過該覆蓋層且進入但未通過該障壁層之閘極凹槽。 10. 如請求項1之方法,其中該覆蓋層包含一 GaN基半導體材 料。 11. 一種製造一高電子遷移率電晶體(HEMT)之方法,其包 含: ’、 形成一障壁層; 於該障壁層上形成一覆蓋層; 於該覆蓋層中形成歐姆接觸凹槽; 於該等歐姆接觸凹槽中形成歐姆接觸材料圖案丨 於該覆蓋層t形成一延伸至該障壁層之閘極凹槽; 於該覆蓋層上、該等歐姆接觸材料圖案; 槽中形成一封裝層; mu 退火該障壁層、該等歐姆接觸材料圓案及該具有該間 極凹槽之覆蓋層,該等歐姆接觸 ° 订料圖案係第一次退 J00909-J010416.doc •2- 1375326 火;及然後 於該退火之閉極凹槽φ芬彡4、 甲形成—閘極接觸; 其中形成一閘極接觸包含: 於該覆蓋層上圖荦仆一说+ 固系化遮罩層以具有一對應於該閘極 凹槽之開口;及 將該圖案化遮罩層用 尤早增用作一姓刻遮罩來蝕刻該覆蓋層以 提供該閘極凹槽;及 其中形成該封裝層包含於該圖案化遮罩層及該閘極凹 槽上形成該封裝層,且其中在退火之後使用—自對準起 離(lift-off)技術來移除該遮罩層及該封裝層,以便提供 餘留在該閘極凹槽中之該封裝層之一部分。 12.如請求項11之方沐,甘 &万击其中該封裝層包含AIN、SiN、 S1O2、氮氧化物及/或一 〇N〇結構。 U· 項11之方法’其進—步包含在形成該閘極接觸之 前移除該閘極凹槽中之該封裝層之該部分。 14. 如請求項13之方法,其進一步包含: 於該覆蓋層上及該閑極凹槽中形成一絕緣層;且 其中形成該閘極接觸包含於該閘極凹槽中之該絕緣層 上形成該閘極接觸。 15. 如凊求項14之方法,其中該閘極接觸亦在該覆蓋層上之 該絕緣層上延伸。 16. —種製造一高電子遷移率電晶體之方法,其包含: 於基板上形成GaN基半導體材料之一第一層; 於該第一層上形成GaN基半導體材料之一第二層,該 I00909-I010416.doc 1375326 第一層係組態為在一接近該第一層與該第二層間之一介 面之區域中感應一二維電子氣; 於該GaN基半導體材料之第二層上形成GaN基半導體 材料之一第三層; 於該GaN基半導體材料之第三層中形成歐姆接觸凹 槽; 於該等歐姆接觸凹槽中形成歐姆接觸材料圖案; 於該第三層中形成一延伸至該第二層之閘極凹槽; 退火該第一層、該第二層歐姆接觸材料圖案及該具有 該閘極凹槽之第三層,該等歐姆接觸材料圖案係第一次 退火;及然後 於該退火之閘極凹槽中形成一閘極接觸。 17. 如請求項16之方法,其中退火在於該GaN基半導體材料 之第二層上及該閘極凹槽_形成一封裝層之後進行,且 其中在形成一閘極接觸步驟之前移除該封裝層。 18. 如請求項π之方法,其中形成一閘極凹槽包含· 於該GaN基半導體材料之第三層上圖案化一遮罩層以 具有一對應於該閘極凹槽之開口; 將該圖案化之遮罩層用作一蝕刻遮罩來蝕刻該GaN基 半導體材料之第三層以提供該閘極凹槽; 其t形成該封裝層包含於該圖案化之遮罩層及該閘極 凹槽上形成該封裝層,•且 其t在退火之後使用一自對準起離技術來移除該遮罩 層及該封裝層以便提供餘留在該閘極凹槽中之該封裝層 100909-1010416.doc -4- 之一部分。 19·如請求項18之方法,其中該封裝層包含Am。 2。·二請求項18之方法,其進一步包含在形成該 前移除餘留在該閘極凹槽中之該封裝層之該部分。觸之 21_如請求項20之方法’其進一步包含: 層於:^基材料之第三層上及該凹槽中形成一絕緣 二中形成該閘極接觸包含於該閘極凹槽中之該絕緣層 上形成該閘極接觸。 •項21之方法,其中該閘極接觸亦形成於該GaN基 材料之第二層上之該絕緣層上。 23·如請求項之古 ^ 万法’其中該閘極接觸包含一 T形閘極结 構。 24.如請求項16之 法:’其中形成一閘極凹槽包含形成一延 咬、Μ第三層且進入但不穿過該第二層之閘極凹槽。 月求項16之方法,其中該閘極接觸為一肖特基接觸。 26_如請求項16 万法,其中形成歐姆接觸凹槽在於該GaN 土材:之第二層上原位形成-鈍化層之後進行。 27·種㈤電子遷移率電晶體(HEMT) ’其包含: 一障壁層; 、 該障壁層上之-覆蓋層; 該覆蓋層Φ 續宁之一延伸至該障壁層之閘極凹槽; 該間極ρη她I W糟中之一閘極接觸,其中在該障壁層、該覆 〜間極凹槽退火之後接近該閘極凹槽之該障壁層 100909-1010416.doc 1375326 之一薄片電阻係與該障壁層之一薄片電阻相同。 28. 如請求項27之HEMT,其進一步包含該覆蓋層中之歐姆 接觸凹槽中之歐姆接觸材料圖案,其中該等歐姆接觸材 料圖案係與該障壁層、該覆蓋層及該閘極凹槽同時退 火。 29. 如請求項28之HEMT,其進一步包含該覆蓋層上之一封 裝層、該等歐姆接觸材料圖案及該閘極凹槽。 30. 如請求項28之HEMT,其進一步包含一通道層,其中該 障壁層係於該通道層上,且其中該通道層係與該障壁 層、該等歐姆接觸材料圖案、該覆蓋層及該閘極凹槽同 時退火。 3 1.如請求項27之HEMT,其中該閘極接觸包含一肖特基 (Schottky)接觸。 32.如請求項27之HEMT,其中該覆蓋層包含該障壁層上之 一 GaN層。 3 3.如請求項27之HEMT,其中該覆蓋層包含: 該障壁層上之一 GaN層;及 該GaN層上之一 SiN層。 34. 如請求項33之HEMT,其中該SiN層係於原位形成。 35. 如請求項27之HEMT,其中該閘極凹槽延伸穿過該覆蓋 層且進入但未通過該障壁層。 36. 如請求項27之HEMT,其中該覆蓋層包含一 GaN基半導 體材料。 100909-1010416.doc 1375326 第094112478號專利申請案 中文圖式替換頁(101年4月 封裝層 44 ΈΜΜ Μ 歐姆接觸 30
1 覆躉層\: 障壁層 2Ζ通道層 20 10 圖1Ε 歐姆接觸 2Q
圖1F 100909-fig-1010416.doc
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2004
- 2004-07-23 US US10/897,726 patent/US7238560B2/en active Active
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- 2005-03-30 JP JP2007522484A patent/JP5355888B2/ja active Active
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- 2005-03-30 CN CN2005800246157A patent/CN1989601B/zh active Active
- 2005-03-30 EP EP18190841.9A patent/EP3425674A3/en active Pending
- 2005-03-30 KR KR1020077001309A patent/KR101108344B1/ko active IP Right Grant
- 2005-03-30 WO PCT/US2005/010874 patent/WO2006022874A1/en active Application Filing
- 2005-04-19 TW TW094112478A patent/TWI375326B/zh active
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Cited By (6)
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US9755044B2 (en) | 2014-05-30 | 2017-09-05 | Delta Electronics, Inc. | Method of manufacturing a transistor with oxidized cap layer |
US9793370B2 (en) | 2014-05-30 | 2017-10-17 | Delta Electronics, Inc. | Transistor with oxidized cap layer |
TWI794599B (zh) * | 2020-03-24 | 2023-03-01 | 世界先進積體電路股份有限公司 | 高電子遷移率電晶體及其製作方法 |
US11380767B2 (en) | 2020-04-28 | 2022-07-05 | Vanguard International Semiconductor Corporation | High electron mobility transistor and fabrication method thereof |
US11929407B2 (en) | 2020-04-28 | 2024-03-12 | Vanguard International Semiconductor Corporation | Method of fabricating high electron mobility transistor |
TWI755277B (zh) * | 2021-02-09 | 2022-02-11 | 世界先進積體電路股份有限公司 | 高電子遷移率電晶體及其製作方法 |
Also Published As
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CN1989601A (zh) | 2007-06-27 |
KR101108344B1 (ko) | 2012-01-25 |
EP3425674A2 (en) | 2019-01-09 |
US20060019435A1 (en) | 2006-01-26 |
CA2572244C (en) | 2014-01-28 |
US7238560B2 (en) | 2007-07-03 |
EP3425674A3 (en) | 2019-05-15 |
US20070254418A1 (en) | 2007-11-01 |
CN1989601B (zh) | 2012-06-20 |
US9666707B2 (en) | 2017-05-30 |
US7678628B2 (en) | 2010-03-16 |
CA2572244A1 (en) | 2006-03-02 |
WO2006022874A1 (en) | 2006-03-02 |
JP2008507843A (ja) | 2008-03-13 |
TW200605350A (en) | 2006-02-01 |
US20100140664A1 (en) | 2010-06-10 |
EP1771876B1 (en) | 2018-09-26 |
EP1771876A1 (en) | 2007-04-11 |
KR20070032790A (ko) | 2007-03-22 |
JP2012142595A (ja) | 2012-07-26 |
JP5355888B2 (ja) | 2013-11-27 |
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