KR880010509A - 전계효과 트랜지스터 - Google Patents

전계효과 트랜지스터 Download PDF

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KR880010509A
KR880010509A KR870001712A KR870001712A KR880010509A KR 880010509 A KR880010509 A KR 880010509A KR 870001712 A KR870001712 A KR 870001712A KR 870001712 A KR870001712 A KR 870001712A KR 880010509 A KR880010509 A KR 880010509A
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layer
channel
disposed
field effect
effect transistor
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KR870001712A
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안트레아시안 아삼
아담 가빈스키 폴
다니엘 마테라 2세 빈센트
템킨 헨리크
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오레그 이. 앨버
아메리칸 텔리폰 앤드 텔레그라프 캄파니
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Publication of KR880010509A publication Critical patent/KR880010509A/ko

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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Abstract

내용 없음

Description

전계효과 트랜지스터
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도면은 본 발명에 부합되는 실시예의 개략도.

Claims (5)

  1. 최소한 하나의 반 절연 표면층을 가진 본체(12)를 구비하는 전계효과 트랜지스터(10)에 있어서, 반 절연 표면층 상에 배치되며 낮게 도프되는 InP형 적층성장 채널층(14)과, 높게 도프되는 InGaAs형의 적층성장 접촉중개층(18)과, 접촉중계층으로부터 채널로 도판트 불순물이 확산되는 것을 방지하기 위해 상기 채널과 접촉 중개층 사이에 배치되는 낮게 도프된 InGaAs형 적층성장 배리어층(16)과, 상기 접촉 중개층에 소오스 및 드레인 접촉부를 형성시키는 수단(40,50)과, 상기 채널과 사이 소오스와 드레인 접촉부 사이에서의 전류흐름을 제어하기 위한 게이트 전극수단(30)을 구비하는 것을 특징으로 하는 전계효과 트랜지스터.
  2. 제1항에 있어서, 상기 게이트 전극수단은 상기 채널층 부분을 노출시키는 상기 InGaAs형 층에 형성된 홈과, 최소한 상기 부분상에 배치된 유전체층과 상기 유전체층상에 배치된 금속층을 포함하는 것을 특징으로 하는 전계효과 트랜지스터.
  3. 제2항에 있어서, 상기 접촉 형성 수단은 상기 홈의 양편상에 상기 접촉 중개층에 대한 옴 금속 접촉부를 포함하는 것을 특징으로 하는 전계효과 트랜지스터.
  4. 제1,2 또는 3항에 있어서, 상기 채널 및 배리어층은 Wig 1015cm-3미만의 캐리어 농도를 가지는 것을 특징으로 하는 전계효과 트랜지스터.
  5. 여기 모드 전계효과 트랜지스터에 있어서, 최소한 하나의 반-절연 표면층을 가진 InP단 결정체와, 상기 표면층사이에 배치되며 Wig 1015cm-3미만의 캐리어 농도를 가지며 비의도적으로 도프된 InP적층성장 채널층과, 높게 도프된 n타입 In0.53Ga0.47As적층 성장 접촉 중개층과 상기 채널층과 상기 접촉 중개층 사이에 배치되어 도판트 불순물아 상기 접촉 중개층에서 상기 채널층으로 확산되는 것을 방지하며 비의도적으로 도포된 In0.53Ga0.47As 적층성장 배리어층과, 상기 채널층의 한 부분을 노출시키며 관통하는 홈을 가진 In0.53Ga0.47As층과, 상기 홈의 대향편상의 상기 접촉 중개층상에 배치되는 소오스 및 드레인 옴 접촉부와, 최소한 상기 부분상에 배치되는 SiO2층과, 상기 소오스와 드레인 접촉부 사이에 흐르는 전류를 조정하기 위해 상기 SiO2층상에 배치되는 게이트 금속전극을 구비하는 것을 특징으로 하는 전계효과 트랜지스터.
    ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR870001712A 1987-02-11 1987-02-27 전계효과 트랜지스터 KR880010509A (ko)

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US1332887A 1987-02-11 1987-02-11
US013328 1987-02-11

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US5138408A (en) * 1988-04-15 1992-08-11 Nec Corporation Resonant tunneling hot carrier transistor
FR2632452B1 (fr) * 1988-06-03 1990-08-17 Labo Electronique Physique Procede de realisation de couches epitaxiales
US5012318A (en) * 1988-09-05 1991-04-30 Nec Corporation Hybrid semiconductor device implemented by combination of heterojunction bipolar transistor and field effect transistor
JP2687519B2 (ja) * 1988-12-06 1997-12-08 日本電気株式会社 半導体装置及びその製造方法
US5041393A (en) * 1988-12-28 1991-08-20 At&T Bell Laboratories Fabrication of GaAs integrated circuits
US5132764A (en) * 1991-03-21 1992-07-21 Texas Instruments Incorporated Multilayer base heterojunction bipolar transistor
JPH04335538A (ja) * 1991-05-10 1992-11-24 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5334865A (en) * 1991-07-31 1994-08-02 Allied-Signal Inc. MODFET structure for threshold control
JP2735718B2 (ja) * 1991-10-29 1998-04-02 三菱電機株式会社 化合物半導体装置及びその製造方法
JPH10150185A (ja) * 1996-11-20 1998-06-02 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH10223651A (ja) * 1997-02-05 1998-08-21 Nec Corp 電界効果トランジスタ
US6594293B1 (en) * 2001-02-08 2003-07-15 Amberwave Systems Corporation Relaxed InxGa1-xAs layers integrated with Si
US6963090B2 (en) * 2003-01-09 2005-11-08 Freescale Semiconductor, Inc. Enhancement mode metal-oxide-semiconductor field effect transistor
US7238560B2 (en) * 2004-07-23 2007-07-03 Cree, Inc. Methods of fabricating nitride-based transistors with a cap layer and a recessed gate
US9048302B2 (en) * 2008-01-11 2015-06-02 The Furukawa Electric Co., Ltd Field effect transistor having semiconductor operating layer formed with an inclined side wall
US9093532B2 (en) 2013-06-21 2015-07-28 International Business Machines Corporation Overlapped III-V finFET with doped semiconductor extensions

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US4479222A (en) * 1982-04-27 1984-10-23 The United States Of America As Represented By The Secretary Of The Air Force Diffusion barrier for long wavelength laser diodes
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