TWI300619B - Electronic device - Google Patents

Electronic device Download PDF

Info

Publication number
TWI300619B
TWI300619B TW095102077A TW95102077A TWI300619B TW I300619 B TWI300619 B TW I300619B TW 095102077 A TW095102077 A TW 095102077A TW 95102077 A TW95102077 A TW 95102077A TW I300619 B TWI300619 B TW I300619B
Authority
TW
Taiwan
Prior art keywords
metal film
metal
electrode
substrate
interface
Prior art date
Application number
TW095102077A
Other languages
English (en)
Other versions
TW200723494A (en
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of TW200723494A publication Critical patent/TW200723494A/zh
Application granted granted Critical
Publication of TWI300619B publication Critical patent/TWI300619B/zh

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65G—TRANSPORT OR STORAGE DEVICES, e.g. CONVEYORS FOR LOADING OR TIPPING, SHOP CONVEYOR SYSTEMS OR PNEUMATIC TUBE CONVEYORS
    • B65G1/00—Storing articles, individually or in orderly arrangement, in warehouses or magazines
    • B65G1/02—Storage devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8381—Soldering or alloying involving forming an intermetallic compound at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8382—Diffusion bonding
    • H01L2224/83825—Solid-liquid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01065—Terbium [Tb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)
  • Multi-Conductor Connections (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

1300619 九、發明說明： 【發明所屬之技術領域】 本發明係關於以車載用電源模組為代表之電子裝置，其 係關於將半導體元件等電子零件實際裝設於基板之構造。 【先前技術】 基於環保考量，如以油電動力混合車為代表的電動馬達 驅動的汽車今後應會越加普及。此外，以往以油壓控制的 動力方向盤或煞車系統等，也傾向採用利用電動馬達的電 力控制單元（Electric Control Unit，ECU)。控制馬達用的 ECU使用大量電流通過之IGBT晶片（insuiated Gate Bipolar
Transistor)或 FET晶片（Field Effect Transistor)，此晶片（半 導體晶片等電子零件）會發出數十瓦到數百瓦的熱能。因 此’這些晶片或是具備這些晶片的電子裝置，都需要水冷 系統或疋氣冷系統進行冷卻。圖1所示之馬達控制用ECU 模組的剖面構造之一例中，此FET晶片丨下方之汲極，以焊 錫3連接至高溫傳導的陶瓷基板7之電極$上，此陶瓷基板7 係以高溫傳導的樹脂黏著劑11黏著於散熱裝置上。FET晶 片1的上方閘極電極及源極電極，係以多數的烊接線丨3連 接至陶曼基板7上之特定電極15。此種需要多數焊接線的 電子裝置構造，其製程需要龐大的設備投資，同時製程本 身也A花費長時間及高成本。此外，由於焊接線用的電極 15表面需要保持清潔，因此晶片1焊接連接於基板7後，需 要另行進行洗淨工程。 由於近來電子裝置（例如動力模組）上所裝載之FET晶片 108113.doc 1300619 發熱量有增加趨勢，因此其構造需要更優異的散熱性。此 種需求不限於汽車用電子裝置（車載用電源模組），在鐵道 車輛變頻器、發電機、照明器具或加熱器具的控制系統等 中所使用的其他電子裝置亦相同。在此種電子裝置的製程 中’如能省略上述焊接線工程，將可大幅度的減低製作成 本。 根據如圖2所示之既有電子裝置構造，即可達成上述目 標。亦即，基板7使用熱傳導率高的陶瓷，以焊錫5將晶片 1裝載於該陶瓷基板7上，再將此陶瓷基板7以焊錫連接於 散熱用的散熱裝置19上。通常會用來取代焊接線的連接材 料’使用Cu(銅）等熱傳導性優良的材料所形成的金屬製框 21 ’將其與晶片電極與基板7上的電極23焊接連接。 此外，下述非專利文件1中亦揭示了焊接技術的相關報 告。 [非專利文獻 l]Ricky W· Chuang 等，51th Electronic
Components and Technology Conference，P.671-674
Note :專利文獻1中對應外國申請未被擷取。 【發明内容】 在實現圖2所示之構造的製程上，面臨著以下課題。首 先’焊接連接部從以往的1階層加大為3階層。在此，即使 為複數焊接連接部，只要是可同時連接而無問題的部位， 將稱為1階層焊接連接部。對於此種具有多階層焊接連接 部的構造，必須以適當的順序完成焊接連接。例如，首先 以焊錫A形成晶片1與基板7的連接部3，接著以焊錫b同時 108113.doc 1300619 各自形成晶片1與金屬框21的連接部25、以及設於基板7上 的電極15與金屬框21的連接部23。最後，以焊錫C連接基 板7與散熱裝置19(代替上述樹脂黏著劑之連接部u)。假設 不使用3種焊錫A〜C，而欲使用同一焊錫連接時，除了因 金屬框21旋轉等造成的連接位置偏移、晶片1旋轉等造成 的連接位置偏移之外，還可能發生上述焊接連接部的斷線 (或導電不良）、電性短路等各式問題。此外，如以同一焊 錫依上述順序連接，則電子裝置將承受最多3次的加熱， 因此設置於其之連接部（該焊接材料層）與電極間所產生之 金屬間化合物的量將增多，產生電子裝置信賴性低的問 題。 如使用A〜C三種焊錫，即可解決此種問題。例如，焊錫 A可用Pb(錯）-10% Sn(錫）（熔點：約320°C )、焊錫B可用Sn- 3% Ag(銀）-〇·5〇/0 Cu(熔點：約 217。〇、焊錫 C可用 Sn-37%
Pb(熔點：183 °C)，即可不產生上述問題，依上述順序將 上述晶片1與基板7、晶片1及基板7的電極1 5與金屬框2 i， 以及基板7與散熱裝置19依序連接組裝成電子裝置。然 而，由於市場上需求未包含Pb焊錫材料的電子裝置，上述 將不同熔點的3種焊錫組合製造而成的電子裝置即失了市 場價值，即便僅以未包含扑焊錫材料取代該焊接材料之組 合來製造電子裝置，要確保其信賴性亦十分困難。 面對此種問冑，如利㈣如上述非專利文獻以斤揭示之 技術，理論上可僅使用未包含pb之焊錫材料進行上述3階 層的連接。亦即，在電子零件端電極上形成〇〇3以瓜厚度 108113.doc 1300619 的Cr(鉻），於其上形成互相相接之5 μιη的Sn及1.11 μηι厚度 的In(銦），此層積構造的最表面形成〇 〇5 μιη厚度的 Au(金）。基板端電極上，形成〇 〇3 μη1厚度的Cr，Cr層的 最表面形成Au0.05 μηι。在適當條件下，以Sn與In的共晶 溫度（118°C)以上、例如以i5〇°c加熱，在Sn與In界面附近 引起溶融，再於固相的Sn全體進行“的擴散完成連接。連 • 接部之Sn與In合金部分，由於呈現Sn較強的組成，故該合 金部分的溶點上升，例如在175〇c以下的溫度即不會再次 > 溶融。 相較於行動通訊機器等民生用品，更需要高信賴性的車 用電子機器’若使用上述連接方式將產生下述問題。首先 ’ 關於Sl晶片（石夕材質所形成之電子零件）與基板連接的電子 裝置，該電子裝置（其中包含的矽晶片與基板之連接部）之 石夕晶片與基板連接時的溫度冷卻至室溫之過程中，會發生 矽與基板的熱膨脹率差異所導致的矽晶片破壞。此外，基 • 板與散熱金屬板（散熱裝置）之連接中，該電子裝置的大氣 溫度以一週期-55〜i5(rc為範圍令其變化，僅重複進行1〇〇 • 次以下的耐久溫度循環測試，亦會由於基板與放熱金屬板 • 熱膨脹率的差異，在此等之間的連接層内產生破壞。 本發明為了貝現可以多階層焊接連接部組成實際裝設構 化之電子衣置，且為了提高此等焊接連接部之信賴性，提 供下列方法。 亦即，為減少因晶片等構件與其連接以及固定的相關埠 伤產生的應力、變形，本發明增加兩個構件γ間所形成之 108113.doc 13〇〇619 連接部的厚度（高度）。如同之後的實施例中所詳述，此兩 種構件，例如Si晶片與基板上各自形成組成不同的金屬 層，在藉由令此等金屬層互相接觸，使雙方金屬層的構成 元素擴散，而令該二種材料連接之方式中，本發明以鍵敷 方式，令該二種構件之至少一方（例如Si晶片端或基板端） 上之金屬層增厚。藉此，可充分確保兩種構件上各自設有 的金屬層所形成之連接部（連接層）之最後連接厚度，令該 連接部吸收上述應力及變形，可因此避免例如Si晶片或連 接部的破壞。此外，實施本發明所需的上述金屬層鍍敷工 程之時間及相關成本之增加都極微少。 上述非專利文獻1中所揭示的技術，因以濺鍍法於電子 零件與基板雙方形成上述金屬層，故實際上要形成各個金 屬層為數微米以上的厚度有其困難。本發明係有鑒於非專 利文獻1中疏忽未探討的連接部信賴性（例如耐溫度變化性） 問題，提供一個適於實現堪於實用的電子裝置之構造。 根據本發明之一例，係具備：電子零件，其係具有第i 電極與形成於此第1電極表面之至少一層的第丨金屬膜者； 以及基板，其係具有與上述電子零件之上述第丨電極電性 連接的第2電極，與形成於此第2電極表面的至少一層之第 2金屬膜。上述電子零件與上述基板，係令上述第丨金屬膜 的最表面與上述第2電極的最表面相接觸，在第1金屬膜及 第2金屬膜各自的熔融溫度以下、且為第丨金屬膜及第2金 屬膜的共晶溫度以上令其熔融，由第丨金屬膜及第2金屬膜 的擴散反應，在界面附近形成含有第、金屬膜及第2金屬膜- 108113.doc 1300619 各自構成元素之合金部分藉以連接。上述電子零件與上述 基板連接後之上述合金部分的熔融開始溫度，從電子零件 與基板連接時之上述界面附近的上述第丨金屬膜與上述第2 金屬膜之熔融開始溫度提升（升高）。且上述第丨金屬膜與上 述第2金屬膜之至少一方，包含由鍍敷形成之至少一層的 金屬層。 上述第1金屬膜及第2金屬膜之至少一方，包含因鍍敷形 成之至少一層金屬層，取代上述’亦可為第丨金屬膜及第2 金屬膜之至少一方，包含形成為1〇微米以上厚度之一層金 屬層。另外’由第丨金屬膜及第2金屬膜在電子零件與^板 間所形成之連接部的厚度可令其為2〇微米以上。 電子零件與基板例示為應連接的一對構件之一例。第^ 金屬膜及上述第2金屬膜並不限定為由一層金屬層所形 成’亦可為其-方或雙方為層積相異材料所形成的複數金 屬所形成。 上述電子裝置的構造性特徵之一例，有例如上述約金 屬膜與上述第2金屬膜所接觸之界面附近存在之安定的金 屬間化合物。 上述電子零件，使用與形成上述第j電極之主面相反的 置上诚：上心成有第3電極之Sl功率元件’在上述基板設 電性二Γ之主面上’以金屬引線形成與上述第3電極 第4電極時，於上述引線上形成上述第i全屬 !上:=第3電極形成上述第2金屬膜。接著令上述引線 ，、述弟3電極上各自形成之上述幻金屬臈的最表面與上〜 108113.doc 1300619 電極的最表面相接觸，在上述溶融溫度以下且第1金 腔# 膜取表面接觸之界面附近，以第1及第2金 、之共晶溫度以上之溫度令其熔融，由第i金屬膜與第2 =膜之擴散反應，在界面附近形成包含第工金屬膜與第2 孟膜各自構成元素的合金部分藉以連接’上述引線盘上 =3電極連接後的上述合金部分之溶融開始溫度，高於
引線與第3電極連接時於上述界面附近之上述第以屬膜與 上述第2金屬膜的熔融開始溫度。 述根據本發明之電子裳置之一例，為擁有不同熱膨服 率之請件與第2構件，“由挾著主面之接合層所接 〇接口層係由至少由第1金屬即與該第^金屬相異之第 2金屬所形成的電子裝置中，例如下述說明。第】，該接合 層之第1金屬的濃度’在對接合層的厚度方向(第】構件主 面到弟2構件主面之方向）之中心、偏向第2構件端較低。第 2—’對上述接合層之厚度方向，上述^構件區域包含上述 第1金屬與上述第2金屬的濃度比相異之兩種共晶組織(結 晶粒對其厚度方向之中心偏向第2構件之其他區域上殘 留有第2金屬之組織（結晶粒）。帛3，上述接合層至少包含 包s上述第1金屬及上述第2金屬之複數固溶體組織，與第 1金屬和，2金屬濃度比相異之兩種共晶組織，&共晶組織 係各複數個分離存在於複數個固溶體組織（結晶粒）之間。 根據本發明之電子裝置的其他例，係、具備基板；裝載於 基板-方的主面上之Si功率元件；以及連接基板另一主面 之金屬板，形成於與上導以功率元件之上述基板的一方主 108113.doc -11 - 1300619 面相反端的面之第！電極與：形成於基板一方之主面的第2 電極以導電金屬材料電性連接。而導電金屬材料與第2電 極間’插入金屬製隔離物，導電金屬材料上不對上述基板 之厚度方向施加彎曲加工。 藉由本發明，可提供具有足夠信賴性電子裝置，且可降 低製造成本。 【實施方式】 以下’說明本發明之實施形態。 實施例1 以下將以適於實現具有充分信賴性之馬達控制用電性控 制單元（以下簡稱為ECU)之實施例說明本發明之電子裝 置。· " 首先’圖4顯示於5 mm、0.3 mm厚度的Si基材上形成 MOS-FET(Metal-Oxide Semiconductor Field Effect Transistor)的電子零件（以下稱為m〇S-FET晶片或Si晶片） 之模式圖。此MOS-FET晶片係為於Si基材1厚度方向形成 使載子（電子或電洞）流動之通道，而隔著此通道之兩個電 極（源極電極與汲極電極）各自形成於Si基材1之兩個主面 (圖4中為上面及下面）。再者，控制通道中載子流動的開極 於圖4中加以省略。具有此種構造之m〇S_Fet晶片在例如 功率模組等中，用作開關大電流之功率元件。 作為MOS-FET晶片的源極電極，係於μ基材1 一方的主 面（上面）所形成之銘t〜極25上，以3 μπι厚〜度形成鍍 Ni(鎳如，以〇·〇5 μηι厚度形成鍍Au(金阳。於Si晶片、背面 108113.doc -12- 1300619 (Si基材1另一方之主面、上述一方主面之相反側）上作為汲 極電極所形成之Ag電極27上，也同樣以3 μπι厚度形成鍍犯 29 ’以〇·〇5 μπι尽度形成鍍Au 3 1。此處鍍Ni及Au係由無電 解鍍敷形成。較厚形成此鍍錄，將可提升連接部的信賴 性，因此進行鍍敷將可加速鍍敷形成速度，可降低Si晶片 的製造成本。 接著，圖5顯示裝載上述MOS-FET晶片之基板的模式 圖。基板使用由熱傳導率南的Si^4(氮化石夕）所形成之厚度 0.3 mm之陶瓷板7作為絕緣層，於該陶瓷板（之後亦只稱為 基板」）7的一方主面上形成厚度〇·5 mm的Cu 5的圖案作 為佈線以及電極層。於陶瓷板7的背面（陶瓷板7的另一方 主面、上述一方主面之相反側）上，為防止比陶瓷板7厚的 Cu 5之圖案造成陶瓷板（基板）7翹起，考慮Cu 5之佈線密度 及圖案之居度的Cu固體圖案9以例如〇·4 mm厚度形成。晶 片搭載用電極（Cu 5之圖案）及背面Cu固體圖案9各自再以 鍍敷形成厚30微米之Sn膜33。Sn膜33上用濺鍍法形成厚！ 微米之In膜35，再於in膜35上以濺鍍法形成防止表面氧化 用厚度0.05微米的Au膜31，。圖4顯示之MOS-FET晶片1， 其上述另一方的主面所形成之汲極電極27連接至基板（陶 甍板）7的上述一方之主面所形成之5圖案之一。 接著’圖6顯示連接於上述基板7之上述另一方主面（Cu 的固體圖案9)且亦發揮散熱裝置作用之金屬板（之後稱為基 底金屬）的模式圖。負責上述M〇s_FET晶片1的散熱及上述 基板7的補強之厚度$ mm的Cu底層37上之基板7搭載位〜置 108113.doc -13· 1300619 上’以鍍敷形成厚30微米之Sn膜33。在Sn膜33上以濺鍍法 形成厚1微米之In膜35，再於In膜35上以濺鍍法形成防止表 面氧化用厚度0.05微米的Au膜31’。另外，圖6中所揭示之
Cu底層37與Sn膜33中間的鍍Ni層29視需要不形成亦可。 連接Si晶片1的源極電極25(29、31)與基板7上的電極 5(33、35、31f)之構件的引線材料，使用Cu-M〇合金（例如 以：40%、Mo(鉑）·· 60%)。弓丨線材料厚度為〇·4顧，配合 後述分隔零件及晶片電極圖案，選擇性地在引線材料上鍍 敷形成厚度30微米的Sn膜。於其上以濺鍍法形成厚丨微米 之In，再於In膜上以濺鐘法形成防止表面氧化用厚度〇〇5 微米的Au膜。 为隔零件係與Si晶片大致相同厚度 零件，可不需彎曲引線材料之加卫，而進行源極電極25邀 基板的電極5之電性連接。如不使用分隔零件，由於以晶 片1上之墊片（例如例示為源極電極之構件25 H)與基 板上之墊片（例如例示為電極構件5、33、35、31，）之高度 差’將產生幾乎一個晶片的厚度’故在引線與晶片上的墊 片之間’及引線與基板上的塾片之間，以焊接連接（包含 除了本實施例之外的-般焊接連接)時，如圖3所示，須對 引線進行彎曲加工，传复 2 ’、吸收上述高度差。本發明者發 際上進仃’’弓曲加工過的引線，有可能發生斷裂不良。 此不良會帶來良品率降低造成的成本增加問題’因此，採 用分隔零件與不需彎曲加工 置之信賴性。 <引線的組合，可提升電子裝 108113.doc -14- 1300619 圖7顯示上述分隔零件的模式圖。此分隔零件與引線相 同擁有由Cu-Mo合金（例如Cu : 4〇0/〇，M〇(铜）·· 6〇%)戶斤 形成之厚度G.3 mm的基材（BlQek)39。此基材39的兩面，亦 即刀隔零件上與引線之連接面及與基板之連接面上，分別 形成厚3微米的Ni鍍敷層29、及厚〇 〇5微米的Au鍍敷31。 如上所述’電極或與其類似之金屬構件25、27、5、9、 29、39上，以鍍敷法或濺鍍法形成金屬層之&晶片i、基 板7、金屬板37、分隔零件39各自如下互相連接。首先， 在基板7上將Si晶片1與分隔零件39，搭載於設於基板7之 上述一方的主面之墊片（5、33、35、3丨，）上，在氫還原環 i兄中以150 C加熱30分鐘。此工程簡示於圖8。si晶片 /及極電極27以及分隔零件（基材）39各自連接基板7的電極 5，汲極電極27以及分隔零件（材料）39與基板7的電極5之間 所挾之Ni鍍敷層29的一部分，八11層31、31，、化膜35，以 及Sn鍍敷層33所形成之層積構造，以Sn-In合金為主成 分，變為包含Ni、Sn-Ni化合物、Au-Sn化合物，以及Au-In化合物之金屬層41。 此金屬層41因宏觀看來具有sn較多之組成，令上述以晶 片1以及分隔零件39連接至基板7上時（初期連接時）之溶融 溫度，較上述層積構造的熔融溫度（15(rc左右）高。圖9(a) 顯示Si晶片1與以及分隔零件39連接至基板7後之構造，上 述金屬層41與Ni鍍敷層29共同顯示為連接部43(汲極電極 27因過薄而省略）。在此種於基板7上連接si晶片丨與分隔零 件3*9之構造中，可確認、並不會發生Si晶片1的破裂等破 108113.doc •15- 1300619 壞。 接著如圖9⑻所示，將引線21(例如以金fg或金屬板的形 式提供）從si晶片丄上的墊片（25、29、31)橫跨到分隔零件 39之墊片（29、31)上而配置’在與上述連接工程相同條件 下加熱（氫還原環境下、15(TC、30分鐘）。此時，基板7與 Si晶片i及分隔零件39之間的連接部41，如上述由於熔融 溫度上升，故不會熔融。此外，圖9(b)顯示引線21連接以 晶片1及分隔零件39連接後之構造’因各自的連接部44， 係由Si晶片1以及分隔零件39所形成之Ni鍍敷層29以及Au 層31，及引線21所形成之Sn鍍敷層（厚度30微米）、比膜（厚 度1微米），以及Au鍍敷膜（厚度〇.05微米）的熔融而相互擴 散所形成（源極電極25由於過薄而省略）。 再者，如圖9(b)所示，Si晶片1、分隔零件39與引線21連 接之基板7，如圖9(c)所示，搭載於上述金屬板（Cu底層）3 7 之特定位置（29、33、35、31，）上，同樣以15〇°c加熱30分 鐘。之Θ所形成之連接部43、44，於此加熱過程亦不會溶 融。基板7之上述另一方主面所形成的金屬層（Cu固體圖案 9、亦可於佈線上製備圖案）與金屬板37之間，因形成於金 屬層9上之Sn鍍敷層33、In膜35、以及Au層3Γ，以及形成 於金屬板37上之Ni鐘敷層29、Sn鍍敷層33、In膜35，以及 Au膜3Γ熔融而相互擴散所形成連接部45。 最後，將固定於金屬板37上之基板7、Si晶片1、分隔零 件39、引線21全部，如圖9(d)所示用樹脂17成型。此一連 串製程的概略示於圖9(a)至（9d)，其結果可得之最終構造 108113.doc -16- 1300619 示於圖ίο 顯示。 但圖10中省略了上述連接相 關之金屬層的詳細 _以上’與連接部43的厚度為5微米的模組相較，發現令 此為ίο微米的模組之信賴性提升兩倍以上，令此為3〇微米 的模組之信賴性提升五倍以上。同樣地，對其他連接部 44 45 ’令連接部厚度為1〇微米以上，可提升模組信賴性 如此完成之模組示於（參照圖10)中，對每一周期賦予 55〜15(TC的溫度變化重複進行刚週期的溫度循環測試。 其結果’在上述連接部43、44、45並未發生破壞或不良， 可確認該模組具有充分信賴性。另外進行模擬測試的結 果’對晶片1與基板7的連接部43,尸、要晶片i的尺寸y 兩倍以上，作為車載機器極可能具有充分信賴性。 實施例2 關於本發明之電子裝置的其他實施例，將使用圖丨丨說明 如下。本貫施例之電子裝置（模組）與實施例丨之相異處為， 代替以絕緣材料構成之基板7，使用金屬底層（例如以底 層）47之一方主面以樹脂46絕緣之基板（簡稱為以底層基 板）。使用此Cu底層基板，係因電子裝置全體構造希望提 而散熱性之要求，而使用熱傳導率2 w/m.k以上之材料作 為絕緣樹脂46。於實施例丨中，基板内有底層金屬37，故 基板以外不需要另行設置其他散熱或補強用底層基板。因 此’可減少一層連接部的階層，可望減少製程並縮減成 本0 此外’如以具備AI金屬底層者取代上述Cu底層基板，其 108113.doc -17- 1300619 散熱性比起Cu底基板雖然稍差，伸 之 1 一了達到整體電子裝置 輊量化。 衣直 實施例3 在此，關於上述實施例丨及2將參昭 …、圖12考察本發 電 子裝置上連接部的特徵。 ％ Λ之电 相接合的兩種材質各有不同熱膨脹率時，其間所形成之 連接部（以下稱為接合層）厚度，將抑制該兩種構件= 方之熱膨脹（變形）對另一方造成之影響。如圖12(咖= Si晶片與基板的情況下’前者之熱膨脹率為石夕之教膨 率祈後者之t膨脹率受到基板的主要構成因素’例如陶竟 材貝、玻璃環氧材質、金屬板之埶膨 之熱膨脹率所影響。因此接 合層在工業上有時會被要求達到至少10㈣、 為 20〜100 μιη之厚度。此晟声t技分士 心的疋為 呈 子又L係依存於由電子裝置控制之 電k置以及其可利用之環境， 兄反映出例如動力模組中之弱 電機器内不會發生之構件溫度變化產生的變形。因此’各 自形成於圖12⑷所示的2種部材上，於其間如圖12⑻所 不，形成接合層之金屬A及與該金屬A相異組合之金屬3之 其中至少一方，理想的是由鑛敷方式形成。再者如有必要 金屬A與金屬_者皆由鑛敷形成亦可。非專利文獻i記載 之賤錢法，由於工紫L —Γ A. Λ . 、 ^不可此以充分之厚度形成此等金屬 A或金屬B之至少 方，故無法確保接合層厚度符合上述 要求。 另方面，在形成接合層之現象中，本發明亦不一定需 要如非專利文獻1所聞迷，藉由2種金屬之固相_液相擴 108113.doc 1300619 散，令接合層之組成一致。例如，接合層之組成只須變化 至其厚度方向（換言之，令相接合之兩種構件之一方朝向 另方），亦旎得到上述效果。令金屬A為Sn、令金屬B為 In，形成顯示Sn(85%)-In(15%)之熔融溫度接合層時，用非 專利文獻1的手法可充分進行金屬A與金屬B之擴散，故Sn_ In之固熔體（Gamma-Phase Solid Solution)的組織（結晶粒， 戈·疋的金屬間化合物）形成於接合層整體上，接合層同樣 地顯示該組成或其附近之組成。 另一方面’宏觀來看，本發明之金屬A與金屬b的熔 融，僅發生於此等相接之界面與其附近。其理由可能為金 屬A與金屬B連接時之加熱溫度，可降低其連接所產生之 接合層的熔融溫度。圖12(c)所示之接合層上的金屬B濃度 分佈之一例中，無論其數值於接合前之金屬則則（接合層與 基板佈線之界面侧）為固定，或接合前之金屬A侧（接合層 與Si晶片電極之界面側）上在金屬A與金屬B接觸界面附近 保持固定，當接近接合層與Si晶片電極側之界面側相當程 度’便會急速降低。如此般於金屬A側之金屬b溫度變 化，亦相異於由金屬A與B接觸界面依Fick定律估算金屬B 之元素對金屬A的擴散虛線。 再者，於接合層之結晶粒分佈狀況，亦可能有圖12(d) 與圖12(e)兩例。圖12(d)中，在金屬A與金屬B產生相互擴 散之區域中’形成金屬A之濃度高的結晶粒與金屬b之濃 度高的結晶粒產生之共晶組鳟，對應其附近區域之金屬A 與金屬B之濃度比率，每單位體積之前者的結晶粒數與後 108113.doc -19- 1300619 者結晶粒個數不同。令金屬A為Sn，令金屬B為In時，前者 為γ固溶體、後者為β固溶體。但與接合層之Si晶片的電極 之界面側，殘留金屬B未充分擴散之區域，與金屬A之本 身之組織。 在圖12(e)中，金屬A的厚度tA與金屬B的厚度tB組成之固 溶體（金屬A的濃度高之固溶體）形成初晶時，上述共晶組 織亦將進入其間隙内。再者，金屬A與金屬B間存在所謂 安定的金屬間化合物時，金屬A與金屬B充分相互擴散區 域中僅存在由金屬A與金屬B所形成之金屬間化合物，金 屬A與金屬B之組成比率亦可能相同。另一方面，此擴散 不充分之區域中，相應於共晶組織以及金屬間化合物以外 之部分的固溶體體積或數量，金屬A與B之組成比會隨之 變化。 參考圖12(c)〜圖12(e)所說明之各個事例，不僅可為令金 屬A為Sn，令金屬B為In所形成之接合層，亦可為令金屬a 為Sn、令金屬B為Bi(鉍）所形成之接合層，或令金屬a為 Ag、令金屬B為Sn所形成之接合層，或令金屬a為Cu、令 金屬B為Sn所形成之接合層。 再者，亦可如圖12(a)所示，相連接之兩個構件之其中一 方（於此為Si晶片）上，層積金屬A之膜及與金屬a相異的金 屬C之膜，該一方之構件與另一構件（於此為基板）接合 前，於金屬A與C間擴散各自的元素。如將金屬c膜形成為 薄於金屬A膜’该金屬C之膜的最表面係為由金屬a與金屬 C之固洛體所形成之金屬組織·而形成。即使於此固溶體與 108113.doc -20 - 1300619 該另-部材所形成之金屬B之間令各含有元素擴散，亦可 能產生參照圖丨2⑷〜圖12⑷所說明之各事例。此時，金屬 A與金屬C之固溶體組成，只要與金μ之組成相異即可， 因此金屬C可為與金屬_同之材料，亦可為盘金屬β不同 之材料。圖12⑷中，以錄敷法令金屬Α膜形成得較金心 或金屬C厚，但亦可用濺鍍法令金❹膜形成為較厚，以 濺鍍法令金屬Α之臈及金屬C之媒形成為較金屬Β膜薄。 從參照圖12⑷〜圖12⑷所說明之各事例可發現，在接合 :厚度所產生之此種變化’可將該接合層整體的熔融溫： &升至期望值，甚至，由互相接合之兩種部材之熱膨脹率 差，可為吸收-方對另-方施加的應力或變形之可能原因 之一 〇 [發明之效果] 本發明可適用於汽車電子機器、鐵道用變頻器、工業用 發電機等。 一 【圖式簡單說明】 圖 圖1為先前技術中打線接合型馬達控制用Ecu之剖面 圖2為先前技術中引線連接型馬達控制卿之剖面圖。 圖3為先前技術中顯示一般引線材料之構造例。 圖4為本發明之電子裝置所裝載之晶片及其電極構造之 剖面圖。 圖5為本發明之電子裝置所使用之基板的一部分及其電 極構造之剖面圖。 108113.doc -21 - 1300619 圖6為本發明之電子裝置所使用之基底金屬之 其電極構造之剖面圖。 77 圖7為本發明之雷+驻 造之剖面圖。 、 /刀隔零件及其電極構 圖8⑷跟(b)為本發明之電子裝置之製造方法中，將曰， 及分隔零件連接至基板的過程概要圖。 曰曰 圖9⑷〜⑷為本發明之電子裝置之一例的馬達控制用 ECU製造過程概要圖。
圖10為本發明之馬達控制Ecu之剖面圖。 圖11為本發明之實施例2中所說明之馬達控制ECU剖面 圖0
圖12(a)〜(e)為本發明實施例3中說明本發明之電子裝置 (連接部）之特徵所參考的說明圖，圖12(勾為Si晶片（第工構 件）與基板（第2構件）連接前之剖面形狀，圖12(1})為以晶片 電極（連接部）上所形成之金屬A與基板配線層（連接部）上所 形成之金屬B的擴散反應所形成之接合層（連接層）剖面， 圖12(c)為接合層上金屬6濃度的分布曲線（實線）與其假想 曲線（虛線）’圖12((1)為接合層上結晶粒分布之一例，圖 12(e)為該接合層上結晶粒分部之其他例。 【主要元件符號說明】 1 FET晶片 3 焊錫 5 〜 電極 7 陶瓷板 108113.doc -22- 91300619 11 13 15 19 21 23 25
29 31 33 35 37 39
44 45 46
Cu固體圖案 樹脂黏著劑 焊接線 電極 散熱裝置 金屬製框 連接部 連接部 汲極電極 Ni(鎳）鍍敷 Au層 鍛敷層 In層 Cu層 分隔零件 金屬層 連接部 連接部 連接部 絕緣樹脂 108113.doc -23-

Claims (1)

  1. D0(^59)2077號專利申請案 中文申請專利範圍替換本(97年3月） 十、申請專利範圍： 1· 一種電子裝置，其具備： 電子零件，其係具有第1電極與於該電極表面所形成 之至少一層第1金屬膜者；及 y 基板，其係具備：第2電極，其係與上述電子零件之 上述第1電極電性連接者；及至少一層第2金屬臈，其係 形成於該第2電極表面者； 上述電子零件與上述基板藉由使上述第丨金屬膜之最 表面與上述第2電極之最表面接觸，以該第丨金屬膜及該 第2金屬膜各自之熔融溫度以下且使該第丨金屬膜及該第 2金屬膜的該最表面接觸之界面附近以該第丨金屬膜及該 第2金屬膜之共晶溫度以上熔融，以該第1金屬膜及該第 2金屬膜之擴散反應使該界面附近形成包含該第1金屬膜 及4第2金屬膜各自之構成元素的合金部分而連接； 上述笔子零件與上述基板連接後之上述合金部分的開 始熔融溫度較該電子零件與該基板連接時的上述界面附 近之上述第1金屬膜與上述第2金屬膜之開始熔融溫度 ， 上述第1金屬膜及上述第2金屬膜的至少一方包含形成 為10微米以上厚度之至少一個金屬層，或者藉由該第1 金屬膜及該第2金屬膜在上述電子零件與上述基板之間 所形成的連接部厚度為2〇微米以上。 如睛求項1之電子裝置，其中上述第1金屬膜與上述第2 金屬膜接觸之上述界面附近存在安定之金屬間化合物。 108113-970303.doc 1300619 3·如請求項1或2之電子裝置，其中 上述私子零件係於與形成有上述第1電極之主面相反 側之其他主面形成有第3電極之Si功率元件； 口又有上述第2電極之上述基板的主面上形成以金屬引 ‘ 線與上述第3電極電性連接之第4電極； • 上述引線上形成有上述第1金屬膜，上述第3電極上形 成有上述第2金屬膜； _ 上述引線與上述第3電極藉由使各自形成之上述第丄金 屬膜之最表面與上述第2電極之最表面接觸，以上述熔 W Λ度以下且使5亥第丨金屬膜與該第2金屬膜之該最表面 接觸之界面附近以該第！金屬膜及該第2金屬膜之共晶溫 度以上熔融，以該第丨金屬膜及該第2金屬膜之擴散反應 使該界面附近形成包含該第！金屬膜及該第2金屬膜各自 之構成元素之合金部分而連接； 上述引線與上述第3電極連接後之上述合金部分的開 馨始炼融溫度高於該引線與該第3電極連接時之上述界面 附近的上述第i金屬膜及上述第2金屬膜的開始溶融溫 ' 度0 4· 一種電子裝置 之Si功率元件 板； 其具備··基板；搭载於基板之一方主面 及與該基板之另一方主面連接之金屬 於與上述Si功率元件之上述基板之一方主面相反側之 面所形成的第1電極與於該基板的一方主面所形成之第2 電極以導電金屬材料電性連接，且 108113-970303.doc 1300619 上述導電金屬材料與上述第2電極之間插入 離物’該導電金屬材料未施以將其朝上 Μ製隔 向彎曲之加工。 土之厚度方 5.如請求項4之電子裝置，其中 上述Si功率元件及上述隔離物與上述基板之 述Si功率元件及上述隔離物與上述導電金屬材料之： 接、及上述基板與上述金屬板之 進行： 夕個係如下 於連接之兩個構件之一方形成第i金屬膜，於另一方 形成上述第2金屬膜； 使上述第1金屬膜之最表面與上述第2電極之最表面接 觸，以該第1金屬膜及該第2金屬膜各自之熔融溫度以下 且使該第1金屬膜及該第2金屬膜之該最表面接觸之界面 附近以該第1金屬膜及該第2金屬膜之共晶溫度以上熔 融，以該第1金屬膜及該第2金屬膜之擴散反應於該界面 附近形成包含該第1金屬膜及該第2金屬膜各自之構成元 素的合金部分； 使上述連接後的上述合金部分之開始熔融溫度較該連 接時在上述界面附近之上述第1金屬膜與上述第2金屬膜 之開始熔解溫度高。 108113-970303.doc
TW095102077A 2005-02-28 2006-01-19 Electronic device TWI300619B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005052249A JP4325571B2 (ja) 2005-02-28 2005-02-28 電子装置の製造方法

Publications (2)

Publication Number Publication Date
TW200723494A TW200723494A (en) 2007-06-16
TWI300619B true TWI300619B (en) 2008-09-01

Family

ID=36931314

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095102077A TWI300619B (en) 2005-02-28 2006-01-19 Electronic device

Country Status (5)

Country Link
US (1) US7535092B2 (zh)
JP (1) JP4325571B2 (zh)
KR (1) KR100731243B1 (zh)
CN (1) CN100421244C (zh)
TW (1) TWI300619B (zh)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4858290B2 (ja) * 2006-06-05 2012-01-18 株式会社デンソー 負荷駆動装置
US20090020876A1 (en) * 2007-07-20 2009-01-22 Hertel Thomas A High temperature packaging for semiconductor devices
DE102007035902A1 (de) * 2007-07-31 2009-02-05 Siemens Ag Verfahren zum Herstellen eines elektronischen Bausteins und elektronischer Baustein
US8664038B2 (en) * 2008-12-04 2014-03-04 Stats Chippac Ltd. Integrated circuit packaging system with stacked paddle and method of manufacture thereof
JP5751258B2 (ja) * 2011-01-07 2015-07-22 富士電機株式会社 半導体装置の製造方法
JP5772050B2 (ja) 2011-02-22 2015-09-02 富士通株式会社 半導体装置及びその製造方法、電源装置
JP5681025B2 (ja) * 2011-04-08 2015-03-04 ニチコン株式会社 パワーモジュール
JP6067982B2 (ja) 2012-03-19 2017-01-25 スタンレー電気株式会社 半導体素子の製造方法
JP6005957B2 (ja) 2012-03-19 2016-10-12 スタンレー電気株式会社 半導体素子及びその製造方法
DE112013007187B4 (de) * 2013-09-13 2023-08-10 Ev Group E. Thallner Gmbh Verfahren zum Aufbringen einer Bondschicht
JP6192561B2 (ja) * 2014-02-17 2017-09-06 三菱電機株式会社 電力用半導体装置
CN107210238B (zh) * 2015-02-25 2020-03-17 三菱电机株式会社 功率模块
JP6418126B2 (ja) * 2015-10-09 2018-11-07 三菱電機株式会社 半導体装置
JP6330786B2 (ja) * 2015-11-16 2018-05-30 トヨタ自動車株式会社 半導体装置の製造方法
JP6849660B2 (ja) * 2016-04-01 2021-03-24 三菱電機株式会社 半導体装置
US11367669B2 (en) 2016-11-21 2022-06-21 Rohm Co., Ltd. Power module and fabrication method of the same, graphite plate, and power supply equipment
JP7025181B2 (ja) * 2016-11-21 2022-02-24 ローム株式会社 パワーモジュールおよびその製造方法、グラファイトプレート、および電源装置
US11830856B2 (en) 2019-03-06 2023-11-28 Semiconductor Components Industries, Llc Semiconductor package and related methods
KR102564459B1 (ko) * 2019-05-09 2023-08-07 현대자동차주식회사 양면 냉각 파워모듈의 스페이서 구조 및 그 제조 방법
EP3772087A1 (de) * 2019-07-30 2021-02-03 Siemens Aktiengesellschaft Montage einer elektronischen baugruppe
KR102312085B1 (ko) * 2019-11-08 2021-10-13 제엠제코(주) 방열 기판, 그 제조 방법, 그리고 이를 포함하는 반도체 패키지
US11610861B2 (en) * 2020-09-14 2023-03-21 Infineon Technologies Austria Ag Diffusion soldering with contaminant protection

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5308782A (en) 1992-03-02 1994-05-03 Motorola Semiconductor memory device and method of formation
JP3325072B2 (ja) 1992-03-02 2002-09-17 モトローラ・インコーポレイテッド 半導体メモリ装置
JPH0997818A (ja) * 1995-09-28 1997-04-08 Denso Corp フリップチップ構造及びその実装方法
JP2951882B2 (ja) * 1996-03-06 1999-09-20 松下電器産業株式会社 半導体装置の製造方法及びこれを用いて製造した半導体装置
US6441473B1 (en) * 1997-09-12 2002-08-27 Agere Systems Guardian Corp. Flip chip semiconductor device
JP3735526B2 (ja) * 2000-10-04 2006-01-18 日本電気株式会社 半導体装置及びその製造方法
WO2002029844A1 (en) 2000-10-04 2002-04-11 Extreme Devices Incorporated Multilayer carbon-based field emission electron device for high current density applications
JP2004006603A (ja) * 2002-03-26 2004-01-08 Fuji Electric Holdings Co Ltd 半導体パワーデバイス
JP4334966B2 (ja) 2002-11-13 2009-09-30 株式会社日立製作所 ディスクモジュール、及びディスクアレイ装置
JP2005076584A (ja) 2003-09-02 2005-03-24 Toyota Motor Corp 排熱発電装置
US7262444B2 (en) * 2005-08-17 2007-08-28 General Electric Company Power semiconductor packaging method and structure

Also Published As

Publication number Publication date
JP4325571B2 (ja) 2009-09-02
KR100731243B1 (ko) 2007-06-22
US20060192291A1 (en) 2006-08-31
US7535092B2 (en) 2009-05-19
JP2006237419A (ja) 2006-09-07
KR20060095502A (ko) 2006-08-31
CN100421244C (zh) 2008-09-24
CN1828881A (zh) 2006-09-06
TW200723494A (en) 2007-06-16

Similar Documents

Publication Publication Date Title
TWI300619B (en) Electronic device
JP6041469B2 (ja) 高融点半田層の形成方法
JP6667765B2 (ja) 電極接続方法及び電極接続構造
CN101290930B (zh) 包含半导体芯片叠层的半导体器件及其制造方法
JP5708961B2 (ja) 半導体装置の製造方法
JP2013016525A (ja) パワー半導体モジュールおよびその製造方法
JP3627591B2 (ja) パワー半導体モジュールの製造方法
CN111916418A (zh) 用于双面冷却功率模块的隔离件结构及其制造方法
JP6374240B2 (ja) 両面パワーモジュールのための液相拡散接合プロセス
JP4917375B2 (ja) パワー半導体モジュールの製造方法
JP2009158715A (ja) 放熱装置及びパワーモジュール
JP5733466B2 (ja) 半導体装置の製造方法
JP6156693B2 (ja) 半導体装置の製造方法
JP6847020B2 (ja) 半導体チップおよびパワーモジュールならびにその製造方法
JP6673635B2 (ja) 接合体の製造方法、ヒートシンク付パワーモジュール用基板の製造方法、ヒートシンクの製造方法、及び、接合体、ヒートシンク付パワーモジュール用基板、ヒートシンク
JP2014053406A (ja) 半導体装置およびその製造方法
TWI745572B (zh) 電子零件安裝模組
JP6260941B2 (ja) 半導体装置の製造方法
EP2782124A1 (en) Power semiconductor mounting
JPWO2016171122A1 (ja) 半導体装置及びその製造方法
JP2015160224A (ja) 接合用材料
CN104465578A (zh) 半导体装置及半导体模块
JP2009026965A (ja) 電子部品、およびその製造方法
JPH01302733A (ja) 電気回路装置
JP2006295074A (ja) 半導体装置用パッケージの製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees