CN111916418A - 用于双面冷却功率模块的隔离件结构及其制造方法 - Google Patents

用于双面冷却功率模块的隔离件结构及其制造方法 Download PDF

Info

Publication number
CN111916418A
CN111916418A CN201911175465.XA CN201911175465A CN111916418A CN 111916418 A CN111916418 A CN 111916418A CN 201911175465 A CN201911175465 A CN 201911175465A CN 111916418 A CN111916418 A CN 111916418A
Authority
CN
China
Prior art keywords
semiconductor chip
layer
spacer
plating layer
power module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911175465.XA
Other languages
English (en)
Inventor
朴圣源
金现旭
金泰华
朴准熙
李贤求
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Hyundai Motor Co
Kia Corp
Original Assignee
Hyundai Motor Co
Kia Motors Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Motor Co, Kia Motors Corp filed Critical Hyundai Motor Co
Publication of CN111916418A publication Critical patent/CN111916418A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32501—Material at the bonding interface
    • H01L2224/32503—Material at the bonding interface comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/83379—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/83464—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

一种隔离件结构及其制造方法，该隔离件结构连接绝缘基板和双面冷却功率模块的半导体芯片，包括：由复合材料构成的导电材料层；底镀层，设置在导电材料层上；以及铜镀层，设置在底镀层上，其中，铜镀层与将隔离件接合到半导体芯片和绝缘基板的接合材料接触。

Description

用于双面冷却功率模块的隔离件结构及其制造方法
相关申请的交叉引用
本申请要求于2019年5月9日在韩国知识产权局提交的韩国专利申请第10-2019-0054500号的优先权，其全部公开内容通过引用合并于此。
技术领域
本发明涉及一种用于双面冷却功率模块的隔离件结构及其制造方法，更具体地，涉及一种用于将双面冷却功率模块的半导体芯片与绝缘基板电连接和物理连接的隔离件结构及其制造方法。
背景技术
适当地将从高压电池供应的电流传输到驱动马达的功率模块主要用于操作用于诸如混合动力汽车或电动汽车的环保车辆的驱动马达。
功率模块由于其非常快速的开关操作而产生大量的热量。由于产生的热量降低了功率模块的效率，因此安装了冷却器以冷却功率模块。
配置双面冷却功率模块，使得将基板分别安装在功率模块的绝缘栅双极晶体管(IGBT)或MOSFET的半导体芯片的两侧，并将冷却器安装在基板外部，使得功率模块在两侧同时被冷却。
现有技术中的双面冷却功率模块具有其中半导体芯片和绝缘基板接合的结构。在双面冷却功率模块的结构中，使用被称为隔离件的部件来电连接和物理连接半导体芯片和绝缘基板。为了保持半导体芯片和绝缘基板之间的接合力，通常通过使用接合材料(焊料)将隔离件接合到半导体芯片和绝缘基板。另外，隔离件主要由诸如CuMo或AlSiC的复合材料制成。然而，复合材料难以确保与接合材料的润湿性，并且不引起与接合材料的界面反应。因此，难以将接合材料和由复合材料制成的隔离件电和物理地接合。
因此，需要将金属涂覆到隔离件的表面上，以通过使用接合材料将由复合材料制成的隔离件接合至半导体芯片和绝缘基板。通常，镍(Ni)用作要涂覆到由复合材料制成的隔离件的表面上的金属。
在双面冷却功率模块的情况下，半导体芯片在反复打开和关闭的同时进行操作，结果，如上所述，半导体芯片在运行期间产生大量的热量。通过在高温环境(例如在大约120℃至175℃的温度下)下无人看管所制造的双面冷却功率模块并检查接合部分是否异常，来评估在这种产生热量的状态下的耐用性。
在复合材料制成的隔离件的表面镀有镍(Ni)且在高温环境下无人看管双面冷却功率模块的状态下进行测试的情况下，由于半导体芯片产生的热量，涂覆在半导体芯片表面上的薄金属层与接合材料发生反应，结果形成并生长了金属间化合物。由于金属间化合物的生长，半导体芯片表面上的薄金属层被完全耗尽，结果，存在半导体芯片的电特性劣化或半导体芯片被烧毁的问题。
因此，需要一种在相关技术中通过使用由复合材料制成的隔离件来通过抑制半导体芯片表面上的薄金属层的耗尽而能够改善半导体芯片的电特性和耐久性的技术。
发明内容
做出本公开的目的在于提供一种隔离件结构及其制造方法，对于将半导体芯片和绝缘基板电连接和物理连接，通过使用现有技术中由复合材料构成的隔离件来抑制半导体芯片表面上的薄金属层的耗尽，从而能够改善双面冷却功率模块的半导体芯片的电气特性和耐用性。
本公开要解决的技术问题不限于上述技术问题，并且通过以下描述，本公开所属领域的技术人员可以清楚地理解上面未提及的其他技术问题。
本公开的示例性实施方式提供了一种隔离件结构，该隔离件结构连接绝缘基板和双面冷却功率模块的半导体芯片，该隔离件结构包括：由复合材料构成的导电材料层；设置在导电材料层上的底涂层；以及设置在底镀层上的铜镀层，其中，铜镀层与将隔离件接合到半导体芯片和绝缘基板的接合材料接触。
本公开的另一示例性实施方式提供一种制造隔离件的方法，该隔离件连接绝缘基板和双面冷却功率模块的半导体芯片，该方法包括以下步骤：在由复合材料构成的导电材料层上涂覆底镀层；以及将铜镀层涂覆到底镀层上，其中，铜镀层与将隔离件接合到半导体芯片和绝缘基板的接合材料接触。
底镀层可以由选自包含镍(Ni)，钛(Ti)，铬(Cr)和钴(Co)的组中的一种金属构成。
铜镀层可以具有5μm以上的厚度。
隔离件结构可以进一步包括涂覆到铜镀层上的金属层，并且制造隔离件的方法可以进一步包括将金属层涂覆到铜镀层上。
金属层可以由选自包含金(Au)、银(Ag)和钯(Pd)的组中的一种金属构成。
下面将描述根据本公开的隔离件结构的效果及其制造方法。
首先，在现有技术中使用隔离件结构的双面冷却功率模块的情况下，当在高温环境下无人看管双面冷却功率模块时，由于半导体芯片表面上的金属层的损失，半导体芯片的电特性劣化。然而，通过应用根据本公开的隔离件结构，可以通过抑制半导体芯片表面上的金属层的损失来改善半导体芯片的电特性和耐久性。
第二，根据本公开的隔离件结构，可以通过使镍镀层最小化并将铜镀层添加到镍镀层上来提高与接合材料的润湿性。
通过本公开获得的效果不限于上述效果，并且根据以下描述，本领域技术人员将清楚地理解上述未提及的其他效果。
附图说明
提供以下附图以帮助理解本公开，并且将本公开的示例性实施方式与详细描述一起提供。然而，本公开的技术特征不限于特定附图，并且在各个附图中示出的特征可以组合以构成另一示例性实施方式。
图1是示出相关技术中的双面冷却功率模块的结构的截面图。
图2A是示出相关技术中的用于双面冷却功率模块的隔离件结构的视图。
图2B是示出在图2A所示的现有技术中，在半导体芯片与隔离件之间的接合部分处的接合材料与金属层之间的反应过程的示意图。
图3A是示出根据本公开的示例性实施方式的可以用于双面冷却功率模块的隔离件结构的视图。
图3B是示出根据图3A所示的本公开的示例性实施方式的在半导体芯片与隔离件之间的接合部分处的接合材料与金属层之间的反应过程的示意图。
图4是示出根据本公开的示例性实施方式的双面冷却功率模块的接合方法的示意图。
具体实施方式
在下文中，将参考附图详细描述本公开。然而，本公开不受示例性实施方式的限制。在各个附图中指示的相同参考标号指代执行基本相同功能的构件。
根据以下描述，可以自然地理解本公开的目的和效果，或者可以使本公开的目的和效果更加清楚，并且本公开的目的和效果不仅限于以下描述。另外，在本公开的描述中，当确定特定描述可能不必要地使本公开的主题模糊时，将省略与本公开相关的公知技术的特定描述。
图1是示出相关技术中的双面冷却功率模块的结构的截面图。如图1所示，在现有技术的双面冷却功率模块中，上、下绝缘基板130可以设置在半导体芯片160的两侧，并且可以安装隔离件150以将上、下绝缘基板130连接，并限定其中安装电线(未示出)的空间。通常，执行使用接合材料(焊料)140的接合过程以保持隔离件150、半导体芯片160和绝缘基板130之间的接合力。此外，在上、下绝缘基板130的每一个的外侧形成导热油脂(thermalgrease)，即热界面材料(TIM)120，以将热量传递到冷却器110。
图2A示出现有技术中的用于双面冷却功率模块的隔离件结构。参照图2A，现有技术中的隔离件结构具有其中镍镀层220被涂覆到由复合材料制成的导电材料层210上的结构。当将图2A所示的隔离件结构用于双面冷却功率模块时，可能会出现以下问题，并且将在下面参考图2B来描述该问题。
图2B是示出在图2A所示的现有技术中，在半导体芯片和隔离件之间的接合部分处的接合材料与金属层之间的反应过程的示意图。如图2B所示，在现有技术中，当功率模块工作时半导体芯片产生热量的情况下，在接合材料位于隔离件之间的状态下，其中将镍镀层220涂覆到复合材料层210上，并且，在保持高温状态(例如，在120℃～175℃左右的温度)的情况下，在其上涂覆薄金属层的半导体芯片，金属间化合物形成为锡(Sn)，这是接合材料的主要成分，并且半导体芯片表面上的金属层相互反应并发生金属间扩散。
在这点上，因为涂覆到半导体芯片的表面上的金属层被构造为薄膜，所以在如上所述保持高温状态的情况下，金属层可能容易地被耗尽。根据本公开的示例性实施方式，半导体芯片上的薄金属层可以包括几微米(μm)的镍层和由金(Au)等制成并且具有纳米级(Au)的贵金属层。当接合材料在高温状态下熔化时，贵金属层完全消失在接合材料中，此后，镍层用作与接合材料反应的主要反应层。
因此，由于半导体芯片产生的热量，半导体芯片表面的薄金属层与接合材料发生反应，从而形成金属间化合物，并且半导体芯片表面上的金属层被完全耗尽，这引起半导体芯片的电特性和耐久性下降的问题。
作为该问题的解决方案，如图3A所示，提出了根据本公开的示例性实施方式的隔离件结构，在其上进行底层镀覆，然后另外进行铜镀覆。进行底层镀覆以确保隔离件和铜镀层之间的紧密接触力，并且接合材料与铜镀层进行反应而不是底镀层。
下面将更具体地描述图3A所示的根据本公开的示例性实施方式的隔离件结构。
根据本公开的示例性实施方式的隔离件是被配置为连接绝缘基板和双面冷却功率模块的半导体芯片的部件。将参照图3A描述隔离件的截面结构。隔离件包括由复合材料制成的导电材料层310，涂覆到导电材料层310上的底镀层320，以及涂覆到底镀层320上的铜镀层330。布置在隔离件的横截面结构的最外围部分处的铜镀层330与接合材料接触，该接合材料被配置为将隔离件与半导体芯片和绝缘基板接合。
特别地，隔离件的导电材料层310可以由能够使电流流过的导电材料制成，即，具有优异的导热性的材料。另外，根据本公开的示例性实施方式，底镀层320可以由金属制成以确保导电材料层310和铜镀层330之间的紧密接触力。例如，底镀层320可以由镍(Ni)、钛(Ti)、铬(Cr)和钴(Co)的任一种制成。
特别地，铜镀层330可以具有5μm以上的厚度。另外，根据本公开的示例性实施方式，铜镀层330的外周可以镀有附加的金属层，以防止氧化并提高与接合材料的润湿性。例如，铜镀层330的外围可以另外镀有由金(Au)、银(Ag)和钯(Pd)中的任一种制成的金属层。
根据图3A所示的根据本公开示例性实施方式的隔离件结构，如以上参考图2A和图2B所描述的，可以解决在现有技术的隔离件结构上出现的半导体芯片的电特性的劣化和耐久性的问题。下面将参考图3B描述该配置。
图3B是示出根据本公开的示例性实施方式的在半导体芯片与隔离件结构之间的接合部分处的接合材料与金属层之间的反应过程的示意图。如图3B中所示，在根据本公开的示例性实施方式，当功率模块工作时半导体芯片产生热量的情况下，将接合材料置于隔离件之间，其中，将底镀层320和铜镀层330涂覆到导电材料层310上，并且，在保持高温状态(例如，在120℃～175℃左右的温度)的情况下，在其上涂覆薄金属层的半导体芯片，作为接合材料的主要成分的锡(Sn)不仅与半导体芯片表面上的金属层(例如，镍镀层)反应，而且还与隔离件的铜镀层330反应。因此，在接合材料与半导体芯片之间以及接合材料与隔离件之间发生金属间扩散时，形成金属间化合物。
但是，如以上参考图2B(其中使用了相关技术中的隔离件(图2A所示))所述，与在接合材料和半导体芯片表面上的金属层之间形成金属间化合物时，耗尽了半导体芯片上的金属层的情况不同，在图3B(其中使用根据本公开的示例性实施方式的隔离件(图3A所示))的情况下，接合材料与隔离件的铜镀层之间的反应速度明显高于接合材料与半导体芯片的薄金属层(例如，镍镀层)之间的反应速度，使得隔离件的铜镀层优先与接合材料反应，结果，抑制了接合材料与半导体芯片的薄金属层之间的反应。如上所述被抑制的反应速度也抑制了半导体芯片的金属薄层的耗尽。即，即使在接合材料和半导体芯片的薄金属层之间形成反应层，半导体芯片的薄金属层也没有被完全耗尽。因此，由于抑制了半导体芯片的薄金属层的耗尽，所以可以解决高温环境下半导体芯片的电特性劣化的问题。
图4是示出根据本公开的示例性实施方式的双面冷却功率模块的接合方法的示意图。接合方法将在下面具体描述。
参照图4，可以通过以下过程来执行根据本公开的示例性实施方式的双面冷却功率模块的接合。
首先，通过将下绝缘基板421耦接到夹具，在下绝缘基板421上布置第一接合材料422和半导体芯片423，然后执行焊接来形成第一半成品420。之后，通过将上绝缘基板411耦接到夹具上，在上绝缘基板411上布置第二接合材料412和隔离件413，另外在隔离件413上布置第三接合材料414，然后执行焊接来形成第二半成品410。在这种情况下，根据本公开的示例性实施方式，隔离件413可以是通过在复合材料上执行底层镀覆和铜镀覆而制成的辅助材料。最后，将第一半成品420和第二半成品410分别耦接至夹具，然后执行焊接。
参照图4，可以通过以下过程来执行根据本公开的另一示例性实施方式的双面冷却功率模块的接合。
首先，通过将下绝缘基板421耦接至夹具，将第一接合材料422和半导体芯片423设置在下绝缘基板421上，然后进行焊接来形成第一半成品420。此后，通过将上绝缘基板411耦接至夹具，并且将第二接合材料412和隔离件413设置在上绝缘基板411上来形成第二半成品410。在这种情况下，根据本公开的示例性实施例，隔离件413可以是通过在复合材料上进行底镀覆和铜镀覆而制成的辅助材料。最后，将第一半成品420和第二半成品410分别耦接至夹具，将第三接合材料414插入其间，然后进行焊接。
将根据上述任何一种方法连接功率模块而获得的多个样品与理想状态进行比较时，电特性的变化显示在下表1和表2中。
表1示出在结合了图4所示的现有技术中的隔离件的情况下各个样品的电特性的变化，以及表2示出在结合了图4所示的根据本发明示例性实施方式的隔离件的情况下各个样品的电特性的变化。
[表1]
示例1 示例2
Vce(sat)-H[V] 7.5％↑ 13％↓
Vce(sat)-L[V] 25％↑ 15％↓
Vf-H[V] 32％↑ 20％↑
Vf-L[V] 9％↑ 34％↑
[表2]
示例1 示例2 示例3 示例4 示例5
Vce(sat)-H[V] 2.15％↑ 2.46％↑ 2.08％↑ 1.85％↑ 2.15％↑
Vce(sat)-L[V] 1.00％↓ 0.69％↓ 0.92％↓ 1.00％↓ 0.15％↓
Vf-H[V] 2.35％↑ 2.35％↑ 1.35％↑ 1.65％↑ 2.71％↑
Vf-L[V] 1.82％↓ 2.18％↓ 2.65％↓ 2.41％↓ 1.59％↓
当比较表1和表2时，可以确定，在使用相关技术的隔离件的情况下，电特性在7.5％至34％之间变化，然而，在使用根据本公开的示例性实施方式的隔离件的情况下，电特性在0.15％和2.71％之间变化。可以确定的是，与使用相关技术中的隔离件结构的情况相比，在如上所述使用根据本公开的示例性实施方式的隔离件结构的情况下，抑制了电特性的变化。换句话说，在使用根据本公开的示例性实施方式的隔离件结构的情况下，可以解决现有技术中的半导体芯片的电特性劣化或半导体芯片烧坏的问题。
另外，表3示出了在根据参照图4描述的任何一种方法，在焊接功率模块之后，使用根据本公开的示例性实施例的隔离件结构的情况和使用现有技术的隔离件结构的情况之间进行比较的半导体芯片表面上的剩余金属层的厚度。
[表3]
Figure BDA0002289820180000111
如表3所示，当功率模块工作时(即，保持高温状态)，与在使用现有技术的隔离件结构的情况(约1.1μm)相比，在使用根据本公开的示例性实施方式的隔离件结构的情况(约1.5μm)中半导体芯片表面上剩余的金属层的厚度厚约0.4μm。可以确定的是，与使用现有技术的隔离件结构的情况相比，在使用根据本公开示例性实施例的隔离件结构的情况下，抑制了半导体芯片表面上的金属层的损失。换句话说，在使用根据本公开的示例性实施方式的隔离件结构的情况下，抑制了半导体芯片上的金属层的耗尽，结果，可以解决现有技术中半导体芯片的耐用性降低的问题。
尽管以上已经参照示例性实施方式详细描述了本公开，但是本公开所属领域的技术人员将理解，可以在不脱离本公开的范围的情况下对示例性实施方式进行各种修改。因此，本公开的范围不应限于所描述的示例性实施方式，而是不仅应由所附权利要求书限定，而且还应由从与权利要求书等效的概念得出的所有改变或修改形式限定。

Claims (10)

1.一种隔离件结构，连接绝缘基板和双面冷却功率模块的半导体芯片，所述隔离件结构包括：
导电材料层，由复合材料构成；
底镀层，设置所述导电材料层上；以及
铜镀层，设置在所述底镀层上，
其中，所述铜镀层与将所述隔离件接合到所述半导体芯片和所述绝缘基板的接合材料接触。
2.根据权利要求1所述的隔离件结构，其中，所述底镀层由选自包含镍(Ni)、钛(Ti)、铬(Cr)以及钴(Co)的组中的一种金属构成。
3.根据权利要求1所述的隔离件结构，其中，所述铜镀层具有5μm以上的厚度。
4.根据权利要求1所述的隔离件结构，还包括设置在所述铜镀层上的金属层。
5.根据权利要求4所述的隔离件结构，其中，所述金属层由选自包含金(Au)、银(Ag)以及钯(Pd)的组中的一种金属构成。
6.一种制造隔离件的方法，该隔离件连接绝缘基板和双面冷却功率模块的半导体芯片，所述方法包括以下步骤：
在由复合材料构成的导电材料层上涂覆底镀层；以及
将铜镀层涂覆到所述底镀层上，
其中，所述铜镀层与将所述隔离件接合到所述半导体芯片和所述绝缘基板的接合材料接触。
7.根据权利要求6所述的方法，其中，所述底镀层由选自包含镍(Ni)、钛(Ti)、铬(Cr)以及钴(Co)的组中的一种金属构成。
8.根据权利要求6所述的方法，其中，所述铜镀层具有5μm以上的厚度。
9.根据权利要求6所述的方法，还包括将金属层涂覆到所述铜镀层上。
10.根据权利要求9所述的方法，其中，所述金属层由选自包含金(Au)、银(Ag)以及钯(Pd)的组中的一种金属构成。
CN201911175465.XA 2019-05-09 2019-11-26 用于双面冷却功率模块的隔离件结构及其制造方法 Pending CN111916418A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020190054500A KR102564459B1 (ko) 2019-05-09 2019-05-09 양면 냉각 파워모듈의 스페이서 구조 및 그 제조 방법
KR10-2019-0054500 2019-05-09

Publications (1)

Publication Number Publication Date
CN111916418A true CN111916418A (zh) 2020-11-10

Family

ID=72943461

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911175465.XA Pending CN111916418A (zh) 2019-05-09 2019-11-26 用于双面冷却功率模块的隔离件结构及其制造方法

Country Status (4)

Country Link
US (1) US11031314B2 (zh)
KR (1) KR102564459B1 (zh)
CN (1) CN111916418A (zh)
DE (1) DE102019217858A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102260662B1 (ko) * 2019-12-12 2021-06-04 한국전자기술연구원 체결형 스페이서를 이용한 양면냉각모듈패키지 및 그의 제조방법
KR20210138385A (ko) 2020-05-12 2021-11-19 현대자동차주식회사 다층 스페이서 및 이를 적용한 양면냉각 파워모듈
KR20230094645A (ko) 2021-12-21 2023-06-28 현대자동차주식회사 파워 모듈 및 그 제조 방법

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0026926D0 (en) * 1999-11-04 2000-12-20 Nec Corp Flip-chip type semiconductor device with stress-absorbing layer made of thermosetting resin, and its manufacturing method
CA2445890A1 (en) * 2002-10-22 2004-04-22 Sumitomo Electric Industries, Ltd. Package for housing semiconductor chip, and semiconductor device
CN101687284A (zh) * 2007-11-20 2010-03-31 丰田自动车株式会社 焊接材料及其制造方法、接合体及其制造方法、以及功率半导体模块及其制造方法
US20120152510A1 (en) * 2010-12-16 2012-06-21 Nippon Soken, Inc. Bonding structure and bonding method of heat diffusion member, and cooling unit using the same
CN105575830A (zh) * 2014-10-30 2016-05-11 丰田自动车株式会社 半导体装置和制造半导体装置的方法
CN108074888A (zh) * 2016-11-09 2018-05-25 现代自动车株式会社 具有双面冷却的电源模块
CN108231709A (zh) * 2016-12-15 2018-06-29 现代自动车株式会社 具有双面冷却的功率模块

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4325571B2 (ja) * 2005-02-28 2009-09-02 株式会社日立製作所 電子装置の製造方法
JP6112077B2 (ja) * 2014-07-03 2017-04-12 トヨタ自動車株式会社 半導体装置
KR101755769B1 (ko) * 2014-10-29 2017-07-07 현대자동차주식회사 양면 냉각 파워 모듈 및 이의 제조 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0026926D0 (en) * 1999-11-04 2000-12-20 Nec Corp Flip-chip type semiconductor device with stress-absorbing layer made of thermosetting resin, and its manufacturing method
CA2445890A1 (en) * 2002-10-22 2004-04-22 Sumitomo Electric Industries, Ltd. Package for housing semiconductor chip, and semiconductor device
CN101687284A (zh) * 2007-11-20 2010-03-31 丰田自动车株式会社 焊接材料及其制造方法、接合体及其制造方法、以及功率半导体模块及其制造方法
US20120152510A1 (en) * 2010-12-16 2012-06-21 Nippon Soken, Inc. Bonding structure and bonding method of heat diffusion member, and cooling unit using the same
CN105575830A (zh) * 2014-10-30 2016-05-11 丰田自动车株式会社 半导体装置和制造半导体装置的方法
CN108074888A (zh) * 2016-11-09 2018-05-25 现代自动车株式会社 具有双面冷却的电源模块
CN108231709A (zh) * 2016-12-15 2018-06-29 现代自动车株式会社 具有双面冷却的功率模块

Also Published As

Publication number Publication date
KR102564459B1 (ko) 2023-08-07
DE102019217858A1 (de) 2020-11-12
US11031314B2 (en) 2021-06-08
KR20200129699A (ko) 2020-11-18
US20200357720A1 (en) 2020-11-12

Similar Documents

Publication Publication Date Title
US7535092B2 (en) Si power device mounted on a substrate including arrangements to prevent damage to connection layers due to heat treatment
US8592986B2 (en) High melting point soldering layer alloyed by transient liquid phase and fabrication method for the same, and semiconductor device
CN111916418A (zh) 用于双面冷却功率模块的隔离件结构及其制造方法
US8975117B2 (en) Semiconductor device using diffusion soldering
WO2015053356A1 (ja) 電極接続方法及び電極接続構造
JP3627591B2 (ja) パワー半導体モジュールの製造方法
US20170162482A1 (en) Semiconductor device
JPH0936186A (ja) パワー半導体モジュール及びその実装方法
US20170062317A1 (en) Power semiconductor module and method for manufacturing the same
JP4344560B2 (ja) 半導体チップおよびこれを用いた半導体装置
JP2019079905A (ja) 半導体装置および半導体装置の製造方法
US9299633B2 (en) Semiconductor device, heat radiation member, and manufacturing method for semiconductor device
JP5011088B2 (ja) 放熱装置及びパワーモジュール
JP2011061105A (ja) 接続構造、パワーモジュール及びその製造方法
JP5203896B2 (ja) 半導体装置およびその製造方法
JP2013506310A (ja) 回路装置およびその製造方法
JP3307145B2 (ja) パワーチップキャリア及びこれを用いたパワー半導体装置
US20230369166A1 (en) Power semiconductor module arrangement and method for producing the same
US11756923B2 (en) High density and durable semiconductor device interconnect
JP2013009014A (ja) 半導体装置
WO2016171122A1 (ja) 半導体装置及びその製造方法
US20230056682A1 (en) Semiconductor device
CN117174661A (zh) 功率模块及半导体器件
JP2023030574A (ja) 半導体装置および半導体装置の製造方法
JP5151837B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: Seoul, South Kerean

Applicant after: Hyundai Motor Co.,Ltd.

Applicant after: Kia Co.,Ltd.

Address before: Seoul, South Kerean

Applicant before: Hyundai Motor Co.,Ltd.

Applicant before: Kia Motors Corp.

CB02 Change of applicant information
TA01 Transfer of patent application right

Effective date of registration: 20230420

Address after: Seoul, South Kerean

Applicant after: Hyundai Motor Co.,Ltd.

Applicant after: Kia Co.,Ltd.

Applicant after: Infineon Technologies AG

Address before: Seoul, South Kerean

Applicant before: Hyundai Motor Co.,Ltd.

Applicant before: Kia Co.,Ltd.

TA01 Transfer of patent application right