CN104465578A - 半导体装置及半导体模块 - Google Patents
半导体装置及半导体模块 Download PDFInfo
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- CN104465578A CN104465578A CN201410053381.XA CN201410053381A CN104465578A CN 104465578 A CN104465578 A CN 104465578A CN 201410053381 A CN201410053381 A CN 201410053381A CN 104465578 A CN104465578 A CN 104465578A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 132
- 229910052751 metal Inorganic materials 0.000 claims abstract description 57
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- 239000000758 substrate Substances 0.000 claims description 26
- 239000011135 tin Substances 0.000 claims description 17
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- 230000009471 action Effects 0.000 claims description 10
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- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 229910052709 silver Inorganic materials 0.000 claims description 9
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- 239000004332 silver Substances 0.000 claims description 8
- 229910052718 tin Inorganic materials 0.000 claims description 8
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- 229910052804 chromium Inorganic materials 0.000 claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims 2
- 239000010410 layer Substances 0.000 description 36
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- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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Abstract
一种半导体装置,上述半导体装置包括半导体元件和金属膜。上述半导体元件具有第1面以及与第1面相反的一侧的第2面。上述金属膜设置在上述半导体元件的上述第2面。上述金属膜含Cr。上述半导体元件也可以含有动作确保温度比Si的动作确保温度高的材料。
Description
相关申请
本申请主张以日本专利申请2013-191176号(申请日:2013年9月13日)为基础申请的优先权。本申请通过参照该基础申请而包括基础申请的全部内容。
技术领域
实施方式在一般情况下涉及半导体装置及半导体模块。
背景技术
在基板上安装半导体元件时,用焊料等接合件连接两者。在对封装内收纳有这种半导体元件的半导体模块长时间施加冷热循环、动力循环等负荷的情况下,有在接合部产生裂纹的可能性。若裂纹发展,则发生接合部的断裂,成为由温度阻抗的上升引起的接合部的熔融等故障的原因。在半导体装置及半导体模块中,提高可靠性是重要的。
发明内容
本发明的实施方式提供一种能够提高可靠性的半导体装置及半导体模块。
实施方式所涉及的半导体装置包括半导体元件和金属膜。
上述半导体元件具有第1面以及与第1面相反的一侧的第2面。
上述金属膜设置在上述半导体元件的上述第2面。上述金属膜含Cr。
附图说明
图1(a)及图1(b)是例示第1实施方式所涉及的半导体装置的结构的示意性剖视图。
图2是例示半导体装置110的安装状态的示意性剖视图。
图3是例示基于恒温试验的金属膜的厚度的变化的图。
图4是例示第2实施方式所涉及的半导体模块的结构的示意性剖视图。
图5是例示半导体模块内的安装状态的示意性俯视图。
图6(a)及图6(b)是例示中间层的图。
图7(a)及图7(b)是表示参考例的图。
图8(a)及图8(b)是例示中间层的结构的示意性剖视图。
具体实施方式
以下,根据附图说明本发明的实施方式。在以下说明中,对同一部件标以同一符号,对已说明过一次的部件适当省略其说明。
(第1实施方式)
图1(a)及图1(b)是例示第1实施方式所涉及的半导体装置的结构的示意性剖视图。
在图1(a)中,表示半导体装置110整体的剖视图。在图1(b)中,表示半导体装置110的金属膜20的放大剖视图。
如图1(a)所示,本实施方式所涉及的半导体装置110具备半导体元件10和金属膜20。
半导体元件10包括通过向半导体材料进行规定的杂质注入工艺、光刻工艺等而形成的元件区域。元件区域是晶体管、二极管等有源元件,或电阻、电容器等无源元件。半导体元件10是将包含半导体材料的晶片等切成矩形而成的芯片形状。半导体元件10具有第1面10a以及与第1面10a相反的一侧的第2面10b。第1面10a例如是半导体元件10的表面,第2面10b例如是半导体元件10的背面。
金属膜20设置在半导体元件10的第2面10b上。金属膜20与第2面10b相接。金属膜20至少包含第1膜21-1。如图1(b)所示,第1膜21-1设置在金属膜20的最表面20a侧。在半导体装置110中,最表面20a包含铬(Cr)。在本实施方式中,作为第1膜21-1,使用实质上的纯Cr或含Cr的金属(合金)。实质上的纯Cr包括无意间混入有杂质的Cr。
金属膜20也可以是只有第1膜21-1的单层膜。此外,金属膜20也可以是多层膜。
如图1(b)所示,作为金属膜20而使用n(n为2以上的整数)层的多层膜的情况下,金属膜20具有第1膜21-1~第n膜21-n。在n层的多层膜中,将最远离半导体元件10的第2面10b的膜设为第1膜21-1。从第1膜21-1朝向第2面10b,依次设为第2膜21-2、第3膜21-3、…。与第2面10b相接的膜为第n膜21-n。
在金属膜20为n层的多层膜的情况下,第2膜21-2~第n膜21-n中的至少1个含有从由钛(Ti)、铝(Al)、金(Au)、锡(Sn)、镍(Ni)、银(Ag)构成的组中选择的至少1种。
表示金属膜20的具体例。
n=2,即表示2层的多层膜的例子。
第2膜21-2为Au,第1膜21-1为Cr。
n=3,即表示3层的多层膜的例子。
第3膜21-3为Ti,第2膜21-2为Au,第1膜21-1为Cr。
n=4,即表示4层的多层膜的例子。
第4膜21-4为Al,第3膜21-3为Ti,第2膜21-2为Au,第1膜21-1为Cr。
n=4,即表示4层的多层膜的其他例子。
第4膜21-4为Al,第3膜21-3为Ti,第2膜21-2为Sn,第1膜21-1为Cr。
含有Cr的第1膜21-1的厚度例如为500纳米(nm)以上且750nm以下的程度。
金属膜20例如通过真空蒸镀、溅射、离子镀、电镀形成。在使用Cr作为第1膜21-1的情况下,为了抑制表面的氧化,优选的是,通过减压环境下的干式制法来形成。
图2是例示半导体装置110的安装状态的示意性剖视图。
如图2所示,半导体装置110安装在基板50之上。基板50具有支撑部51和导体图案52。支撑部51例如使用陶瓷。导体图案52例如使用铜(Cu)。
半导体装置110经由接合件60与基板50的导体图案52接合。接合件60例如使用含锡(Sn)的焊料。或者,接合件60也可以是含有银(Ag)纳米粒子、银(Ag)烧结材料、锡铜(SnCu)或银锡(Ag3Sn)等的金属间化合物。
例如,若在半导体装置110运转时对半导体元件10通电,则半导体元件10的温度上升。另一方面,若半导体装置110的运转停止,则半导体元件10的温度下降。若反复进行半导体装置110的运转及停止,则在接合件60即焊料上产生应变。并且,因焊料的再结晶化而产生裂纹,进而发展。
此外,作为另一要因,在半导体装置110的周围设置有树脂模(mold)的情况下,存在该模部分从散热用底板基板剥离的可能性。由此,整体的约束消失,因此存在在焊料等的接合中产生裂纹并发展的可能性。
半导体装置110的热不仅向接合部传递,而且还向其下方的构成材料即基板50的导体图案52及支撑部51传递。当Cu在高温下使用、或因热阻的上升而产生发热的情况下,存在软化的情况。该软化在Cu的温度上升到再结晶温度以上的情况下发生。
在半导体装置110中,半导体元件10使用比可确保Si元件的动作的最高温度(动作确保温度)高的动作确保温度的材料。例如,半导体元件10的材料例如包含SiC及GaN中的某1种。SiC、GaN等在功率模块中所使用的材料能够期待在非常高的温度下使用。例如,作为使用温度区域,Si以175℃为界限,但是SiC及GaN能够实现在超过200℃、250℃的温度区域使用。
在这样的高温下使用的半导体装置110中,通过使用在最表面20a具有含Cr的第1膜21-1的金属膜20,能够有效地抑制金属膜20消失。
经由接合件60接合了半导体装置110和基板50的情况下的接合部的可靠性通过冷热循环、动力循环、恒温试验等来检验。在对接合部施加了负荷的情况下,若在接合件60上产生裂纹,且负荷进一步持续,则存在该裂纹发展的情况。
图3是例示基于恒温试验的金属膜的厚度的变化的图。
图3的横轴为时间,纵轴为金属膜的厚度。图3所示的线L1表示本实施方式所涉及的半导体装置110中适用的金属膜20的厚度,线L2表示使用了在最表面含Ni的金属膜的情况下的金属膜的厚度。在该恒温试验中,测定在200℃的恒温槽中将样品放置2000小时的情况下的金属膜的厚度的变化。
如图3的线L1所示可知,在本实施方式所涉及的半导体装置110中适用的金属膜20中,与线L2相比,金属膜20的厚度的减小得到抑制。即,如线L2所示,在使用含Ni的金属膜的情况下,金属膜的厚度逐渐减小。另一方面,如线L1所示,在使用含Cr的金属膜20的情况下,金属膜20的厚度几乎不减小。
这是因为,在使用含Ni的金属膜的情况下,接合件60中所含的Sn与Ni构成化合物并扩散而消失。若金属膜的Ni消失,则因金属膜的变形而容易产生裂纹,导致接合部分处的可靠性下降。与此相对地,在使用含Cr的金属膜20的情况下,由于接合件60中所含的Sn难以与Cr构成化合物,因此因消失引起的金属膜20的厚度减小得到抑制。若金属膜20的厚度减少得到抑制,则半导体装置110的接合部处的可靠性提高。
这样,在本实施方式所涉及的半导体装置110中,即使施加例如200℃以上的温度,也能够维持金属膜20的厚度。因此,在将半导体装置110安装在基板50上使用的情况下的高温下的长期使用中,能够提高可靠性。
另外,在本实施方式中,作为金属膜20的最表面20a中所含的材料而示出了Cr,但只要是在与接合件60的材料之间不构成化合物、或难以构成化合物的材料,也可以是Cr以外的材料。此外,作为金属膜20的最表面20a中所含的材料,也可以是即使施加比Si的动作确保温度高的温度的情况下也不消失或难以消失的材料。
(第2实施方式)
接着,说明第2实施方式所涉及的半导体模块。
图4是例示第2实施方式所涉及的半导体模块的结构的示意性剖视图。
图5是例示半导体模块内的安装状态的示意性俯视图。
如图4所示,半导体模块210具备半导体装置110、基板50及接合件60。在图4所示的例子中,半导体模块210还具备底板70、散热片80及外壳90。
如在第1实施方式中所说明的那样,半导体装置110具有半导体元件10和金属膜20。半导体装置110安装在基板50之上。接合件60设置在半导体装置110的金属膜20与基板50的导体图案52之间。
在图4中,在半导体模块210内表示有1个半导体装置110,但也可以包含多个半导体装置110。例如,在图5所示的例子中,在半导体模块210内,作为半导体装置110,设置有多个半导体装置CP11、CP12、CP21、CP22、CP31、CP32、CP41及CP42。
此外,在图5所示的例子中,每2个半导体装置110安装在1个基板50上。即,在图5所示的例子中,设置有4个基板50,在各基板50上安装有2个半导体装置110。
例如,半导体装置CP12、CP22、CP32及CP42是电力用晶体管(例如IGBT:Insulated Gate Bipolar Transistor,绝缘栅双极型晶体管)。此外,例如,半导体装置CP11、CP21、CP31及CP41是电力用二极管(例如FRD:Fast Recovery Diode,快速恢复二极管)。
各半导体装置CP11、CP12、CP21、CP22、CP31、CP32、CP41及CP42分别经由接合线(Bonding wire)93与导体图案52电连接。
在各基板50上,例如设置有作为栅极的端子T1、作为集电极的端子T2以及作为发射极的端子T3。由这些半导体装置CP11、CP12、CP21、CP22、CP31、CP32、CP41及CP42构成变换器等规定的电路。
如图4所示,基板50安装在底板70之上。在基板50的支撑部51的背面设置有导体膜53。基板50的导体膜53经由焊料等接合件65接合在底板70之上。
在底板70的下表面可以设置有散热片80。散热片80经由例如导热硅脂(Thermal grease)75连接在底板70的下表面上。
在底板70之上,基板50、半导体装置110及接合线93被外壳90包围。在外壳90内,也可以填充有保护及散热用的凝胶95。
在这样的半导体模块210中,即使在半导体装置110成为高温的情况下,也能够维持半导体装置110与基板50的接合部的高可靠性。尤其,如图5所示,在半导体模块210内设置有多个半导体装置110的情况下,外壳90内的温度容易变高。即使是包括多个半导体装置110的半导体模块210,也能够确保足够的可靠性。
接着,说明中间层40。
图6(a)及图6(b)是例示中间层的图。
在图6(a)中,示出表示中间层40的配置例的示意性剖视图。在图6(b)中,示出例示图6(a)的A部处的组织的状态的示意性剖视图。
半导体模块210也可以具备中间层40。
如图6(a)所示,中间层40设置在金属膜20的第1膜21-1与基板50的导体图案52之间。中间层40具有比导体图案52的导热系数低的导热系数。中间层40只要是第1膜21-1与导体图案52之间,就可以配置在任何位置。在作为导体图案52而使用Cu的情况下,中间层40例如使用不锈钢。中间层40的厚度为约10微米(μm)。
通过设置中间层40,从半导体元件10经由金属膜20及接合件60向导体图案52传递的热的阻挡性比不设置中间层40的情况高。由此,难以经由基板50向外部释放。因此,例如能够保护位于基板50的外侧且外壳90的内侧的部件(例如凝胶95)免受热的影响。在设置有中间层40的情况下,热被切断,半导体元件10的温度上升,因此优选在金属膜20中含Cr。由此,如上述说明那样,金属膜20的厚度的减小变少,产生裂纹的情况得到抑制。
另外,在本实施方式中,作为半导体元件10的材料,使用SiC、GaN等能够进行高温动作的材料。因此,即使设置中间层40从而朝向基板50侧的热的传导性降低,也不会对半导体元件10的动作带来影响。
对于具备这样的中间层40的半导体模块210,若进行50000次通过通电/非通电使半导体元件10在100℃与200℃之间进行温度上升、温度下降的循环,则导体图案52成为图6(b)所示的组织。导体图案52使用Cu。
图7(a)及(b)是表示参考例的图。
在图7(a)中,示出表示不具备中间层40的配置例的示意性剖视图。在图7(b)中,示出例示图7(a)的B部处的组织的状态的示意性剖视图。对于参考例,若进行50000次与上述相同的温度上升、温度下降的循环,则导体图案52成为图7(b)所示的组织。
如图6(b)所示可知,在具备中间层40的例子中,残留有导体图案52的Cu中的初始的晶粒,几乎不受到热循环的影响。另一方面,如图7(b)所示可知,在不具备中间层40的参考例中,导体图案52的Cu中的晶粒生长得比图6(b)的晶粒大。
在具备中间层40的例子中,接合件60的裂纹发展率为约15%。另一方面,在不具备中间层40的例子中,接合件60的裂纹发展率为约85%。在此,裂纹发展率是裂纹的长度相对于将半导体装置110和基板50接合的接合件60的接合长度的比例。
这样,通过设置中间层40,导体图案52的组成变化得到抑制,能够获得半导体模块210的长期使用中的高可靠性。
图8(a)及图8(b)是例示中间层的结构的示意性剖视图。
图8(a)所示的中间层40A包括中间部件41和外侧部件42。中间层40A具有由2片外侧部件42夹持中间部件41的构造。中间部件41例如使用厚度约10μm的不锈钢。外侧部件42例如使用厚度约10μm的Ni。由于在不锈钢的表面形成氧化膜,因此采用由Ni的外侧部件42夹持不锈钢的中间部件41的构造。由此,使用时的在层间的剥离得到抑制。
图8(b)所示的中间层40B包括中间部件41B和外侧部件42。中间层40B具有由2片外侧部件42夹持中间部件41B的构造。中间部件41B具有在图8(a)所示的中间部件41的一部分设置有中空部43的结构。中间部件41B例如在不锈钢箔中设置有多个孔而成。该孔成为中空部43。如中间层40B那样,在内部具有中空部43的构造中,通过中空部43,将热有效地切断。
通过使用这样的中间层40A及40B,能够获得可靠性更高的半导体模块210。
另外,在使用中间层40、40A及40B的半导体模块210中,也可以使用除了Cr以外的材料(例如Ni、Ag),来作为金属膜20的最表面20a侧所含的材料。
如以上说明那样,根据实施方式,能够提供提高了可靠性的半导体装置及半导体模块。
另外,以上说明了本实施方式,但本发明不限定于这些例子。例如,在本领域技术人员对上述各实施方式适当地进行了构成要素的追加、删除、设计变更的情况、或适当地组合了各实施方式的特征的情况下,只要具备本发明的主旨,就包含在本发明的范围内。
说明了本发明的几个实施方式,但这些实施方式仅是示例,不限定发明的范围。这些新颖的实施方式能够以其他各种方式来实施,在不脱离发明的主旨的范围内,能够进行各种省略、替换、变更。这些实施方式及其变形包含在发明的范围及主旨中,并且包含在权利要求书中所记载的发明及其等价的范围内。
Claims (20)
1.一种半导体装置,具备:
半导体元件,具有第1面以及与第1面相反的一侧的第2面;和
含铬(Cr)的金属膜,设置在上述半导体元件的上述第2面。
2.根据权利要求1所述的半导体装置,其中,
上述半导体元件含有动作确保温度比硅(Si)的动作确保温度高的材料。
3.根据权利要求2所述的半导体装置,其中,
上述材料含有硅碳化物(SiC)及氮化镓(GaN)中的某1种。
4.根据权利要求1所述的半导体装置,其中,
上述金属膜具有:
含铬(Cr)的第1膜,设置在最表面侧;和
第2膜,设置在上述第1膜与上述第2面之间。
5.根据权利要求4所述的半导体装置,其中,
上述第2膜含有从由钛(Ti)、铝(Al)、金(Au)、锡(Sn)、镍(Ni)、银(Ag)构成的组中选择的至少1种。
6.根据权利要求4所述的半导体装置,其中,
上述第2膜是多层膜,上述多层膜中的至少1个膜含有从由钛(Ti)、铝(Al)、金(Au)、锡(Sn)、镍(Ni)、银(Ag)构成的组中选择的至少1种。
7.一种半导体模块,具备:
半导体装置,包括具有第1面及与第1面相反的一侧的第2面的半导体元件、以及设置在上述半导体元件的上述第2面上且含铬(Cr)的金属膜;
基板,具有导体图案;以及
接合件,设置在上述金属膜与上述导体图案之间。
8.根据权利要求7所述的半导体模块,其中,
上述导体图案含有铜(Cu)。
9.根据权利要求7所述的半导体模块,其中,
上述接合件含有锡(Sn)或银(Ag)。
10.根据权利要求7所述的半导体模块,其中,
还具备中间层,该中间层设置在上述金属膜与上述导体图案之间,具有比上述导体图案的导热系数低的导热系数。
11.根据权利要求10所述的半导体模块,其中,
上述中间层含有不锈钢。
12.根据权利要求10所述的半导体模块,其中,
上述中间层具有中间部件和一对外侧部件,
上述中间部件由上述一对外侧部件夹持,
上述中间部件含有上述不锈钢,
上述外侧部件含有镍(Ni)。
13.根据权利要求10所述的半导体模块,其中,
在上述中间层的一部分设置有中空部。
14.根据权利要求13所述的半导体模块,其中,
上述中间层具有中间部件和一对外侧部件,
上述中间部件由上述一对外侧部件夹持,
在上述中间部件上设置有上述中空部。
15.根据权利要求14所述的半导体模块,其中,
上述中空部是设置在上述中间部件的孔。
16.根据权利要求7所述的半导体模块,其中,
上述半导体元件含有动作确保温度比硅(Si)的动作确保温度高的材料。
17.根据权利要求7所述的半导体模块,其中,
上述材料含有硅碳化物(SiC)及氮化镓(GaN)中的某1种。
18.根据权利要求7所述的半导体模块,其中,
上述金属膜具有:
含铬(Cr)的第1膜,设置在最表面侧;和
第2膜,设置在上述第1膜与上述第2面之间。
19.根据权利要求18所述的半导体模块,其中,
上述第2膜含有从由钛(Ti)、铝(Al)、金(Au)、锡(Sn)、镍(Ni)、银(Ag)构成的组中选择的至少1种。
20.根据权利要求18所述的半导体模块,其中,
上述第2膜是多层膜,上述多层膜中的至少1个膜含有从由钛(Ti)、铝(Al)、金(Au)、锡(Sn)、镍(Ni)、银(Ag)构成的组中选择的至少1种。
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JPS61117845A (ja) * | 1984-11-14 | 1986-06-05 | Hitachi Micro Comput Eng Ltd | 半導体装置 |
CN85109419A (zh) * | 1984-12-28 | 1986-06-10 | 株式会社东芝 | 半导体器件 |
JPS61125025A (ja) * | 1984-11-22 | 1986-06-12 | Hitachi Ltd | 半導体装置の製造方法 |
US20120208323A1 (en) * | 2011-02-10 | 2012-08-16 | Infineon Technologies Ag | Method for Mounting a Semiconductor Chip on a Carrier |
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JPS55143042A (en) * | 1979-04-25 | 1980-11-08 | Hitachi Ltd | Semiconductor device |
US4574470A (en) * | 1984-03-19 | 1986-03-11 | Trilogy Computer Development Partners, Ltd. | Semiconductor chip mounting system |
GB2268304B (en) * | 1992-06-26 | 1994-11-16 | Motorola As | A display |
US6242280B1 (en) * | 1999-06-30 | 2001-06-05 | Agilent Technologies, Inc. | Method of interconnecting an electronic device |
DE10332017A1 (de) * | 2003-07-14 | 2005-03-03 | Infineon Technologies Ag | Elektronisches Bauteil und Flachleiterrahmen zur Herstellung des Bauteils |
JP4135101B2 (ja) * | 2004-06-18 | 2008-08-20 | サンケン電気株式会社 | 半導体装置 |
US20060124956A1 (en) * | 2004-12-13 | 2006-06-15 | Hui Peng | Quasi group III-nitride substrates and methods of mass production of the same |
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2013
- 2013-09-13 JP JP2013191176A patent/JP2015056646A/ja active Pending
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2014
- 2014-02-17 CN CN201410053381.XA patent/CN104465578A/zh active Pending
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US4480261A (en) * | 1981-07-02 | 1984-10-30 | Matsushita Electronics Corporation | Contact structure for a semiconductor substrate on a mounting body |
GB2138633A (en) * | 1983-04-16 | 1984-10-24 | Toshiba Kk | Bonding semiconductor chips to a lead frame |
JPS61117845A (ja) * | 1984-11-14 | 1986-06-05 | Hitachi Micro Comput Eng Ltd | 半導体装置 |
JPS61125025A (ja) * | 1984-11-22 | 1986-06-12 | Hitachi Ltd | 半導体装置の製造方法 |
CN85109419A (zh) * | 1984-12-28 | 1986-06-10 | 株式会社东芝 | 半导体器件 |
US20120208323A1 (en) * | 2011-02-10 | 2012-08-16 | Infineon Technologies Ag | Method for Mounting a Semiconductor Chip on a Carrier |
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