JP2015056646A - 半導体装置及び半導体モジュール - Google Patents

半導体装置及び半導体モジュール Download PDF

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Publication number
JP2015056646A
JP2015056646A JP2013191176A JP2013191176A JP2015056646A JP 2015056646 A JP2015056646 A JP 2015056646A JP 2013191176 A JP2013191176 A JP 2013191176A JP 2013191176 A JP2013191176 A JP 2013191176A JP 2015056646 A JP2015056646 A JP 2015056646A
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Japan
Prior art keywords
film
semiconductor
metal film
semiconductor device
semiconductor element
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JP2013191176A
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English (en)
Inventor
久里　裕二
Yuuji Kuri
裕二 久里
関谷　洋紀
Hironori Sekiya
洋紀 関谷
遥 佐々木
Haruka Sasaki
遥 佐々木
和也 小谷
Kazuya Kotani
和也 小谷
田多　伸光
Nobumitsu Tada
伸光 田多
仁嗣 松村
Hitotsugu Matsumura
仁嗣 松村
井口　知洋
Tomohiro Iguchi
知洋 井口
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Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2013191176A priority Critical patent/JP2015056646A/ja
Priority to CN201410053381.XA priority patent/CN104465578A/zh
Priority to US14/202,588 priority patent/US20150076516A1/en
Publication of JP2015056646A publication Critical patent/JP2015056646A/ja
Pending legal-status Critical Current

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Abstract

【課題】半導体素子と基板との接合部の信頼性を向上させることができる半導体装置及び半導体モジュールを提供すること。【解決手段】実施形態に係る半導体装置は、半導体素子と、金属膜と、を含む。前記半導体素子は、第１面及び第１面とは反対側の第２面を有する。前記金属膜は、前記半導体素子の前記第２面に設けられる。前記金属膜は、Ｃｒを含む。前記半導体素子は、Ｓｉの動作保証温度よりも高い動作保証温度の材料を含んでいても良い。【選択図】図１

Description

本発明の実施形態は、半導体装置及び半導体モジュールに関する。
半導体素子を基板上にマウントするには、はんだ等の接合材を用いて両者を接続している。このような半導体素子がパッケージ内に収納された半導体モジュールに、冷熱サイクルやパワーサイクル等の負荷を長時間与えた場合、接合部に亀裂が発生する可能性がある。亀裂が進展すると、接合部の破断が発生し、温度抵抗の上昇による接合部の溶融など、故障の原因となる。半導体装置及び半導体モジュールにおいては、信頼性の向上が重要である。
特開平８−４６１３４号公報
本発明の実施形態は、信頼性を向上させることができる半導体装置及び半導体モジュールを提供する。
実施形態に係る半導体装置は、半導体素子と、金属膜と、を含む。
前記半導体素子は、第１面及び第１面とは反対側の第２面を有する。
前記金属膜は、前記半導体素子の前記第２面に設けられる。前記金属膜は、Ｃｒを含む。
図１（ａ）及び図１（ｂ）は、第１の実施形態に係る半導体装置の構成を例示する模式的断面図である。 図２は、半導体装置１１０の実装状態を例示する模式的断面図である。 図３は、恒温試験による金属膜の厚さの変化を例示する図である。 図４は、第２の実施形態に係る半導体モジュールの構成を例示する模式的断面図である。 図５は、半導体モジュール内の実装状態を例示する模式的平面図である。 図６（ａ）及び図６（ｂ）は、中間層を例示する図である。 図７（ａ）及び（ｂ）は、参考例について示す図である。 図８（ａ）及び図８（ｂ）は、中間層の構成を例示する模式的断面図である。
以下、本発明の実施形態を図に基づき説明する。以下の説明では、同一の部材には同一の符号を付し、一度説明した部材については適宜その説明を省略する。
（第１の実施形態）
図１（ａ）及び図１（ｂ）は、第１の実施形態に係る半導体装置の構成を例示する模式的断面図である。
図１（ａ）には、半導体装置１１０の全体の断面図が表される。図１（ｂ）には、半導体装置１１０の金属膜２０の拡大断面図が表される。
図１（ａ）に表したように、本実施形態に係る半導体装置１１０は、半導体素子１０と、金属膜２０と、を備える。
半導体素子１０は、半導体材料に所定の不純物注入プロセスやフォトリソグラフィプロセスなどによって形成された素子領域を含む。素子領域は、トランジスタやダイオード等の能動素子であったり、抵抗やコンデンサ等の受動素子である。半導体素子１０は、半導体材料を含むウェーハ等を矩形に切り出したチップ形状になっている。半導体素子１０は、第１面１０ａと、第１面１０ａとは反対側の第２面１０ｂと、を有する。第１面１０ａは、例えば半導体素子１０の表面であり、第２面１０ｂは、例えば半導体素子１０の裏面である。
金属膜２０は、半導体素子１０の第２面１０ｂに設けられる。金属膜２０は、第２面１０ｂと接する。金属膜２０は、第１膜２１−１を少なくとも含む。図１（ｂ）に表したように、第１膜２１−１は、金属膜２０の最表面２０ａ側に設けられる。半導体装置１１０において、最表面２０ａはクロム（Ｃｒ）を含む。本実施形態では、第１膜２１−１として、実質的に純ＣｒまたはＣｒを含む金属（合金）が用いられる。実質的に純Ｃｒには、意図せず不純物が混入したＣｒを含む。
金属膜２０は、第１膜２１−１のみの単層膜であってもよい。また、金属膜２０は、多層膜であってもよい。
図１（ｂ）に表したように、金属膜２０としてｎ（ｎは２以上の整数）層の多層膜である場合、金属膜２０は、第１膜２１−１〜第ｎ膜２１−ｎを有する。ｎ層の多層膜のうち、最も半導体素子１０の第２面１０ｂから離れた膜を第１膜２１−１とする。第１膜２１−１から第２面１０ｂに向けて、順に第２膜２１−２、第３膜２１−３、…とする。第２面１０ｂに接する膜は第ｎ膜２１−ｎである。
金属膜２０がｎ層の多層膜である場合、第２膜２１−２〜第ｎ膜２１−ｎのうち少なくとも１つは、チタン（Ｔｉ）、アルミニウム（Ａｌ）、金（Ａｕ）、錫（Ｓｎ）、ニッケル（Ｎｉ）、銀（Ａｇ）によりなる群から選択された少なくとも１つを含む。
金属膜２０の具体例を示す。
ｎ＝２、すなわち２層の多層膜の例を示す。
第２膜２１−２はＡｕ、第１膜２１−１はＣｒである。
ｎ＝３、すなわち３層の多層膜の例を示す。
第３膜２１−３はＴｉ、第２膜２１−２はＡｕ、第１膜２１−１はＣｒである。
ｎ＝４、すなわち４層の多層膜の例を示す。
第４膜２１−４はＡｌ、第３膜２１−３はＴｉ、第２膜２１−２はＡｕ、第１膜２１−１はＣｒである。
ｎ＝４、すなわち４層の多層膜の他の例を示す。
第４膜２１−４はＡｌ、第３膜２１−３はＴｉ、第２膜２１−２はＳｎ、第１膜２１−１はＣｒである。
Ｃｒを含む第１膜２１−１の厚さは、例えば５００ナノメートル（ｎｍ）以上７５０ｎｍ以下程度である。
金属膜２０は、例えば真空蒸着、スパッタ、イオンプレーティング、電気めっきによって形成される。第１膜２１−１としてＣｒを用いる場合、表面の酸化を抑制するため、減圧環境下でのドライ製法によって形成することが望ましい。
図２は、半導体装置１１０の実装状態を例示する模式的断面図である。
図２に表したように、半導体装置１１０は、基板５０の上に実装される。基板５０は、支持部５１と、導体パターン５２と、を有する。支持部５１には、例えばセラミックスが用いられる。導体パターン５２には、例えば銅（Ｃｕ）が用いられる。
半導体装置１１０は、接合材６０を介して基板５０の導体パターン５２に接合される。接合材６０には、例えば錫（Ｓｎ）を含むはんだが用いられる。
例えば、半導体装置１１０の稼働時に半導体素子１０に通電されると、半導体素子１０の温度が上昇する。一方、半導体装置１１０の稼働が停止されると、半導体素子１０の温度は低下する。半導体装置１１０の稼働及び停止を繰り返すと、接合材６０であるはんだにひずみが発生する。そして、はんだの再結晶化によって亀裂が発生、さらに進展する。
また、別の要因として、半導体装置１１０の周囲に樹脂モールドが設けられている場合、このモールド部分が、放熱用ベース板基板より剥離する可能性がある。これにより、全体の拘束がなくなり、そのために、はんだ等の接合に亀裂が発生し、進展する可能性がある。
半導体装置１１０の熱は、接合部だけではなく、その下の構成材料である基板５０の導体パターン５２や支持部５１にも伝わる。Ｃｕは、高温で使用されたり、熱抵抗の上昇により発熱が生じた場合は、軟化する場合がある。この軟化はＣｕの温度が再結晶温度以上に上昇した場合に生じる。
半導体装置１１０において、半導体素子１０には、Ｓｉの素子の動作が保証される最も高い温度（動作保証温度）よりも高い動作保証温度の材料が用いられる。例えば、半導体素子１０の材料は、例えばＳｉＣ及びＧａＮのうちいずれか１つを含む。ＳｉＣ、ＧａＮ等のパワーモジュールに使用される材料は、非常に高温で使用されることが期待される。例えば、Ｓｉでは、使用温度領域として１７５℃が限界であったが、ＳｉＣやＧａＮにおいては、２００℃や２５０℃を超える温度領域での使用が可能である。
このような高温で使用される半導体装置１１０において、最表面２０ａにＣｒを含む第１膜２１−１を有する金属膜２０を用いることで、金属膜２０の消失が効果的に抑制される。
接合材６０を介して半導体装置１１０と基板５０とを接合した場合の接合部の信頼性は、冷熱サイクル、パワーサイクル、恒温試験などによって検証される。接合部に負荷をかけた場合、接合材６０に亀裂が発生し、さらに負荷が続くと、その亀裂が進展する場合がある。
図３は、恒温試験による金属膜の厚さの変化を例示する図である。
図３の横軸は時間、縦軸は金属膜の厚さである。図３に示すラインＬ１には、本実施形態に係る半導体装置１１０で適用される金属膜２０の厚さが表され、ラインＬ２には、最表面にＮｉを含む金属膜を用いた場合の金属膜の厚さが表される。この恒温試験では、２００℃の恒温槽にサンプルを２０００時間放置した場合の金属膜の厚さの変化を測定している。
図３のラインＬ１に表したように、本実施形態に係る半導体装置１１０で適用される金属膜２０では、ラインＬ２よりも金属膜２０の厚さの減少が抑制されていることが分かる。すなわち、ラインＬ２に表したように、Ｎｉを含む金属膜を用いた場合には、金属膜の厚さが徐々に減少している。一方、ラインＬ１に表したように、Ｃｒを含む金属膜２０を用いた場合には、金属膜２０の厚さはあまり減少していない。
Ｎｉを含む金属膜を用いた場合、接合材６０に含まれるＳｎがＮｉと化合物を構成し、拡散して消失しているためである。金属膜のＮｉが消失すると、金属膜の変形によって亀裂が発生しやすくなり、接合部分での信頼性の低下を招く。これに対し、Ｃｒを含む金属膜２０を用いた場合には、接合材６０に含まれるＳｎはＣｒと化合物を構成しにくいため、消失による金属膜２０の厚さの減少が抑制される。金属膜２０の厚さの減少が抑制されると、半導体装置１１０の接合部での信頼性が向上する。
このように、本実施形態に係る半導体装置１１０では、例えば２００℃以上の温度が加わっても、金属膜２０の厚さを維持することができる。したがって、半導体装置１１０を基板５０に実装して用いる場合の高温での長期使用において信頼性を向上させることができる。
なお、本実施形態では、金属膜２０の最表面２０ａに含まれる材料としてＣｒを示したが、接合材６０の材料との間で化合物を構成しない、または化合物を構成し難い材料であれば、Ｃｒ以外であってもよい。また、金属膜２０の最表面２０ａに含まれる材料としては、Ｓｉの動作保証温度よりも高い温度を与えた場合でも、消失しない、または消失し難い材料であってもよい。
（第２の実施形態）
次に、第２の実施形態に係る半導体モジュールについて説明する。
図４は、第２の実施形態に係る半導体モジュールの構成を例示する模式的断面図である。
図５は、半導体モジュール内の実装状態を例示する模式的平面図である。
図４に表したように、半導体モジュール２１０は、半導体装置１１０と、基板５０と、接合材６０と、を備える。図４に表した例では、半導体モジュール２１０は、さらに、ベース板７０と、ヒートシンク８０と、ケース９０と、を備える。
第１の実施形態で説明したように、半導体装置１１０は、半導体素子１０と、金属膜２０と、を有する。半導体装置１１０は、基板５０の上に実装される。接合材６０は、半導体装置１１０の金属膜２０と、基板５０の導体パターン５２との間に設けられる。
図４には、半導体モジュール２１０内に１つの半導体装置１１０が表されているが、複数の半導体装置１１０を含んでいてもよい。例えば、図５に表した例では、半導体モジュール２１０内に、半導体装置１１０として、複数の半導体装置ＣＰ１１、ＣＰ１２、ＣＰ２１、ＣＰ２２、ＣＰ３１、ＣＰ３２、ＣＰ４１及びＣＰ４２が設けられている。
さらに、図５に表した例では、２つの半導体装置１１０ごとに１つの基板５０に実装されている。すなわち、図５に表した例では、４つの基板５０が設けられ、各基板５０に２つの半導体装置１１０が実装される。
例えば、半導体装置ＣＰ１２、ＣＰ２２、ＣＰ３２及びＣＰ４２は、電力用トランジスタ（例えば、ＩＧＢＴ：Insulated Gate Bipolar Transistor）である。また、例えば、半導体装置ＣＰ１１、ＣＰ２１、ＣＰ３１及びＣＰ４１は、電力用ダイオード（例えば、ＦＲＤ：Fast Recovery Diode）である。
半導体装置ＣＰ１１、ＣＰ１２、ＣＰ２１、ＣＰ２２、ＣＰ３１、ＣＰ３２、ＣＰ４１及びＣＰ４２のそれぞれは、導体パターン５２とボンディングワイヤ９３を介して電気的に接続される。
各基板５０には、例えばゲートである端子Ｔ１と、コレクタである端子Ｔ２と、エミッタである端子Ｔ３と、が設けられる。これらの半導体装置ＣＰ１１、ＣＰ１２、ＣＰ２１、ＣＰ２２、ＣＰ３１、ＣＰ３２、ＣＰ４１及びＣＰ４２によって、インバータ等の所定の回路が構成される。
図４に表したように、基板５０は、ベース板７０の上に実装される。基板５０の支持部５１の裏面には導体膜５３が設けられる。基板５０の導体膜５３は、はんだ等の接合材６５を介してベース板７０の上に接合される。
ベース板７０の下面には、ヒートシンク８０が設けられていてもよい。ヒートシンク８０は、ベース板７０の下面に例えばサーマルグリース７５を介して接続される。
ベース板７０の上において、基板５０、半導体装置１１０及びボンディングワイヤ９３は、ケース９０によって囲まれる。ケース９０内には、保護及び放熱用のゲル９５が充填されていてもよい。
このような半導体モジュール２１０においては、半導体装置１１０が高温になった場合でも、半導体装置１１０と基板５０との接合部の高い信頼性を維持することができる。特に、図５に表したように、半導体モジュール２１０内に複数の半導体装置１１０が設けられている場合には、ケース９０内の温度が高くなりやすい。複数の半導体装置１１０を含む半導体モジュール２１０であっても、十分な信頼性が確保される。
次に、中間層４０について説明する。
図６（ａ）及び図６（ｂ）は、中間層を例示する図である。
図６（ａ）には、中間層４０の配置例を示す模式的断面図が表される。図６（ｂ）には、図６（ａ）のＡ部における組織の状態を例示する模式的断面図が表される。
半導体モジュール２１０は、中間層４０を備えていてもよい。
図６（ａ）に表したように、中間層４０は、金属膜２０の第１膜２１−１と、基板５０の導体パターン５２と、の間に設けられる。中間層４０は、導体パターン５２の熱伝導率よりも低い熱伝導率を有する。中間層４０は、第１膜２１−１と、導体パターン５２との間であれば、どこに配置されていてもよい。導体パターン５２としてＣｕが用いられている場合、中間層４０には、例えばステンレスが用いられる。中間層４０の厚さは、約１０マイクロメートル（μｍ）である。
中間層４０を設けることで、半導体素子１０から金属膜２０及び接合材６０を介して導体パターン５２に伝わる熱の遮蔽性が、中間層４０を設けない場合に比べて高まる。これにより、基板５０を介して外部に放出されにくくなる。したがって、例えば、基板５０の外側であって、ケース９０の内側にある部材（例えば、ゲル９５）を熱による影響から保護することができるようになる。中間層４０を設ける場合、熱が遮断され、半導体素子１０の温度が上昇するため、金属膜２０にはＣｒを含むことが望ましい。これにより、上記説明したように、金属膜２０の厚さの減少が少なくなり、亀裂発生が抑制される。
なお、本実施形態では、半導体素子１０の材料として、ＳｉＣやＧａＮなど高温動作可能な材料を用いている。したがって、中間層４０を設けて基板５０側への熱の伝導性が低くなっても半導体素子１０の動作には影響を与えない。
このような中間層４０を備えた半導体モジュール２１０について、通電／非通電によって半導体素子１０を１００℃と２００℃との間で温度上昇、温度下降させるサイクルを５００００サイクル行うと、導体パターン５２は、図６（ｂ）に表したような組織になる。導体パターン５２には、Ｃｕが用いられる。
図７（ａ）及び（ｂ）は、参考例について示す図である。
図７（ａ）には、中間層４０を備えていない配置例を示す模式的断面図が表される。図７（ｂ）には、図７（ａ）のＢ部における組織の状態を例示する模式的断面図が表される。参考例について、上記と同様な温度上昇、温度下降のサイクルを５００００サイクル行うと、導体パターン５２は、図７（ｂ）に表したような組織になる。
図６（ｂ）に表したように、中間層４０を備えた例では、導体パターン５２のＣｕにおける初期の結晶粒が残っており、熱サイクルの影響をほとんど受けていないことが分かる。一方、図７（ｂ）に表したように、中間層４０を備えていない参考例では、導体パターン５２のＣｕにおける結晶粒が図６（ｂ）の結晶粒に比べて大きく成長していることが分かる。
中間層４０を備えた例では、接合材６０の亀裂進展率は、約１５％である。一方、中間層４０を備えていない例では、接合材６０の亀裂進展率は、約８５％である。ここで、亀裂進展率は、半導体装置１１０と基板５０とを接合する接合材６０の接合長さに対する亀裂の長さの比率である。
このように、中間層４０を設けることで、導体パターン５２の組成変化が抑制され、半導体モジュール２１０の長期使用における高い信頼性が得られる。
図８（ａ）及び図８（ｂ）は、中間層の構成を例示する模式的断面図である。
図８（ａ）に表した中間層４０Ａは、中間部材４１と、外側部材４２と、を含む。中間層４０Ａは、中間部材４１を２枚の外側部材４２で挟んだ構造を有する。中間部材４１には、例えば厚さ約１０μｍのステンレスが用いられる。外側部材４２には、例えば厚さ約１０μｍのＮｉが用いられる。ステンレスの表面には酸化膜が形成されるため、ステンレスによる中間部材４１を、Ｎｉの外側部材４２で挟む構造を採用する。これにより、使用時の層間での剥離が抑制される。
図８（ｂ）に表した中間層４０Ｂは、中間部材４１Ｂと、外側部材４２と、を含む。中間層４０Ｂは、中間部材４１Ｂを２枚の外側部材４２で挟んだ構造を有する。中間部材４１Ｂは、図８（ａ）に表した中間部材４１の一部に中空部４３を設けた構成を有する。中間部材４１Ｂは、例えばステンレス箔に複数の孔を設けたものである。この孔が中空部４３になる。中間層４０Ｂのように、内部に中空部４３を有する構造では、中空部４３によって熱が効果的に遮断される。
このような中間層４０Ａ及び４０Ｂを用いることで、さらなる信頼性の高い半導体モジュール２１０が得られる。
なお、中間層４０、４０Ａ及び４０Ｂを用いた半導体モジュール２１０では、金属膜２０の最表面２０ａ側に含まれる材料として、Ｃｒ以外の材料（例えば、Ｎｉ、Ａｇ）が用いられてもよい。
以上説明したように、実施形態によれば、信頼性を向上した半導体装置及び半導体モジュールを提供することができる。
なお、上記に本実施形態を説明したが、本発明はこれらの例に限定されるものではない。例えば、前述の各実施形態に対して、当業者が適宜、構成要素の追加、削除、設計変更を行ったものや、各実施形態の特徴を適宜組み合わせたものも、本発明の要旨を備えている限り、本発明の範囲に含有される。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１０…半導体素子、１０ａ…第１面、１０ｂ…第２面、２０…金属膜、２０ａ…最表面、２１−１…第１膜、４０，４０Ａ，４０Ｂ…中間層、４１，４１Ｂ…中間部材、４２…外側部材、４３…中空部、５０…基板、５１…支持部、５２…導体パターン、５３…導体膜、６０…接合材、６５…接合材、７０…ベース板、７５…サーマルグリース、８０…ヒートシンク、９０…ケース、９３…ボンディングワイヤ、９５…ゲル、１１０…半導体装置、２１０…半導体モジュール

Claims (15)

  1. 第１面及び第１面とは反対側の第２面を有する半導体素子と、
    前記半導体素子の前記第２面に設けられ、Ｃｒを含む金属膜と、
    を備えた半導体装置。
  2. 前記半導体素子は、Ｓｉの動作保証温度よりも高い動作保証温度の材料を含む請求項１記載の半導体装置。
  3. 前記材料は、ＳｉＣ及びＧａＮのうちいずれか１つを含む請求項２記載の半導体装置。
  4. 前記金属膜は、最表面側に設けられＣｒを含む第１膜と、前記第１膜と前記第２面との間に設けられた第２膜と、を有する請求項１〜３のいずれか１つに記載の半導体装置。
  5. 前記第２膜は、Ｔｉ、Ａｌ、Ａｕ、Ｓｎ、Ｎｉ、Ａｇによりなる群から選択された少なくとも１つを含む請求項４記載の半導体装置。
  6. 第１面及び第１面とは反対側の第２面を有する半導体素子と、前記半導体素子の前記第２面に設けられ、Ｃｒを含む金属膜と、を含む半導体装置と、
    導体パターンを有する基板と、
    前記金属膜と前記導体パターンとの間に設けれた接合材と、
    を備えた半導体モジュール。
  7. 前記導体パターンは、Ｃｕを含む請求項６記載の半導体モジュール。
  8. 前記接合材は、Ｓｎを含む請求項６または７に記載の半導体モジュール。
  9. 前記金属膜と、前記導体パターンと、の間に設けられ前記導体パターンの熱伝導率よりも低い熱伝導率を有する中間層をさらに備えた請求項６〜８のいずれか１つに記載の半導体モジュール。
  10. 前記中間層は、ステンレスを含む請求項９記載の半導体モジュール。
  11. 前記中間層の一部に中空部が設けられた請求項９記載の半導体モジュール。
  12. 前記半導体素子は、Ｓｉの動作保証温度よりも高い動作保証温度の材料を含む請求項６〜１１のいずれか１つに記載の半導体モジュール。
  13. 前記材料は、ＳｉＣ及びＧａＮのうちいずれか１つを含む請求項６〜１２のうちいずれか１つに記載の半導体モジュール。
  14. 前記金属膜は、最表面側に設けられＣｒを含む第１膜と、前記第１膜と前記第２面との間に設けられた第２膜と、を有する請求項６〜１３のいずれか１つに記載の半導体モジュール。
  15. 前記第２膜は、Ｔｉ、Ａｌ、Ａｕ、Ｓｎ、Ｎｉ、Ａｇによりなる群から選択された少なくとも１つを含む請求項１４記載の半導体モジュール。
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