JPS59193036A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPS59193036A
JPS59193036A JP58066340A JP6634083A JPS59193036A JP S59193036 A JPS59193036 A JP S59193036A JP 58066340 A JP58066340 A JP 58066340A JP 6634083 A JP6634083 A JP 6634083A JP S59193036 A JPS59193036 A JP S59193036A
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JP
Japan
Prior art keywords
chip
tin
brazing material
semiconductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58066340A
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English (en)
Other versions
JPH0226376B2 (ja
Inventor
Toshio Tetsuya
鉄矢 俊夫
Hiroyuki Baba
博之 馬場
Osamu Usuda
修 薄田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58066340A priority Critical patent/JPS59193036A/ja
Priority to DE19843413885 priority patent/DE3413885A1/de
Priority to GB08409512A priority patent/GB2138633B/en
Publication of JPS59193036A publication Critical patent/JPS59193036A/ja
Publication of JPH0226376B2 publication Critical patent/JPH0226376B2/ja
Granted legal-status Critical Current

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    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 [ブト明の技術分野1 この発明は半導体装置に関し、特にスズ−銅合金から成
るろう材によって半導体チップが配設台上に固定されて
いることを特徴とηる半う9体装昭に関するものである
[発明の技術的背骨1] 従来、半導体チップを配設台に接合する場合、予め半導
体チップの底面にバナジウム層を被着させ、更に該バナ
ジウム層に積層させてニッケル層を形成しI〔後、配設
台表面と該ニッケル層とを金・ゲルマニウム(All−
GO)合金からなるろう月で接合している(特願昭53
−91 /1158.1.1願昭53−914.16号
)。
しかしながら、このJ、うな接合部を右りる従来の半導
体装置には次のような欠点かあつlこ。
[背景技術の問題点、I 前記のごとぎ接合部を有する従来の半導体装置において
は、該半導体装置がICとえば高湿度の雰囲気中で使用
された場合、ニッケル層とA u−Ge合金中の金どの
間に局部電池が形成されてニッケル層か電食され、その
結果、該半導体装置の電気的特性が悪化したり、あるい
は半導体チップか配設台から剥離する等の事故を発生す
る重大な欠点があった。 また、ろう祠として用いられ
Cいる△u−13e合金【31圭成分が金であるため極
めて高価であり、A u−Ge合金をろう拐として用い
ることは半導体装置の」スト低減化を■む一要因にもな
っていl〔。
[発明の目的] 従って、この発明の目的は電食を生ずるおそれがなく、
目つ従来よりも低コス1〜で製造づることのできる改良
された半導体装置を提供することである。
[発明の1a!要] 本発明者は、スス−銅合金においてススと銅はそれぞれ
同一蒸気圧下での温度がほぼ同一であり(因みに、0.
IT orrにおいてススは1685°K。
銅は1690°にである)従って、蒸着さけたスズ−銅
合金組成が蒸着源合金組成と全く等しくなるように形成
ざUることか可能であること、またスズ−銅合金は比較
的低温で溶融する(たとえばスス38〜92.4%で残
部が銅から成るスズ−銅合金の場合、混融点は415℃
)うえ、高湿度雰囲気中でもニッケルとの間に局部゛電
池を形成しないこと及びA IJ−G e合金にくらべ
てはるかに安価であること等の条件を備え′Cいること
に着目し、スズ−銅合金をろう材として用いることによ
り本発明の半導体装置を得た。
[発明の実施例コ 以下に添イ」図面を参照して本発明の一実施例を説明づ
る。
第1図におい−C1は半導体ヂッf、5は配設台、2は
バナジウム層、3はニラ9ル層、4はろう祠としてのス
ズ−銅合金層である。 このJ:う’tK 4F+造の
本発明の2r導体装置をたとえば以上のことさT程及び
条イ′1で製作した。
まず、半導体チップとして分υjりる前の半導体ウェハ
の裏面(こバナジウム1萌2を300久・〜・700X
の厚ざに被着させた後、該バナジウノ、層2の表面にニ
ッケル層3を10 (l O久〜300 (l久の11
;さ−C形成させる。 更に該ニッケル層3の表…jに
、スス38−92.4%で残分が銅り日らなるスス−銅
合金層4を蒸着法により5000人〜3μm厚さに被ン
′1させる。そして前記三層の金属層を裏面に形成した
半導体・り]胃\をスクライブして個々の半導体チップ
毎に分割すると、前記三層の金属層2〜4を裏面に備え
た半7.14 (本チップ1が得られる。
一方、配設台5〕を415°C以上の温度に加熱してお
き、該配設台5十に前記半導体チップ1のスズ−銅合金
層4を押圧ザることにより、スズ−銅合金層4が融解し
、冷却後には再び固化して半導体デツプ1と配設台5と
が相互に固着される。  ・[発明の効果] 前記のごどぎ本発明の半導体装置に対して、2気圧の圧
力下で約300時間のプレッシャークツカーテス1〜を
行ったところ、電気的特性の低下は全く現れず、また半
導体チップの剥離も全く生じなかった。 因みに、従来
の半導体装置に対して上記と同一条件でプレッシャーク
ツカーテストを実施した場合、ニッケル層が電食されて
半導体チップが配設台5上から剥離し、まlζ半導体チ
ップの電気的特性が悪化りるのが普通であった。
以上のように、この発明によれば、 (I)  電食による電気的特↑9の悪化、t″JJ電
食、る半導体デツプの剥離等を生ずる恐れがなく、(I
f)  製造」ス1へを署しく低減づることがてぎる(
因みに、スズ−銅合金は従来使用されているΔ叶Ge合
金のl111i格の1/10以下であり、また11φ終
的歩留りを考慮すれば更にコスト低下になる)、等の長
所をfiillえた半導体装置が提供される。
【図面の簡単な説明】
第1図は本発明の半導体装置の111面図である。 1・・・半導体ヂッj、 2・・・バナジウム層、 3
・・・ニッケル層、 4・・・スズ−銅合金層、 5・
i12設台。 特許出願人 東京芝浦電気株式会社

Claims (1)

  1. 【特許請求の範囲】 1 スズ−銅合金から成るろう月によって半導体チップ
    を配設台上に固定したことを特徴とする半導体装置。 2 スス−銅合金から成るろう材が、スズ38〜92.
    4重量%そして残分が銅の組成をもつものである特許請
    求の範囲第1項記載の半導体装置。 3 半導体チップが、該チップ底面にバナジウム層を被
    着させ、さらに該バナジウム層に積層さけてニッケル層
    を被着させたものである特許請求の範囲第1項又は第2
    項記載の半導体装向。
JP58066340A 1983-04-16 1983-04-16 半導体装置の製造方法 Granted JPS59193036A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP58066340A JPS59193036A (ja) 1983-04-16 1983-04-16 半導体装置の製造方法
DE19843413885 DE3413885A1 (de) 1983-04-16 1984-04-12 Halbleitervorrichtung
GB08409512A GB2138633B (en) 1983-04-16 1984-04-12 Bonding semiconductor chips to a lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58066340A JPS59193036A (ja) 1983-04-16 1983-04-16 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS59193036A true JPS59193036A (ja) 1984-11-01
JPH0226376B2 JPH0226376B2 (ja) 1990-06-08

Family

ID=13313027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58066340A Granted JPS59193036A (ja) 1983-04-16 1983-04-16 半導体装置の製造方法

Country Status (3)

Country Link
JP (1) JPS59193036A (ja)
DE (1) DE3413885A1 (ja)
GB (1) GB2138633B (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61156823A (ja) * 1984-12-28 1986-07-16 Toshiba Corp 半導体装置
JPS62229848A (ja) * 1986-03-29 1987-10-08 Toshiba Corp 半導体装置
US4954870A (en) * 1984-12-28 1990-09-04 Kabushiki Kaisha Toshiba Semiconductor device
WO2006016479A1 (ja) * 2004-08-10 2006-02-16 Neomax Materials Co., Ltd. ヒートシンク部材およびその製造方法
JP2013052430A (ja) * 2011-09-06 2013-03-21 Sanyo Special Steel Co Ltd 鉛フリー接合材料

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3446780A1 (de) * 1984-12-21 1986-07-03 Brown, Boveri & Cie Ag, 6800 Mannheim Verfahren und verbindungswerkstoff zum metallischen verbinden von bauteilen
JPS63110765A (ja) * 1986-10-29 1988-05-16 Sumitomo Metal Mining Co Ltd Ic用リ−ドフレ−ム
US7830001B2 (en) 2005-05-23 2010-11-09 Neomax Materials Co., Ltd. Cu-Mo substrate and method for producing same
US20100247955A1 (en) 2006-09-29 2010-09-30 Kabushiki Kaisha Toshiba Joint with first and second members with a joining layer located therebetween containing sn metal and another metallic material; methods for forming the same
JP2008221290A (ja) * 2007-03-14 2008-09-25 Toshiba Corp 接合体および接合方法
JP5253794B2 (ja) * 2006-12-25 2013-07-31 山陽特殊製鋼株式会社 鉛フリー接合用材料およびその製造方法
JP5744080B2 (ja) * 2013-02-04 2015-07-01 株式会社東芝 接合体および半導体装置
JP2015056646A (ja) * 2013-09-13 2015-03-23 株式会社東芝 半導体装置及び半導体モジュール

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5521106A (en) * 1978-07-31 1980-02-15 Nec Home Electronics Ltd Method of forming ohmic electrode
JPS55107238A (en) * 1979-02-09 1980-08-16 Hitachi Ltd Semiconductor device and method of manufacturing the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB907734A (en) * 1959-06-06 1962-10-10 Teizo Takikawa Method of soldering silicon or silicon alloy
DE1298387C2 (de) * 1964-02-06 1973-07-26 Semikron Gleichrichterbau Halbleiter-Anordnung
GB1389542A (en) * 1971-06-17 1975-04-03 Mullard Ltd Methods of securing a semiconductor body to a support
US3821785A (en) * 1972-03-27 1974-06-28 Signetics Corp Semiconductor structure with bumps
DE2514922C2 (de) * 1975-04-05 1983-01-27 SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg Gegen thermische Wechselbelastung beständiges Halbleiterbauelement
JPS592175B2 (ja) * 1978-07-28 1984-01-17 株式会社東芝 半導体装置
DE2930789C2 (de) * 1978-07-28 1983-08-04 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Halbleitervorrichtung
JPS592174B2 (ja) * 1978-07-28 1984-01-17 株式会社東芝 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5521106A (en) * 1978-07-31 1980-02-15 Nec Home Electronics Ltd Method of forming ohmic electrode
JPS55107238A (en) * 1979-02-09 1980-08-16 Hitachi Ltd Semiconductor device and method of manufacturing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61156823A (ja) * 1984-12-28 1986-07-16 Toshiba Corp 半導体装置
US4954870A (en) * 1984-12-28 1990-09-04 Kabushiki Kaisha Toshiba Semiconductor device
JPS62229848A (ja) * 1986-03-29 1987-10-08 Toshiba Corp 半導体装置
WO2006016479A1 (ja) * 2004-08-10 2006-02-16 Neomax Materials Co., Ltd. ヒートシンク部材およびその製造方法
US7776452B2 (en) 2004-08-10 2010-08-17 Neomax Materials Co. Ltd. Heat sink member and method of manufacturing the same
JP2013052430A (ja) * 2011-09-06 2013-03-21 Sanyo Special Steel Co Ltd 鉛フリー接合材料

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JPH0226376B2 (ja) 1990-06-08
GB2138633B (en) 1986-10-01
GB2138633A (en) 1984-10-24
DE3413885C2 (ja) 1990-02-22
DE3413885A1 (de) 1984-10-25

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