JPS5944834A - 電子回路素子のダイボンデイング方法 - Google Patents

電子回路素子のダイボンデイング方法

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Publication number
JPS5944834A
JPS5944834A JP15569182A JP15569182A JPS5944834A JP S5944834 A JPS5944834 A JP S5944834A JP 15569182 A JP15569182 A JP 15569182A JP 15569182 A JP15569182 A JP 15569182A JP S5944834 A JPS5944834 A JP S5944834A
Authority
JP
Japan
Prior art keywords
die
electronic circuit
bonding
substrate
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15569182A
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English (en)
Inventor
Kazuo Mizuno
和夫 水野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15569182A priority Critical patent/JPS5944834A/ja
Publication of JPS5944834A publication Critical patent/JPS5944834A/ja
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［発明の技術分野１ 本発明は崖導体集積回路（以下１ｃどいつ）等の電子回
路素子のダイボンディング方法に係り、特に混成集積回
路に（１３りる電子回路素子の交換を容易にした電子回
路素子のダイボンディング方法に関りる。
［発明の技術的１Ｌｌｒ景１ 従来Ｊ、り電子回路素子どしてのＩＣチップの組込／Ｊ
法としＣ１例えばワイヤボンディング法が知られ（いる
が、この組込みに（ユワイ〜７ボンデイングエ程に先だ
ってＩＣチップをリードフレームやセラミックパッケー
ジ基板あるいは混成集積回路基板上の所定の位置に上向
き（ノ１イスｊｉツブ）に固定するダイボンディング工
程が必要である。
これはＩＣチップの基板に対りる機械的保持、電気的接
続および熱拡散の目的で“なされるものであるが、従来
このようなＩＣチップをダイポンプ゛イングする方法と
しＣ次のＪ、うＱ　ｂのか知られＣいる。
（イ〉基板上面の導体面に形成した八〇めっき層とＩＣ
チップ本体づなわらシ１蒐二１ンチッゾ（以上３ｉチッ
プという）裏面とを接合さけ、ΔＩｉ　−３１合金の共
晶点以上の温度に加熱してＡｕ　−３ｉ共共晶台により
ダイボンディングケる共晶含金法、。
（ｒ：Ｉ　）　３　ｉチップの裏面にＡｕ、ＮｉＷのＮ
’　ＩＩＩイｔ］り可能な金属を蒸着し、基板上面の導
体面との間をＰｉ−３ｎ合金あるいはＡＩＪ−３ｎ合金
等のミ１′［１１材料を介在さｉ！【ダイボンディング
接合りる２１′田接続法。
（ハ）基板−１−面の材質を特定物質に限定づることな
く、３ｆチツプ裏面との間をΔＵ、Ａ９等をフィシ−と
しく金石する導電性エポキシ樹脂Ｃ接合し、ダイボンデ
ィング°りる導電（’）樹脂後着払。
［背姐技術の問題点１ しかしイｃがら、上述したような１ｃナツゾのダイポン
プイングツ）法に４５いては、ＩＣチップの取外し交換
が行なわれることのないモノリシックＩＣにａ３いでは
問題が生じないが、多数のＩＣデツプや一般のチップ部
品を回路基板上に実装Ｊ８瀝成果積回路にあっＣは次の
Ｊ、うな欠点が生ずる。
すなわら、実装されるＩＣチップの一つに不良が発生し
た場合、不良のＩＣチップのみを交換Ｊることが′Ｃき
れは、全体を破棄処分することなく軽浩的であるが、Ｉ
Ｃチップのグイボンディング方法とし−（、前述の（イ
）の共晶合金法を採用する場合には、ＩＣチップの交換
をＡｕ−３ｆ合金の共晶温度（３７０℃程度）以上０行
なわな（）ればならないのＣ′、交換時に他のコンデン
リチップ等の性能低トが（１−じ、最も困九であるので
、通常、混成集積回路にａ３いＣは使用され４ｆい。
また上記（ロ）の半ｌ」接続法においては、低融点半田
を使用りる場合、ＩＣチップの交換が最も容易であるが
、接合の際にフラックスレスの半田処理を施すために特
殊な炉を通過さける必東があり、また、接合部内に空隙
が発生し易い、Ｓ＊＋−ツブどの接合部界面にＡＬＩＳ
１１脆弱層が形成されＣ１信頼性が低下づる等の難点を
４１しＣいる。
さらに、（ハ）の導電性樹脂接着法は、接合面相互の材
料に限定されず最も絹込みが容易（あるが、ＩＣチップ
の交換が、導電性−１ニポキシ樹ｎ）７の軟化温度以上
の加熱による機械的剥離にＪ、す（ｊなわれる。そのた
め、加熱■稈を必要どりるうえ、剥１１１１１　ｔｌる
際に残る導電性エポキシ樹脂層を洗浄Ｊる■程が必要と
なり、交換工程か複層１どなる等の問題点がある。
［発明の目的」 本発明はこのような従来の欠！気を解消りく）ためにな
されたちのＣ１基根への電子回路累−ｒの絹込みおよび
交換を簡単な■稈Ｃ・、かつ信頼ｐｌｊ　（１）商い接
合部を容易に、Ｊ、た経演的に得ることのＣきるＩｆ回
路素子のダイボンディング方法を提供づることを［１的
どじ−（いる。
［発明の概要］ 本Ｑ明の電子回路素子のグイボンディング方法は、電子
回路素子を基板上へダイボンディングするにあたり、予
め１−配電子回路素子の裏面に低融点金属Ｊこりなる被
膜を形成し、この被膜と上記基板どの間に導電性樹脂組
成物を介しＣ接合することを特徴とづるｂのひある。
１発明の実施例］ １スト木発明の詳細な説明する。
第１図は接合前のＩＣチップの断面図を示したものｒ、
ｓ＊デツプ１の回路形成面２と反対面すなわち接合面側
には、低融点金属例えばＰＩ）　−８１１半１１」めつ
ぎ層３を形成する。
次に、ヒラミックＪ、りなる例えば混成集積回路基板４
の上面に、例えば厚膜ＡＬ＋よりなるダイパッド５を形
成しく　ａ３　ｅ　、第２図に承りように、３ｉデツプ
１のｌ：）ｌ）−３１１半田めっき層３とダイパラ１〜
５の間に導電性エポキシ樹脂接着剤６（例えば１ヨｌ）
　０−　Ｔ　Ｅ　Ｋ社製１〜＋２０−Ｅ接着剤）を介し
くダイボンディングする。
３ｉチツプ１の裏面に予め形成きれる低ｌＩ点金属から
なる被膜としては、Ｉｎ、Ｐｂ−８ｎ合金等の他にＢｉ
　、Ｐｂ　、３ｎ　、　ｃｄを主成分とＪる二〜三元系
の易溶合金（ｆｕｓｉｂｌｅ△１ｌｏｙ）やこれらに微
量のＡ（＋を添加しＩＣ合金が使用される。
また、前記導電性樹脂接着剤６としＣは、」ポ４゛シ合
成樹脂に導電性フィラー材とし′ＣΔす、Δ＋ｉ、Ｃｕ
、Ａρを配合したものが適する。
さらにダ２イパッド５どしては、八〇の他にΔｇ、Ｎｉ
、ｃｌ、Ａｆｉ、八〇　−Ｐｄ　、　Ａｕ　−Ｐｔ　、
△ａ−Ｆ−’を等の金属あるいは合金を使用することが
可能である。
なお、３ｉチツプ１と基板４とのダイボンディングは、
従来の導電性樹脂接着法と同様であり、一般的な自動マ
ウンターを使用し゛（イボなねれる。
このようなダイボンディング方法によつＣ接合された３
ｉチツプを交換Ｊるため取外り場合には、ツール（図示
１！　−１’　）を３ｉ阜板１の上面に接触させ、ρｉ
＋−３ｎず田めっぎ層３の融点温度以上でか゛つ導電性
エポキシ樹脂接着剤６の軟化湿態以下にＳｉ基板１を加
熱し、これを吸着して引き上げることにＪ、っＣ第３図
に示Ｊにうにｒ’ｂ−ｓｎ半１］］めっき層３を分割さ
ＩＩＣ容易に取り外しができる。
従っ（１）１１−８１１半１１」めっぎ層３は、取り外
された３ｉ基板１土面ど導電性エポキシ樹脂接着剤６に
面の双方に分かれで残ることになる。
イこＣＩＣＩＣブラダ換するには、３ｉ基板１土にｉ）
、１１−３　ＩＩ半１］１めつぎ層が形成された新しい
ＩＣブーツブのそのめっぎ層ど導電性エポキシ樹脂接着
剤（ｊ」：のＰｂ−８ｎ半川の残存層３′とを勇ねた後
、半１１の融点以上に加熱することにより、双りのｐ　
ｂ−８１１半１１Ｊ３．３−を溶解し容易に行なうこと
ができる。
な（Ｉ３この場合、半ＩＪＩめっぎ層３どしＣは交換俊
の結合力が損われないような材料を選択する必要がある
。
また、上述の実施例においては、電子回路格子としＵＩ
ＧＩＣチップイホンディングする例をμ）明したが、Ｉ
Ｃチップと同様な構成の一般的な゛電子回路素子におい
ても応用可能Ｃ゛ある。
［発明の効果］ 以上説明したように本発明の゛Ｃｈ子回路糸ｒのグイボ
ンディング方法は、電子回路素子に形成さ゛れた低融点
金属被膜と基板とを導電ＩＪ１樹脂組成物を介し゛Ｃダ
イボンディングすることにＪ、す、電子回路格子の基板
への接合８３　Ｊ、び取外しが極め（容易となり、しか
も通常のグイボンディング装置を用いて行なうことがで
きるのＣ１自動化に適りる。
さらに、゛電子回路素子の交換時の発生層が捗めＣ少な
く、また基板に機械的損傷をノブえることがないため、
信頼性が極めて高くなる川魚をイｊづる。
【図面の簡単な説明】
第１図は本発明の実施例におい′ＣＣ根板−１グイボン
ディングする前の電子回路素子を小’Ｊ　１１７ｉ面図
、第２図は本発明によるダイボンｊ゛イング後の状態を
示り断面図、第３図は本発明にＪ、つＣダイ小ンデイン
ク凸れた電子回路素子を取外した状態を示１Ｗ１面図Ｃ
ある。 １・・・・・・・・・・・・電子回路素子（ＩＣチップ
）３・・・・・・・・・・・・低融点金属被膜（ｌ〕ｌ
＋−３ｎ半田めっき層） ４・・・・・・・・・・・・基板 ５・・・・・・・・・・・・ダイパッド６・・・・・・
・・・・・・Ｓ電性樹脂組成物代理人弁理−１須　山　
仏　− 第１図 第２図 斗 第５図

Claims (1)

    【特許請求の範囲】
  1. （１）電子回路素子を基板上ヘダイボンデイングするに
    あたり、予め前記電子回路素子の裏面に低融点金属より
    なる被膜を形成し、この被膜ど前記基板との間に導電性
    樹脂組成物を介して接合することを特徴とＪる電子回路
    素子のダイボンディング工程法。
JP15569182A 1982-09-07 1982-09-07 電子回路素子のダイボンデイング方法 Pending JPS5944834A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15569182A JPS5944834A (ja) 1982-09-07 1982-09-07 電子回路素子のダイボンデイング方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15569182A JPS5944834A (ja) 1982-09-07 1982-09-07 電子回路素子のダイボンデイング方法

Publications (1)

Publication Number Publication Date
JPS5944834A true JPS5944834A (ja) 1984-03-13

Family

ID=15611432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15569182A Pending JPS5944834A (ja) 1982-09-07 1982-09-07 電子回路素子のダイボンデイング方法

Country Status (1)

Country Link
JP (1) JPS5944834A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4871405A (en) * 1988-03-30 1989-10-03 Director General, Agency Of Industrial Science And Technology Method of bonding a semiconductor to a package with a low and high viscosity bonding agent
US4897704A (en) * 1983-01-10 1990-01-30 Mitsubishi Denki Kabushiki Kaisha Lateral bipolar transistor with polycrystalline lead regions
JPH04109530U (ja) * 1991-03-07 1992-09-22 日本電気株式会社 半導体装置
US5268048A (en) * 1992-12-10 1993-12-07 Hewlett-Packard Company Reworkable die attachment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897704A (en) * 1983-01-10 1990-01-30 Mitsubishi Denki Kabushiki Kaisha Lateral bipolar transistor with polycrystalline lead regions
US4871405A (en) * 1988-03-30 1989-10-03 Director General, Agency Of Industrial Science And Technology Method of bonding a semiconductor to a package with a low and high viscosity bonding agent
JPH04109530U (ja) * 1991-03-07 1992-09-22 日本電気株式会社 半導体装置
US5268048A (en) * 1992-12-10 1993-12-07 Hewlett-Packard Company Reworkable die attachment

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