JP2013098481A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2013098481A
JP2013098481A JP2011242437A JP2011242437A JP2013098481A JP 2013098481 A JP2013098481 A JP 2013098481A JP 2011242437 A JP2011242437 A JP 2011242437A JP 2011242437 A JP2011242437 A JP 2011242437A JP 2013098481 A JP2013098481 A JP 2013098481A
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Japan
Prior art keywords
layer
plating layer
semiconductor chip
substrate
thickness
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JP2011242437A
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English (en)
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Hiroshi Kawakubo
弘史 川久保
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Sumitomo Electric Device Innovations Inc
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Sumitomo Electric Device Innovations Inc
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Application filed by Sumitomo Electric Device Innovations Inc filed Critical Sumitomo Electric Device Innovations Inc
Priority to JP2011242437A priority Critical patent/JP2013098481A/ja
Priority to US13/668,762 priority patent/US9082742B2/en
Publication of JP2013098481A publication Critical patent/JP2013098481A/ja
Priority to US14/732,179 priority patent/US9401284B2/en
Pending legal-status Critical Current

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Abstract

【課題】良好な放熱性を有し、かつ反りを抑制することが可能な半導体装置を提供すること。
【解決手段】本発明は、ガリウム砒素からなる半導体基板１０と、半導体基板１０上に設けられた能動層１５と、能動層１５と対向する半導体基板１０の下面に設けられた第１Ｎｉ層１２と、第１Ｎｉ層の下面に設けられたＣｕ層１４と、Ｃｕ層１４の下面に設けられた第２Ｎｉ層１６と、を具備する半導体装置である。本発明によれば、良好な放熱性を確保し、かつ反りを抑制することが可能な半導体装置を提供することできる。
【選択図】図２

Description

本発明は半導体装置に関する。
ガリウム砒素（ＧａＡｓ）を含む半導体装置は、高周波数増幅用のパワーデバイスとして用いられている。ＧａＡｓからなる基板には、例えばＦＥＴ（Field Effect Transistor：電界効果トランジスタ）等の能動素子、さらには受動素子が形成される。能動素子はその動作により発熱するため、これを放出することが求められる。半導体チップの放熱性を高めるため、ＧａＡｓからなる基板を薄くすることがある。しかし、ＧａＡｓ基板はもろいため、例えば製造工程中のハンドリング等において破損することがある。そこでＰＨＳ（Plated Heat Sink：プレーテッドヒートシンク）により、基板を補強し、かつ放熱性を高めることがある。ＰＨＳには金（Ａｕ）が用いられる。特許文献１には、半導体基板の下面にＡｕからなるＰＨＳを設ける技術が記載されている。
特開平５−１６６８４９号公報
良好な放熱性を確保するためにはＧａＡｓ基板を薄くし、強度を高めるためにはＰＨＳを厚くすることが好ましい。しかし、ＰＨＳが厚いと、半導体チップを実装する際に大きな反りが発生することがある。特にＰＨＳに用いられるＡｕ等の熱膨張係数が大きいため、反りが大きくなる。本願発明は、上記課題に鑑み、良好な放熱性を有し、かつ反りを抑制することが可能な半導体装置を提供することを目的とする。
本発明は、ガリウム砒素からなる基板と、前記基板上に設けられた能動層と、前記能動層と対向する基板の下面に設けられた第１ニッケルメッキ層と、前記第１ニッケル層の下面に設けられた銅メッキ層と、前記銅メッキ層の下面に設けられた第２ニッケルメッキ層と、を具備する半導体装置である。
上記構成において、前記基板の厚さは２０μｍ以上、４０μｍ以下である構成とすることができる。
上記構成において、前記第１ニッケルメッキ層の厚さ、及び前記第２ニッケルメッキ層の厚さは、それぞれ０．５μｍ以上、３μｍ以下である構成とすることができる。
上記構成において、前記基板の表面積が１ｍｍ２未満の場合、前記銅メッキ層の厚さは５μｍ以上８μｍ未満であり、前記基板の表面積が１ｍｍ２以上９ｍｍ２未満の場合、前記銅メッキ層の厚さは８μｍ以上１０μｍ以下であり、前記基板の表面積が９ｍｍ２以上の場合、前記銅メッキ層の厚さは１６μｍ以上２５μｍ以下である構成とすることができる。
上記構成において、前記第２ニッケルメッキ層の下面に設けられた金層を具備する構成とすることができる。
上記構成において、前記金層は前記第１ニッケルメッキ層の側面、前記銅メッキ層の側面、及び前記第２ニッケルメッキ層の側面を覆っている構成とすることができる。
上記構成において、前記第２ニッケルメッキ層は前記第１ニッケルメッキ層の側面及び前記銅メッキ層の側面を覆い、前記金層は前記第２ニッケルメッキ層の側面を覆っている構成とすることができる。
上記構成において、前記半導体装置は、金錫を含む接着部材により、実装基板に固定される構成とすることができる。
上記構成において、前記第２ニッケルメッキ層は、前記銅メッキ層の側面を覆ってなる構成とすることができる。
本発明によれば、良好な放熱性を有し、かつ反りを抑制することが可能な半導体装置を提供することができる。
図１（ａ）から図１（ｃ）は半導体チップの反りを模式的に例示する断面図である。 図２（ａ）は実施例１に係る半導体チップを例示する断面図である。図２（ｂ）は半導体チップの実装例を示す断面図である。 図３（ａ）から図３（ｃ）は実施例１に係る半導体チップの製造方法を例示する断面図である。 図４（ａ）から図４（ｃ）は実施例１に係る半導体チップの製造方法を例示する断面図である。 図５は比較例に係る半導体チップを例示する断面図である。 図６は実験結果を示すグラフである。 図７は実施例２に係る半導体チップを例示する断面図である。 図８（ａ）から図８（ｄ）は実施例２に係る半導体チップの製造方法を例示する断面図である。 図９（ａ）は実施例３に係る半導体チップを例示する断面図である。図９（ｂ）は実施例３の変形例に係る半導体チップを例示する断面図である。 図１０（ａ）から図１０（ｄ）は実施例３に係る半導体チップの製造方法を例示する断面図である。
まず半導体チップにおいて発生する反りについて説明する。図１（ａ）から図１（ｃ）は半導体チップ１００ａの反りを模式的に例示する断面図である。半導体チップ１００ａは簡略化している。
図１（ａ）において、半導体基板１０に反りは発生していない。図１（ｂ）に示すように、例えば半導体基板１０の下面に、例えばＡｕ又はＣｕ等からなるＰＨＳ１１を設け半導体チップ１００ａを形成する。ＰＨＳ１１の内部応力により、半導体チップ１００ａの中央部が浮き上がるような、凸方向の反りが発生する。図１（ｃ）に示すように、半導体チップ１００ａは、例えば金錫（ＡｕＳｎ）等からなるロウ材２０により、Ｃｕ等からなる実装基板に実装される。このとき、ロウ材２０が軟化する２８０℃以上まで加熱する。ＧａＡｓとＰＨＳ１１との熱膨張係数の差が大きいため半導体チップ１００ａに端部が浮き上がるような、凹方向反りが発生する。反り量が大きい場合、半導体チップ１００ａが実装基板から剥離した状態でロウ材２０が硬化し、半導体チップ１００ａが固定される。その結果、半導体チップ１００ａにクラックが生じる。次に、実施例１について説明する。
実施例１は、ニッケル（Ｎｉ）／Ｃｕ／ＮｉからなるＰＨＳを用いることにより実装前の凸方向の反りを大きくすることで、実装後の凹方向の反りを低減する例である。図２（ａ）は実施例１に係る半導体チップ１００を例示する断面図である。図２（ａ）及び図２（ｂ）において、ＰＨＳ１１は簡略化し、シードメタルは省略している。
図２（ａ）に示すように、ＧａＡｓからなる半導体基板１０の上面には、ＧａＡｓからなりＦＥＴ等の素子として機能する能動層１５が設けられている。能動層１５と対向する半導体基板１０の下面には、第１Ｎｉ層１２（第１ニッケルメッキ層）が設けられている。第１Ｎｉ層１２の下面にＣｕ層１４（銅メッキ層）が設けられている。Ｃｕ層１４の下面に第２Ｎｉ層１６（第２ニッケルメッキ層）が設けられている。第２Ｎｉ層１６の下面にＡｕ層１８が設けられている。第１Ｎｉ層１２、Ｃｕ層１４、第２Ｎｉ層１６及びＡｕ層１８は、半導体基板１０に形成された素子において発生した熱を放熱するＰＨＳ１１として機能する。第１Ｎｉ層１２は半導体基板１０の下面のＡｕからなるシードメタルに接触し、Ｃｕ層１４は第１Ｎｉ層１２の下面に接触している。第２Ｎｉ層１６はＣｕ層１４の下面に接触し、Ａｕ層１８は第２Ｎｉ層１６の下面に接触している。
半導体基板１０の厚さは例えば２０〜３０μｍである。Ｃｕ層１４の厚さは例えば５〜３０μｍである。第１Ｎｉ層１２及び第２Ｎｉ層１６それぞれの厚さは例えば０．５〜３μｍである。Ａｕ層１８の厚さは例えば０．８〜３μｍである。
図２（ｂ）は半導体チップ１００の実装例を示す断面図である。図２（ｂ）に示すように、半導体チップ１００は、ＰＨＳ１１の下面に設けられたロウ材２０（接着部材）により実装基板２２の上面に搭載されている。実装基板２２の絶縁領域２６上にはリードフレーム２４が設けられている。半導体チップ１００とリードフレーム２４とは、ボンディングワイヤ３０により電気的に接続されている。半導体チップ１００は、例えばセラミック等の絶縁体からなる側壁３２及びキャップ３４により封止されている。ロウ材２０は例えばＡｕＳｎを含む。実装基板２２及びリードフレーム２４は例えばＣｕ等の金属を含む。ボンディングワイヤ３０は例えばアルミニウム（Ａｌ）又はＡｕ等の金属からなる。半導体チップ１００において発生した熱は、ＰＨＳ１１及び実装基板２２を介して放出される。
次に半導体チップ１００の製造方法について説明する。図３（ａ）から図４（ｃ）は実施例１に係る半導体チップ１００の製造方法を例示する断面図である。能動層１５の図示は省略する。
図３（ａ）に示すように、不図示のワックス等により、例えばガラスからなる支持体４０の下面に、ＧａＡｓを含むウェハ４１を貼り付ける。素子が形成された上面が支持体４０の下面に接着する。図３（ｂ）に示すように、ウェハ４１を研磨し、ウェハ４１を薄くする。図３（ｃ）に示すように、例えばエッチング等により、スクライブラインに沿ってウェハ４１の一部を除去し、個片化された半導体基板１０を形成する。
図４（ａ）に示すように、支持体４０の下面、半導体基板１０の下面及び側面に例えばＡｕからなるシードメタル１３を設ける。さらに複数の半導体基板１０の間にレジスト４２を設ける。図４（ｂ）に示すように、電解メッキ法により第１Ｎｉ層１２、Ｃｕ層１４、第２Ｎｉ層１６、及びＡｕ層１８を設ける。シードメタル１３は給電線として機能する。第１Ｎｉ層１２及び第２Ｎｉ層１６の形成には、例えば５５℃の温度において、スルミファン酸Ｎｉメッキ浴を用いる。Ｃｕ層１４の形成には、例えば２５℃の温度、２Ａ／ｄｍ２の電流密度において、硫酸Ｃｕメッキ浴を用いる。Ａｕ層１８は、まず薄いＡｕ層（フラッシュメッキ層）を設けた後、厚いＡｕ層を設けることで形成する。Ａｕ層１８の形成には、例えば５５℃の温度、０．１〜０．５Ａ／ｄｍ２の電流密度において、亜硫酸Ａｕメッキ浴を用いる。図４（ｃ）に示すように、レジスト４２及びシードメタル１３を除去する。これにより、半導体チップ１００が形成される。
電解メッキにより形成されたＮｉは圧縮応力を有する。ＰＨＳ１１において、Ｃｕ層１４はＮｉ層に挟まれている。従って半導体チップ１００は、図１（ｂ）に示した凸方向に大きく反る。反り量Ｈ１は例えば２０〜２５μｍである。半導体チップ１００はロウ材２０により、実装基板２２に実装される。熱膨張係数の差により半導体チップ１００は図１（ｃ）に示したように凹方向に反る。凸方向の反り量が大きいため、凹方向の反りは打ち消される。凹方向の反り量Ｈ２は例えば３０〜５０μｍである。
反り量を検証した実験について説明する。実験では、実施例１と比較例とにおいて、ＰＨＳの厚さを変更し、実装前後における反り量を測定した。比較例について説明する。
図５は比較例に係る半導体チップ１００Ｒを例示する断面図である。図５に示すように、半導体チップ１００Ｒは半導体基板１１０、能動層１１５及びＰＨＳ１１１を備える。半導体基板１１０はＧａＡｓからなり、ＰＨＳ１１１はＡｕからなる。
実施例１及び比較例共に、半導体チップのチップサイズは９．３ｍｍ２、半導体基板の厚さは２８μｍである。チップサイズとは半導体基板の上面の面積（表面積）である。ＰＨＳ１１中の第１Ｎｉ層１２及び第２Ｎｉ層１６それぞれの厚さは１μｍである。Ｃｕ層１４の厚さは５、１０及び２０μｍと変化させた。次に実験結果について説明する。
図６は実験結果を示すグラフである。横軸はＰＨＳ１１を構成するＣｕ層１４の厚さ、又はＰＨＳ１１１の厚さを示す。縦軸は反り量を示す。図１（ｂ）に示した方向の反り量Ｈ１を負の値、図１（ｃ）に示した方向の反り量Ｈ２を正の値としている。黒塗りの印は実施例１における反り量、白抜きの印は比較例における反り量を表す。丸は実装前の反り量、四角は実装後の反り量を表す。三角は実装前後における反りの変化を表す。
図６に示すように、比較例においては、実装前における反り量は−１０〜−５μｍ程度である。実装後における反り量は８０〜９０μｍ程度である。反りの変化量は８５〜１００μｍ程度である。図１（ａ）〜図１（ｃ）において述べたように、実装後の反り量が大きいため、半導体チップの破損、実装の不良が生じる。特にＡｕの強度が小さいため、ＰＨＳ１１１を厚くすることが求められる。ＰＨＳ１１１が厚いほど、反り量は大きくなる。
これに対し、実施例１においては、実装前における反り量は−３０〜−２０μｍ程度である。実装後における反り量は３０〜６０μｍ程度である。変化量は６０〜８０μｍである。このように、実施例１によれば、Ｎｉにより実装前の反り量が大きくなる。このため実装時の凹方向の反りが低減される。またＮｉ及びＣｕはＡｕに比べて強度が大きいため、実施例１におけるＰＨＳ１１は比較例におけるＰＨＳ１１１より薄くすることができる。従って、反りはより小さくなる。この結果、半導体チップの破損が抑制され、かつ半導体チップの実装が良好に行われる。
Ｃｕ層１４は良好な熱伝導性を有する。従って、半導体基板１０からの放熱は効率的に行われる。Ｃｕ層１４の厚さが５〜２０μｍ、第１Ｎｉ層１２及び第２Ｎｉ層１６の厚さが１〜３μｍの場合の、ＰＨＳ１１の熱抵抗は４．０４〜４．５１℃／Ｗである。比較例におけるＰＨＳ１１１の厚さが２８〜４０μｍの場合、熱抵抗は４．４２〜４．６１℃／Ｗである。実施例１によれば、比較例と同程度の放熱性を得ることができる。
既述したように、Ｃｕ及びＮｉの強度はＡｕよりも大きいため、ＰＨＳ１１は薄くすることができる。このため反りの低減、及びコストダウンが可能である。反りを低減するためには、Ｃｕ層１４は薄い方が好ましい。しかしＣｕ層１４が薄いと、強度が低下しハンドリングによる破損が発生することがある。チップサイズが大きいほどクラックが発生しやすい。また図１（ｃ）に示したような半導体チップの剥離も生じやすい。このため、チップサイズが大きい場合、Ｃｕ層１４を厚くすることが好ましい。
反りを低減し、かつ十分な強度が得られるＣｕ層１４の厚さを検証するための実験を行った。サンプルとして図２（ａ）の構成の半導体チップ１００を用いた。チップサイズＳ及びＣｕ層１４の厚さＴを変更し、反り量及び強度を調べ、適切な厚さを検証した。実験の結果を表１に示す。
Figure 2013098481
 表１に示すように、チップサイズＳが１ｍｍ２未満の場合、Ｃｕ層１４の厚さＴは５μｍ以上８μｍ未満が好ましい。チップサイズＳが１ｍｍ２以上９ｍｍ２未満の場合、厚さＴは８μｍ以上１０μｍ以下が好ましい。チップサイズＳが９ｍｍ２以上の場合、厚さＴは１６μｍ以上２５μｍ以下が好ましい。なお、チップサイズＳが１ｍｍ２以上９ｍｍ２未満の場合であっても、厚さＴを１６μｍ以上２５μｍ以下とすることも可能である。
第１Ｎｉ層１２は、Ｃｕの半導体基板１０への拡散を抑制する拡散防止層としても機能する。第２Ｎｉ層１６は、ＣｕのＡｕ層１８への拡散を抑制する拡散防止層としても機能する。第１Ｎｉ層１２及び第２Ｎｉ層１６が薄すぎるとＣｕの拡散の抑制、及び反りの低減が困難になり、また半導体チップ１００の強度が小さくなる。厚すぎると熱抵抗が大きくなる。従って、第１Ｎｉ層１２の厚さは０．５〜３μｍが好ましく、０．６〜２．９μｍ、０．７〜２．８μｍとしてもよい。反りを低減し、かつ強度を高めるためには厚さが０．５μｍ以上であることが好ましい。厚さ１μｍ以上であれば、反り量は大きく変わらない。その一方、厚さ３μｍ以上では、熱抵抗が大きくなる。従って、第１Ｎｉ層１２の厚さは０．５〜３μｍ、特に１〜３μｍが好ましい。第２Ｎｉ層１６の厚さも同様の範囲が好ましい。また第１Ｎｉ層１２と第２Ｎｉ層１６とは異なる厚さを有してもよい。
Ａｕ層１８は、Ｎｉの酸化を抑制する酸化防止層、及びＣｕのロウ材２０への拡散を抑制する拡散防止層として機能する。またＡｕはロウ材２０を形成するＡｕＳｎとの濡れ性が高いため、実装信頼性が向上する。Ｃｕの拡散を抑制し、高い濡れ性を確保するためにはＡｕ層１８は厚いことが好ましい。しかし、厚すぎると反りが大きくなる。従って、Ａｕ層１８の厚さは０．８〜３μｍが好ましく、０．９〜２．９μｍ、１．０〜２．８μｍとしてもよい。
実施例２はＡｕ層１８の構成を変えた例である。図７は実施例２に係る半導体チップ２００を例示する断面図である。図７に示すように、半導体チップ２００におけるＡｕ層１８は、第１Ｎｉ層１２の側面、Ｃｕ層１４の側面及び第２Ｎｉ層１６の側面を覆っている。Ａｕ層１８に保護されるため、第１Ｎｉ層１２、Ｃｕ層１４及び第２Ｎｉ層１６の酸化が抑制される。
半導体チップ２００の製造方法について説明する。図８（ａ）から図８（ｄ）は実施例２に係る半導体チップ２００の製造方法を例示する断面図である。図３（ａ）から図４（ａ）までの工程は実施例２にも共通である。
図８（ａ）に示すように、電解メッキ法により第１Ｎｉ層１２、Ｃｕ層１４及び第２Ｎｉ層１６を設ける。図８（ｂ）に示すように、レジスト４２を除去した後、半導体基板１０間にレジスト４４を設ける。図８（ｃ）に示すように、電解メッキ法により、Ａｕ層１８を設ける。図８（ｄ）に示すように、レジスト４４及びシードメタル１３を除去する。これにより半導体チップ２００が形成される。
実施例３は第２Ｎｉ層１６及びＡｕ層１８の構成を変更した例である。図９（ａ）は実施例３に係る半導体チップ３００を例示する断面図である。図９（ａ）に示すように、半導体チップ３００における第２Ｎｉ層１６は第１Ｎｉ層１２の側面及びＣｕ層１４の側面を覆っている。Ａｕ層１８は第２Ｎｉ層１６の側面を覆っている。第２Ｎｉ層１６及びＡｕ層１８に保護されるため、第１Ｎｉ層１２及びＣｕ層１４の酸化は抑制される。Ａｕ層１８に保護されるため、第２Ｎｉ層１６の酸化も抑制される。図９（ｂ）は実施例３の変形例に係る半導体チップ３１０を例示する断面図である。図９（ｂ）に示すように、Ａｕ層１８を設けない場合でも、第２Ｎｉ層１６がＣｕ層１４の側面及び下面を覆ってもよい。
図１０（ａ）から図１０（ｄ）は実施例３に係る半導体チップ３００の製造方法を例示する断面図である。図３（ａ）から図４（ａ）までの工程は実施例２にも共通である。
図１０（ａ）に示すように、電解メッキ法により、第１Ｎｉ層１２及びＣｕ層１４を設ける。図１０（ｂ）に示すように、レジスト４２を除去した後、レジスト４４を設ける。図１０（ｃ）に示すように、電解メッキ法により第２Ｎｉ層１６及びＡｕ層１８を設ける。図１０（ｄ）に示すように、レジスト４４及びシードメタル１３を除去する。これにより半導体チップ３００が形成される。半導体チップ３１０の製造方法の説明は省略する。
実施例１〜３は、ＦＥＴ以外に、例えばＩＧＢＴ（Insulated Gate Bipolar Transistor：絶縁ゲートバイポーラトランジスタ）、サイリスタ等のパワーデバイスを含む半導体装置に適用することができる。
以上、本発明の実施例について詳述したが、本発明はかかる特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。
１０ 半導体基板
１１ ＰＨＳ
１２ 第１Ｎｉ層
１４ Ｃｕ層
１５ 能動層
１６ 第２Ｎｉ層
１８ Ａｕ層
２０ ロウ材
２２ 実装基板
１００、２００、３００、３１０ 半導体チップ

Claims (9)

  1. ガリウム砒素からなる基板と、
    前記基板上に設けられた能動層と、
    前記能動層と対向する基板の下面に設けられた第１ニッケルメッキ層と、
    前記第１ニッケル層の下面に設けられた銅メッキ層と、
    前記銅メッキ層の下面に設けられた第２ニッケルメッキ層と、を具備することを特徴とする半導体装置。
  2. 前記基板の厚さは２０μｍ以上、４０μｍ以下であることを特徴とする請求項１記載の半導体装置。
  3. 前記第１ニッケルメッキ層の厚さ、及び前記第２ニッケルメッキ層の厚さは、それぞれ０．５μｍ以上、３μｍ以下であることを特徴とする請求項１又は２記載の半導体装置。
  4. 前記基板の表面積が１ｍｍ２未満の場合、前記銅メッキ層の厚さは５μｍ以上８μｍ未満であり、前記基板の表面積が１ｍｍ２以上９ｍｍ２未満の場合、前記銅メッキ層の厚さは８μｍ以上１０μｍ以下であり、前記基板の表面積が９ｍｍ２以上の場合、前記銅メッキ層の厚さは１６μｍ以上２５μｍ以下であることを特徴とする請求項１から３いずれか一項記載の半導体装置。
  5. 前記第２ニッケルメッキ層の下面に設けられた金層を具備することを特徴とする請求項１から４いずれか一項記載の半導体装置。
  6. 前記金層は前記第１ニッケルメッキ層の側面、前記銅メッキ層の側面、及び前記第２ニッケルメッキ層の側面を覆っていることを特徴とする請求項５記載の半導体装置。
  7. 前記第２ニッケルメッキ層は前記第１ニッケルメッキ層の側面及び前記銅メッキ層の側面を覆い、
    前記金層は前記第２ニッケルメッキ層の側面を覆っていることを特徴とする請求項５記載の半導体装置。
  8. 前記半導体装置は、金錫を含む接着部材により、実装基板に固定されることを特徴とする請求項１から７いずれか一項記載の半導体装置。
  9. 前記第２ニッケルメッキ層は、前記銅メッキ層の側面を覆ってなることを特徴とする請求項１から４いずれか一項記載の半導体装置。
JP2011242437A 2011-11-04 2011-11-04 半導体装置 Pending JP2013098481A (ja)

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US10002821B1 (en) 2017-09-29 2018-06-19 Infineon Technologies Ag Semiconductor chip package comprising semiconductor chip and leadframe disposed between two substrates
CN108682641B (zh) * 2018-05-28 2020-10-23 焓创制冷技术(苏州)有限公司 晶体管和散热片自动组装设备

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JPH05166849A (ja) 1991-12-17 1993-07-02 Toshiba Corp 半導体素子
JP2000332100A (ja) * 1999-05-18 2000-11-30 Mitsubishi Electric Corp 半導体装置の製造方法および半導体装置
US6870243B2 (en) * 2002-11-27 2005-03-22 Freescale Semiconductor, Inc. Thin GaAs die with copper back-metal structure
JP5530128B2 (ja) * 2009-07-31 2014-06-25 株式会社小糸製作所 蛍光体および発光装置
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JP5583985B2 (ja) * 2010-02-19 2014-09-03 住友電気工業株式会社 金属積層構造体
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