CN104733418A - 管芯基板组装及其方法 - Google Patents

管芯基板组装及其方法 Download PDF

Info

Publication number
CN104733418A
CN104733418A CN201410806694.8A CN201410806694A CN104733418A CN 104733418 A CN104733418 A CN 104733418A CN 201410806694 A CN201410806694 A CN 201410806694A CN 104733418 A CN104733418 A CN 104733418A
Authority
CN
China
Prior art keywords
sublayer
substrate
tube core
interface layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410806694.8A
Other languages
English (en)
Inventor
约翰内斯·威尔赫尔姆斯·范里克瓦塞尔
埃米尔·德·布鲁因
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of CN104733418A publication Critical patent/CN104733418A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0382—Applying permanent coating, e.g. in-situ coating
    • H01L2224/03825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0382—Applying permanent coating, e.g. in-situ coating
    • H01L2224/03826—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/27444—Manufacturing methods by blanket deposition of the material of the layer connector in gaseous form
    • H01L2224/2745—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2746—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2746—Plating
    • H01L2224/27464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29084—Four-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32501—Material at the bonding interface
    • H01L2224/32502—Material at the bonding interface comprising an eutectic alloy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83205—Ultrasonic bonding
    • H01L2224/83207—Thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Die Bonding (AREA)
  • Laminated Bodies (AREA)

Abstract

一种管芯，包括半导体材料本体，所述本体被配置为接收焊料层用于芯片键合所述管芯到基板，其中管芯包括在本体的表面上的接口层用于接收焊料层，接口层具有多个不同金属的子层。

Description

管芯基板组装及其方法
技术领域
本发明涉及一种将管芯附接到基板上的方法。它还涉及一种用于附接到基板的半导体管芯。另外，本发明涉及一种封装，该封装包括设置在基板上的管芯。
背景技术
封装组装包括将半导体管芯键合到基板上的步骤，基板典型的是金属。基板典型地包括CPC或铜钨合金(CuW)。CPC基板包括三明治结构。顶层和底层由铜构成，并且在顶层和底层之间的层包括铜钼(CuMo)合金。管芯本身是典型地通过共熔的金硅(AuSi)芯片键合工艺键合到基板。这种工艺涉及在键合在一起之前应用相对厚的金层在基板上(大约1000-2500nm)和在管芯上(典型地是300nm)。目前的芯片键合工艺是昂贵的，通常是因为所使用的材料，并且是慢的和需要高工艺温度。
发明内容
根据本申请的一个方面，提供一种管芯，包括半导体材料的本体，所述本体被配置为接收焊料层用于将所述管芯芯片键合到基板，其中管芯包括在本体的表面上的接口层用于接收焊料层，接口层具有多个不同金属的子层。
在半导体本体和焊料层之间提供多个不同金属(包括合金)的子层的接口层是有利的，可以改善芯片键合工艺(固定管芯到基板)的可靠性和所产生的管芯-基板的结构的和热的完整性。
接口层可能在管芯的大部分表面上延伸，焊料层施加到该部分上。接口层可能在焊料层和半导体本体之间的由管芯上的焊料层覆盖的大体上整个区域或至少90％的区域上延伸。例如，锯切巷可能没有背面金属。
子层可能包含以下一个或更多：金的子层，银的子层；镍的子层；另外的金的子层。接口层可能包含与本体相邻的金的子层和用于接收焊料层的金的子层，和至少一个在金的子层之间的除了金以外的金属的另外的子层。至少一个的另外的子层可能包括银层。至少一个的另外的子层可能包括镍层。至少一个的另外的子层可能包括镍的子层和银的子层。
在其它的实施例中，接口层可能包含一个或更多的钛(Ti)的子层，铜(Cu)和镍钒(NiV)或镍(Ni)的子层。
在其它实施例中，接口层可能包括金的第一子层和银的第二子层(AuAg)。可选地，接口层可能包含金的第一子层，镍的第二子层和银的第三子层。这样的接口层可能使用镍(Ni)层电镀。
接口层包含施加到本体的金的第一子层，银的第二子层，镍的第三子层镍和用于接收焊料层的金的第四子层。子层的这种特定顺序的布置被认为是有利的。
第一子层和第四子层可能比第二和第三子层厚。另外，接口层的外面的子层可能比接口层的里面的子层厚。
管芯可能包括固定到接口层上的焊料层，和焊料层可能比接口层至少厚两倍。进一步的，焊料层可能比接口层厚至少三倍，四倍或五倍。接口层可能约1000nm厚。
子层的厚度可能在50nm和500nm之间并且优选地在100nm和400nm之间。每个子层的厚度可能具有下限为25nm，50nm，75nm，100nm，125nm，150nm，175nm或者200nm并且与以下上限厚度中的任何一个相结合：200nm，250nm，300nm，350nm，400nm，450nm和500nm。每个子层具有的金属纯度可能至少是80％或者，优选地，至少95％或者至少99％。优选地，各子层包含基本上100％纯度的金属。
焊料层可能包括金的合金。可选的，它可能包含铜的合金，锡的合金或者铜锡(CuSn)合金。焊料层可能包含金和锡(AuSn)的合金。这是有利的因为接口层的存在可能使AuSn键合更加可靠。焊料层的含金量按重量计算可能是在75％和85％之间。
管芯可能通过焊料层键合到铜基板。铜基板的使用可能是比CuW或者CPC基板更节约成本的，由于接口层的使用，管芯和基板之间的键合可能是可靠的。因此，基板可能不包含或者只包含钼的痕量。
基板，可能是铜的，可能大体上是均匀的。因此，不同铜合金的层可能不是必要的。相反，基板可能是由合金的铜块形成的。铜可能具有的纯度按重量计算至少是95％，99％或者99.8％。基板可能至少半硬化回火，这可能具有有利的硬度和刚度性质。
铜基板可能用外层电镀。外层可能包含氧化物防护层。外层可能包含镍-钯-金(NiPdAu)合金。外层可能包含合金，该合金包含金、钯和镍的一个或更多。外面的电镀层的厚度可能小于0.6μm。对于NiPdAu外层，镍的厚度可能大体上是0.5μm，钯的厚度可能大体上是0.05μm和金的厚度可能大体上是0.010μm。可以理解的是这些只是示例的厚度。
基板可能包括布置在基板和管芯的焊料层之间的衬垫层。因此，衬垫层适于接收管芯和通过焊料层邻接到管芯。
封装可能包含RF功率封装。管芯-基板组装特别适用于RF功率应用，其中在管芯和基板之间需要高完整性和高热导率键合，可能包含散热器。
根据本申请的第二方面，提供形成用于键合到基板的管芯的方法，包括以下步骤：
接收半导体本体；
施加接口层到所述半导体本体，所述接口层包括多个不同金属的子层。
方法可能还包括施加金锡合金的焊料层到所述接口层。
施加接口层的步骤可能包含溅射，蒸发电镀或者电镀所述层。
施加接口层的步骤可能包含施加金的第一子层到半导体本体。特别地，金的第一子层可能与半导体本体(例如硅)接合，这提供良好的低欧姆接触。另外，施加接口层的步骤可能还包括施加银的第二子层到第一子层，施加镍的第三子层到第二子层，和施加金的第四子层到第三子层。
方法可能包括以下步骤，接收铜的基板；和使用焊料层将管芯键合到基板。键合可能包含热压缩键合。可选的，可以使用热声波键合。
方法可能包括接收铜的基板，铜的基板具有在其上的金的衬垫层用于接收管芯的焊料层。方法可能包括将衬垫层施加到基板的步骤。方法可能包括用外层电镀基板的步骤，可能包含合金，合金包括金，钯和镍的一个或更多。
附图说明
通过示例的方式根据以下附图描述本发明优选的实施例：
图1示出了管芯和基板的一个实施例；
图2示出了接口层的更详细的视图；
图3示出了具有焊料层的接口层的更详细的视图；
图4-6示出了根据实施例的形成管芯，基板和封装的方法的流程图。
具体实施方式
图1示出了半导体管芯1和金属基板2用于使用焊料来芯片键合在一起。本发明在RF功率封装的制造中具有特别的应用。基板，又名端板(header)或凸缘(flange)，可能包括散热器用于RF功率封装。在保证所产生的封装的可靠性的同时降低制造成本是重要的。需要管理半导体管芯1和基板2之间的相对热膨胀，当保证管芯1和基板2之间的高导热性时，通常使用昂贵的材料。本实施例提供节约成本的管芯和基板和制造工艺，同时维持管芯和基板之间的高完整性的焊料互联以保证结构可靠性和有效的热转移。
管芯1包括半导体材料的本体3，半导体材料例如是硅。本体3包括焊料层4，焊料层4包括合金，该合金包含金用于将管芯芯片键合到基板2。在一些例子中，焊料层可能不包含金。管芯1包括在本体3和焊料层4之间的接口层5，接口层5具有多个不同金属的子层。
半导体本体3由硅片组成，可能在上面会形成电子元件。本体3可能包含单晶硅或者砷化镓或者氮化镓半导体材料或者任何其它半导体材料。本体3的背面具有接口层5施加在其上。
接口层包含多个子层和可能包含与本体3相邻的金子层和与焊料层相邻的金子层和在金子层之间的至少一个除金以外的金属子层。
图2更详细地示出了管芯1和接口层5。在本实施例中，接口层5包括4个子层，5a，5b，5c和5d。第一子层5a直接施加到本体3并且包括金与硅的合金层以获得低欧姆接触。第一子层的厚度可能在100nm和500nm之间并且优选地在200nm和400nm之间。第一子层的厚度可能具有下限为50nm，100nm，150nm，200nm，250nm，300nm并且与以下上限厚度中的任何一个相结合：300nm，350nm，400nm，450nm，500nm。在本实施例中第一子层具有厚度约为300nm。金层的纯度可能至少是80％或者，优选地，至少95％或者至少99％或者基本是纯金。
在本实施例中，第二子层5b包括包括施加到第一子层5a上的银层。第二子层5b可能比第一子层5a更薄。第二子层的厚度可能在50nm和400nm之间并且优选地在100nm和300nm之间。第二子层的厚度可能具有下限为25nm，50nm，75nm，100nm，125nm，150nm，175nm或者200nm并且与以下上限厚度中的任何一个相结合：200nm，250nm，300nm，350nm，400nm。在本实施例中第二子层具有厚度约为200nm。银层的纯度可能至少是80％或者，优选地，至少95％或者至少99％或者基本是纯银。
在本实施例中，第三子层5c包括包括施加到第二子层5b上的镍层。第三子层5c能比第二子层5b更厚和/或可能比第一子层5a更薄。第三子层的厚度可能在100nm和450nm之间并且优选地在200nm和350nm之间。第三子层5c厚度可能具有下限为75nm，100nm，125nm，150nm，175nm，200nm，225nm或者250nm并且与以下上限厚度中的任何一个相结合：250nm，300nm，350nm，400nm，450nm。在本实施例中第三子层具有厚度约为250nm。镍层的纯度可能至少是80％或者，优选地，至少95％或者至少99％或者基本是纯镍。
在本实施例中，在焊料层前的第四及最后的子层5d括包括施加到第三子层5c的金层。第四子层的厚度可能在100nm和500nm之间并且优选地在200nm和400nm之间。第四子层的厚度可能具有下限为50nm，100nm，150nm，200nm，250nm，300nm并且与以下上限厚度中的任何一个相结合：300nm，350nm，400nm，450nm，500nm。在本实施例中第四子层具有厚度约为300nm。金层的纯度可能至少是80％或者，优选地，至少95％或者至少99％或者基本是纯金。
图3示出了管芯1，具有施加到接口层并且特别地，施加到接口层5的最后的子层(在本实施例中是第四子层)的焊料层4。焊料层包括用于焊接工艺中将管芯1键合到基板2的层。在本实施例中，焊料层包括，金和锡的合金(AuSn)。在合金中金和锡的比例可能基本上是80/20wt％。焊料层可能包含其它物质的痕量。已经发现接口层的使用可能改善硅片/焊料键合的完整性。
焊料层的厚度可能至少为2000nm或者至少3000nm或者至少4000nm。然而，可以理解的是，根据特定的实施例焊料层可能具有任何厚度。在本实施例中，焊料层的厚度根据管芯尺寸大体上在5000nm和7000nm之间。因此，焊料层4的厚度可能是接口层5的厚度的至少三至四倍。
再一次参考图1，基板2包括铜的均匀区6。铜的纯度可能至少是80％，90％，95％或者99.8％。基板区6包括至少/基本上是占基板重量的90％。基板是均匀的，它不包含不同金属或者合金的子层。这是有利的，因为铜基板比其它典型的基板，例如CPC或者CuW更加节约成本。然而，基板可能包含衬垫7。衬垫7包含银层，该银层至少在基板2的部分表面上。衬垫7可能具有与连接到基板2的管芯1的尺寸大体上相应的尺寸。银衬垫7可能具有纯度至少为90％，95％或者98％或者可能基本上是纯银。基板区6以及可能还有衬垫7可能与外层8镀在一起。
外层8包含基本上纯的镍，钯和金(NiPdAu)的子层。从而，管芯1焊接到外层8上。
图4，5和6示出了根据实施例的用于制造RF功率封装的各种制造和组装工艺的流程图。
图4示出了在步骤40接收半导体材料本体3。步骤41示出了将接口层5施加到本体3的背面。接口层5的子层的施加可能通过溅射，蒸发或者电镀或者任何其它薄膜沉积技术。因此，步骤41包括施加金的第一子层5a到本体3；施加银的第二子层5b到第一子层5a；施加镍的第三子层5c到第二子层5b；以及施加金的第四子层5d到第三子层5c。可能这样施加具有接口层5的本体3但是该方法可能还包括，如步骤42所示，施加金锡合金焊料层4到接口层5。
图5示出了用于形成键合到管芯1的基板2的制造工艺。该工艺包括步骤60，在步骤50中接收包括基板的主体的铜基板区6。步骤51示出了施加金的衬垫层7在基板的芯片键合表面的至少一部分上用于接收管芯1。可能通过任何适当的薄膜沉积技术施加衬垫层。步骤52示出了使用外层8将区域6和衬垫层电镀。
图6示出了芯片键合的步骤，其中管芯包括接口层5，焊料层4键合到包括衬垫7和外部电镀层8的基板2。步骤60示出了接收基板1。步骤61示出了接收管芯，管芯包括具有接口层5和焊料层4的本体3。步骤62示出了芯片键合步骤，其中焊料层是热压缩键合或者热超声键合的以将管芯1焊接到基板2的衬垫层7。
在其它实施例中，接口层可能包括金的第一子层和银的第二子层(AuAg)。可选地，接口层可能包含金的第一子层，镍的第二子层和银的第三子层。可能使用镍(Ni)层电镀这样的接口层。

Claims (15)

1.一种管芯，其特征在于，包括半导体材料的本体，所述本体被配置为接收焊料层用于芯片键合所述管芯到基板，其中管芯包括在本体的表面上的接口层用于接收焊料层，接口层具有多个不同金属的子层。
2.根据权利要求1所述的管芯，其特征在于，子层包括以下中的一个或者多个：金的子层，银的子层；镍的子层；另外的金的子层。
3.根据权利要求1或权利要求2所述的管芯，其特征在于，接口层包括施加到本体上的金的第一子层，银的第二子层，镍的第三子层和毗邻焊料层的金的第四子层。
4.据权利要求3所述的管芯，其特征在于，第一子层和第四子层比第二子层和第三子层厚。
5.根据权利要求4所述的管芯，其特征在于，管芯包括固定到接口层的焊料层，焊料层比接口层至少厚两倍。
6.根据前述任一权利要求所述的管芯，其特征在于，所述焊料层包含金和锡的合金。
7.一种封装，其特征在于，包括铜的基板，具有通过焊料层键合在基板上的根据权利要求1至5中任一项的管芯。
8.根据权利要求7所述的封装，其特征在于，基板是均匀的。
9.根据权利要求7或8所述的封装，其特征在于，基板包括布置在基板和管芯的焊料层之间的金的衬垫层。
10.根据权利要求6至8中任一项所述的封装，其特征在于，封装包括RF功率封装。
11.一种形成用于键合到基板的管芯的方法，其特征在于，包括以下步骤：
接收半导体本体；
施加接口层到所述半导体本体，所述接口层包括多个不同金属的子层；
施加焊料层到所述接口层。
12.根据权利要求11所述的方法，其特征在于，施加接口层的步骤包括溅射，蒸发电镀或者电镀所述接口层。
13.根据权利要求12所述的方法，其特征在于，施加接口层的步骤包括：施加金的第一子层到半导体本体，施加银的第二子层到第一子层，施加镍的第三子层到第二子层和施加金的第四子层到第三子层。
14.根据权利要求11至14任意一项所述的方法，其特征在于，包括以下步骤：
接收铜的基板；和
使用焊料层将管芯键合到基板。
15.根据权利要求13或权利要求14所述的方法，其特征在于，所述方法包括接收铜的基板，铜的基板上具有衬垫层用于接收管芯的焊料层。
CN201410806694.8A 2013-12-24 2014-12-22 管芯基板组装及其方法 Pending CN104733418A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP13199587.0 2013-12-24
EP13199587.0A EP2889903A1 (en) 2013-12-24 2013-12-24 Die with a multilayer backside interface layer for solder bonding to a substrate and corresponding manufacturing method

Publications (1)

Publication Number Publication Date
CN104733418A true CN104733418A (zh) 2015-06-24

Family

ID=49943142

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410806694.8A Pending CN104733418A (zh) 2013-12-24 2014-12-22 管芯基板组装及其方法

Country Status (3)

Country Link
US (1) US9324674B2 (zh)
EP (1) EP2889903A1 (zh)
CN (1) CN104733418A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783785A (zh) * 2015-11-20 2017-05-31 赛米控电子股份有限公司 功率半导体芯片以及用于制造功率半导体芯片的方法
CN110957293A (zh) * 2018-09-26 2020-04-03 恩智浦美国有限公司 封装管芯连接系统和其对应的方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150201515A1 (en) * 2014-01-13 2015-07-16 Rf Micro Devices, Inc. Surface finish for conductive features on substrates
US9893027B2 (en) * 2016-04-07 2018-02-13 Nxp Usa, Inc. Pre-plated substrate for die attachment
TWI638433B (zh) * 2017-10-24 2018-10-11 英屬維京群島商艾格生科技股份有限公司 元件次黏著載具及其製造方法
NL2021598B1 (en) 2018-09-10 2020-05-01 Ampleon Netherlands Bv Seed layer for electroplating eutectic AuSn solder

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60110127A (ja) * 1983-11-18 1985-06-15 Sony Corp 積層金属電極を有する半導体装置
US20060108672A1 (en) * 2004-11-24 2006-05-25 Brennan John M Die bonded device and method for transistor packages
WO2008050251A1 (en) * 2006-10-23 2008-05-02 Nxp B.V. Backside wafer contact structure and method of forming the same
CN102956514A (zh) * 2011-08-10 2013-03-06 株式会社东芝 半导体装置的制造方法及半导体装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2757805B2 (ja) * 1995-01-27 1998-05-25 日本電気株式会社 半導体装置
EP1737029A4 (en) * 2004-03-24 2011-03-30 Tokuyama Corp SUBSTRATE FOR COMPONENTS BONDING AND MANUFACTURING METHOD THEREFOR
TWI462236B (zh) * 2005-03-18 2014-11-21 同和電子科技有限公司 副載置片及其製造方法
US7999369B2 (en) * 2006-08-29 2011-08-16 Denso Corporation Power electronic package having two substrates with multiple semiconductor chips and electronic components
EP2089901A4 (en) * 2006-11-09 2011-05-18 Interplex Qlp Inc MICROCIRCUIT HOUSING HAVING A DUCTILE LAYER
US8310043B2 (en) * 2008-03-25 2012-11-13 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader with ESD protection layer
US8399969B2 (en) * 2010-07-27 2013-03-19 Visera Technologies Company Limited Chip package and fabricating method thereof
EP2453474A1 (en) * 2010-11-10 2012-05-16 Nxp B.V. Semiconductor device packaging method and semiconductor device package
JP2012178438A (ja) * 2011-02-25 2012-09-13 Omron Corp ｎ型半導体基板にダイボンド用金属層が設けられた構造体およびその製造方法
EP2693465A1 (en) 2012-07-31 2014-02-05 Nxp B.V. Electronic device and method of manufacturing such device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60110127A (ja) * 1983-11-18 1985-06-15 Sony Corp 積層金属電極を有する半導体装置
US20060108672A1 (en) * 2004-11-24 2006-05-25 Brennan John M Die bonded device and method for transistor packages
WO2008050251A1 (en) * 2006-10-23 2008-05-02 Nxp B.V. Backside wafer contact structure and method of forming the same
CN102956514A (zh) * 2011-08-10 2013-03-06 株式会社东芝 半导体装置的制造方法及半导体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783785A (zh) * 2015-11-20 2017-05-31 赛米控电子股份有限公司 功率半导体芯片以及用于制造功率半导体芯片的方法
CN110957293A (zh) * 2018-09-26 2020-04-03 恩智浦美国有限公司 封装管芯连接系统和其对应的方法

Also Published As

Publication number Publication date
EP2889903A1 (en) 2015-07-01
US9324674B2 (en) 2016-04-26
US20150179599A1 (en) 2015-06-25

Similar Documents

Publication Publication Date Title
CN104733418A (zh) 管芯基板组装及其方法
US8963321B2 (en) Semiconductor device including cladded base plate
US8519532B2 (en) Semiconductor device including cladded base plate
US8823175B2 (en) Reliable area joints for power semiconductors
US11842975B2 (en) Electronic device with multi-layer contact and system
US8021929B2 (en) Apparatus and method configured to lower thermal stresses
US20070025684A1 (en) Connection Structure Semiconductor Chip and Electronic Component Including the Connection Structure and Methods for Producing the Connection Structure
JP3661695B2 (ja) 半導体装置
WO2008060447A2 (en) Microcircuit package having ductile layer
JP2014053384A (ja) 半導体装置およびその製造方法
US8283756B2 (en) Electronic component with buffer layer
EP2693465A1 (en) Electronic device and method of manufacturing such device
US20100148326A1 (en) Thermally Enhanced Electronic Package
US11682644B2 (en) Semiconductor device with a heterogeneous solder joint and method for fabricating the same
US8866298B2 (en) Bonded system with coated copper conductor
WO2008050251A1 (en) Backside wafer contact structure and method of forming the same
JPH08115928A (ja) 半導体装置およびその製造方法
US20150076699A1 (en) Semiconductor device and method for manufacturing the same
US8354754B2 (en) Layered chip for use in soldering
JPH03218031A (ja) 半導体集積回路装置およびそれに用いられるプリフォーム接合材
US8188592B2 (en) Apparatus and method configured to lower thermal stresses
TWI381562B (zh) 低溫形成反射性發光二極體固晶接合結構之方法
JP2017069366A (ja) 半導体装置およびその製造方法
JPH0645485A (ja) 高放熱性集積回路パッケージ
CN104465578A (zh) 半导体装置及半导体模块

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20151029

Address after: Holland Ian Deho Finn

Applicant after: NXP BV

Address before: Holland Ian Deho Finn

Applicant before: NXP BV

CB02 Change of applicant information

Address after: Nijmegen

Applicant after: AMPLEON NETHERLANDS B.V.

Address before: Holland Ian Deho Finn

Applicant before: NXP BV

COR Change of bibliographic data
RJ01 Rejection of invention patent application after publication

Application publication date: 20150624

RJ01 Rejection of invention patent application after publication