JP6041469B2 - 高融点半田層の形成方法 - Google Patents
高融点半田層の形成方法 Download PDFInfo
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- JP6041469B2 JP6041469B2 JP2011172912A JP2011172912A JP6041469B2 JP 6041469 B2 JP6041469 B2 JP 6041469B2 JP 2011172912 A JP2011172912 A JP 2011172912A JP 2011172912 A JP2011172912 A JP 2011172912A JP 6041469 B2 JP6041469 B2 JP 6041469B2
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- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Description
(積層化高融点半田層の構成)
実施の形態に係る積層化高融点半田層5の模式的断面構造は、図1(a)に示すように表され、低融点メタル薄膜層81と、低融点メタル薄膜層81の表面および裏面に配置された高融点メタル薄膜層82とを有する3層構造を複数積層化した積層化構造80の模式的断面構造は、図1(b)に示すように表される。
実施の形態に係る積層化高融点半田層を適用した半導体装置10の模式的断面構造は、図2に示すように、絶縁基板6と、絶縁基板6上に配置された第1伝導用メタル層7aと、第1伝導用メタル層7a上に配置された第1積層化高融点半田層5aと、第1積層化高融点半田層5a上に配置された半導体デバイス4とを備える。
実施の形態に係る積層化高融点半田層の形成方法の一工程を説明する模式的断面構造は、図5〜図9に示すように表される。また、実施の形態に係る積層化高融点半田層に適用されるAg−Sn系半田の2元状態図は、図10に示すように表される。
実施の形態に係る積層化高融点半田層を適用した半導体装置10の製造方法の一工程として、基板取り付け工程を説明する模式的断面構造は、図11に示すように表される。また、図11の基板取り付け工程の詳細を説明するための加熱温度Tと時間tとの関係は、図12に示すように表される。
実施の形態に係る積層化高融点半田層を適用した半導体装置10の製造方法の一工程として、半導体デバイス取り付け工程を説明する模式的断面構造は、図13に示すように表される。また、図13の半導体デバイス取り付け工程の詳細を説明するための加熱温度Tと時間tとの関係は、図14に示すように表される。
図15は、従来の半導体デバイス(Pb−Sn系低融点半田層を使用)と本実施の形態に係る半導体デバイス(Ag−Sn系高融点半田層を使用)における、ダイ剥離強度の温度変化を示す。従来の半導体デバイスは高温で著しくダイ剥離強度が低下するが、本実施の形態に係る半導体デバイスでは、大幅な低下は見られなかった。
実施の形態に係る積層化高融点半田層を適用して形成した半導体装置10のモジュール構成例は、図16に示すように、ベースプレート8と、第2積層化高融点半田層5bおよび第2伝導用メタル層7bを介してベースプレート8上に配置された絶縁基板6と、第1伝導用メタル層7aおよび第1積層化高融点半田層5aを介して絶縁基板6上に配置された半導体デバイス4とを備える。
実施の形態に係る積層化高融点半田層を適用した変形例に係る半導体装置10は、図17(a)および図17(b)に示すように、半導体デバイス4と、半導体デバイス4上に配置された第3積層化高融点半田層5cと、第3積層化高融点半田層5c上に配置されたソース側パッド電極40と、第3積層化高融点半田層5cが配置された表面とは反対側の半導体デバイス4の裏面に配置された第4積層化高融点半田層5dと、半導体デバイス4が配置された第4積層化高融点半田層5dの表面とは反対側の第4積層化高融点半田層5dの裏面に配置されたドレイン側パッド電極42とを備える。図17に示される半導体装置10においては、3個の半導体デバイス4が並列接続されている。
上記のように、実施の形態および変形例によって記載したが、この開示の一部をなす論述および図面は例示的なものであり、この発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例および運用技術が明らかとなろう。
1b,12b…第2高融点メタル層
2a…第1低融点密着層
2b…第2低融点密着層
2c…第3低融点密着層
2d…第4低融点密着層
3,14…低融点メタル層
4…半導体デバイス
5…積層化高融点半田層
5a…第1積層化高融点半田層
5b…第2積層化高融点半田層
5c…第3積層化高融点半田層
5d…第4積層化高融点半田層
6…絶縁基板
7a…第1伝導用メタル層
7b…第2伝導用メタル層
8…ベースプレート
9a,9b…ボンディングワイヤ
10…半導体装置
18…おもり
20…リフローマシン
22a…第1バリアメタル層
22b…第2バリアメタル層
24…ドレイン領域
26…高抵抗基板
28…ベース領域
30…ソース/ドレイン領域
32…ゲート絶縁膜
34…ソース電極
36…ドレイン電極
38…ゲート電極
40…ドレイン側パッド電極
42…ソース側パッド電極
44…枠体
46…封止板
50…ゲートドライブ部
52…パワーモジュール部
54…3相モータ部
60…半導体パワーモジュール
62…TLP接合部
80…積層化構造
81…高融点メタル薄膜層
82…低融点メタル薄膜層
S…ソースリード
G…ゲートリード
D…ドレインリード
Claims (3)
- Sn層若しくはSn−Ag共晶半田層によって形成される低融点メタル薄膜層と、前記低融点メタル薄膜層の表面および裏面に配置されたAg層によって形成される高融点メタル薄膜層とを有する3層構造を複数積層化した積層化構造と、前記積層化構造の表面に配置されたAg層によって形成される第1高融点メタル層と、前記積層化構造の裏面に配置されたAg層若しくはNi層によって形成される第2高融点メタル層とを平坦化する工程と、
前記低融点メタル薄膜層の融解温度以上に加熱して、前記積層化構造を前記第1高融点メタル層および前記第2高融点メタル層の合金に拡散させて、液相拡散接合を形成する工程と、
前記液相拡散接合を冷却する工程と
を有し、前記低融点メタル薄膜層の融解温度以上の融解温度を有することを特徴とする高融点半田層の形成方法。 - 前記Sn−Ag共晶半田層は、96.5±1質量%のSnと3.5±1質量%のAgの組成からなることを特徴とする請求項1に記載の高融点半田層の形成方法。
- 前記液相拡散接合を形成する温度は、250℃以上350℃以下であることを特徴とする請求項1に記載の高融点半田層の形成方法。
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EP12173116.0A EP2541593B1 (en) | 2011-06-30 | 2012-06-22 | Laminated high melting point soldering layer |
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