JP5772050B2 - 半導体装置及びその製造方法、電源装置 - Google Patents
半導体装置及びその製造方法、電源装置 Download PDFInfo
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- JP5772050B2 JP5772050B2 JP2011036254A JP2011036254A JP5772050B2 JP 5772050 B2 JP5772050 B2 JP 5772050B2 JP 2011036254 A JP2011036254 A JP 2011036254A JP 2011036254 A JP2011036254 A JP 2011036254A JP 5772050 B2 JP5772050 B2 JP 5772050B2
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Description
近年、GaN系の化合物半導体であるAlGaN/GaNのヘテロ接合を利用し、GaNを電子走行層とし、AlGaNを電子供給層として用い、これらを積層したHEMT構造を備えるGaN−HEMTの開発が活発である。
なお、半導体チップを支持板上に実装する技術としては、例えばはんだや接着剤などのダイボンディング剤を用いて、半導体チップの裏面を支持板の半導体チップ実装領域に接合することで、半導体チップを支持板上に実装する技術がある。
つまり、まず、半導体チップ実装領域及び半導体チップの裏面の一方の全面にダイボンディング剤を塗布する。なお、半導体チップ実装領域及び半導体チップの裏面の他方にはダイボンディング剤を塗布しない。次に、半導体チップを、支持板の半導体チップ実装領域に位置合わせする。そして、これらを加熱して、半導体チップの裏面を、ダイボンディング剤によって、支持板の半導体チップ実装領域に接合する。
本半導体装置の製造方法は、支持板の半導体チップ実装領域及び半導体チップの裏面の一方に、第1金属を含む層及び第2金属を含む層の一方を形成し、半導体チップ実装領域及び半導体チップの裏面の他方の、第1金属を含む層及び第2金属を含む層の一方が形成された領域の一部に相当する領域に、第1金属を含む層及び第2金属を含む層の他方を形成し、半導体チップ実装領域に半導体チップを位置合わせし、第1金属及び第2金属を含む合金を含む層を形成して、半導体チップを半導体チップ実装領域に接合することを要件とする。
[第1実施形態]
まず、第1実施形態にかかる半導体装置及びその製造方法について、図1〜図4を参照しながら説明する。
以下、ディスクリートパッケージを例に挙げて説明する。
ここでは、半導体チップ1の裏面(基板裏面)が固定されたステージ2は、ドレインリード23と電気的に接続されている。なお、これに限られるものではなく、ステージ2がソースリード22と電気的に接続されるようにしても良い。
まず、キャリア走行層及びキャリア供給層を含む窒化物半導体積層構造を備える半導体チップ1を、リードフレームのステージ2上に固定する。
次に、例えばAlワイヤなどのワイヤ4を用いたボンディングによって、半導体チップ1のゲートパッド24をゲートリード21に接続し、ドレインパッド26をドレインリード23に接続し、ソースパッド25をソースリード22に接続する。
その後、リードフレームから切り離して、半導体装置(ディスクリートパッケージ)が得られる。
ところで、リードフレームのステージ2上に半導体チップ1を固定するのに、例えばはんだや熱伝導性樹脂からなる接着剤などのダイアタッチ剤を用いると、加熱接合する際に、半導体チップ1が移動や回転等の位置ずれを生じてしまう(図11参照)。
つまり、まず、図1(A)に示すように、リードフレームのステージ2上の半導体チップ実装領域2Aの全面に、例えば電解めっき法によって、第1金属を含む層としてAg層5を形成する。このAg層5の厚さは、例えば約5μmである。ここで、Ag層5を形成する領域は、例えばレジストパターニングによって規定すれば良い。なお、半導体チップ実装領域2Aの大きさ(面積)は、半導体チップ1の裏面の大きさ(面積)と同一である。また、半導体チップ実装領域2Aを、リードフレーム実装エリアともいう。また、ここでは、リードフレームは、例えばCuに微量のZr(ジルコニウム)を添加した材料からなる。
つまり、ステージ2の半導体チップ実装領域2Aに半導体チップ1を位置合わせし、半導体チップ実装領域2Aの全面に形成されたAg層5に、半導体チップ1の裏面の一部に形成されたSn層6が接するように、半導体チップ1を半導体チップ実装領域2Aにフェイスアップで搭載する。そして、約221℃以上の温度、最大約240℃の温度で加熱することで、Sn−Ag合金層9を形成し、このSn−Ag合金層9によって半導体チップ1をステージ2の半導体チップ実装領域2Aに接合する。これにより、半導体チップ1が、リードフレームのステージ2上に固定される。つまり、Sn−Ag合金層9による金属接合によって、半導体チップ1がリードフレームのステージ2上の半導体チップ実装領域2Aに確実に固着される。ここで、半導体チップ1とリードフレームのステージ2とを接合する接合材料としてのSn−Ag合金は、低い熱抵抗値を有するため、高い放熱効果が得られることになる。
つまり、本実施形態にかかる半導体装置は、図1(D)に示すように、ステージ2と、ステージ2上に設けられた半導体チップ1と、ステージ2と半導体チップ1との間に設けられたAg層5及びSn−Ag合金層9からなる接合層3とを備える。ここでは、Ag層5は、ステージ2に接合されている一方、半導体チップ1には接しているだけである。また、Sn−Ag合金層9は、ステージ2と半導体チップ1とを接合している。また、Sn−Ag合金層9は、ステージ2の半導体チップ実装領域2Aの中央部に設けられており、Ag層5は、ステージ2の半導体チップ実装領域2Aの中央部の外側に設けられている。
つまり、リードフレームのステージ2上に半導体チップ1を実装する際に、位置ずれ等の接合不良を生じることなく、半導体チップ1をリードフレームのステージ2上の所定の位置に高精度に固定(搭載)することができる。また、リードフレームのステージ2と半導体チップ1とを接合する接合層3に含まれるSn−Ag合金の融点は約221℃であり、半導体チップ1の動作時の温度よりも高くなるため、半導体チップ動作時の発熱に伴う位置ずれ等も防止することできる。さらに、本実施形態では、半導体チップ実装領域2Aの中央部にSn−Ag合金層9が形成されるため、リードフレームのステージ2上の半導体チップ実装領域2Aの周囲の領域にSn−Ag合金層9が染み出すのを抑制することができる。特に、リードフレームのステージ2上の半導体チップ実装領域2Aの周囲の領域にCr層8を形成した場合には、Sn−Ag合金層9が染み出すのを確実に防止することができる。これにより、例えばワイヤボンディングによる接続面(ワイヤボンディング電極部)が汚染されないようにすることができる。この結果、信頼性の高い半導体装置を作製することが可能となり、歩留まりを大幅に向上させることができる。
つまり、第1金属を含む層5は、第1金属として、Ag、Cu、Au、Bi、In、Ni、Pb、Sbのいずれかの金属を含む層であれば良い。また、第1金属を含む層5は、第1金属からなる第1金属層であっても良いし、第1金属と他の金属とを含む層であっても良いし、第1金属と樹脂とを含む層であっても良い。ここで、第1金属と樹脂とを含む層は、例えば第1金属の粉末が添加された樹脂層、即ち、第1金属が混合された熱伝導性樹脂層である。なお、樹脂層を接着剤ともいい、熱伝導性樹脂層を熱伝導性接着剤ともいう。なお、第1金属を含む層5を、第1金属と樹脂とを含む層とする場合、あるいは、第1金属を含む層5を、第1金属とフラックスとを含むペースト(例えばAgペースト)を用いて形成する場合、例えばディスペンス法、スクリーン印刷法などの印刷法などによって形成すれば良い。例えば、上述の実施形態において、第1金属を含む層5として、Ag粉末を添加した樹脂層を形成する場合、例えば、平均粒径約5μmのAg粉末を約50vol%含有するエポキシ系樹脂材料を、厚さ約50μmとなるように形成すれば良い。この場合も、上述の実施形態の場合と同様に、リードフレームのステージ2上に半導体チップ1を実装する際に、半導体チップ1が移動や回転等の位置ずれを生じないようにすることができる。また、このようにして作製した半導体装置における半導体チップ1の動作時の熱抵抗値を測定したところ、約0.5℃/W以下であり、熱伝導性接着剤による接合によって作製した半導体装置と同等の熱抵抗値を示した。このようにして半導体チップ1をリードフレームのステージ2に接合した場合であっても、Ag及び樹脂を含む層5、Sn−Ag合金及び樹脂を含む層9、及び、リードフレームのステージ2を介して、半導体チップ1の発熱を効率良く外部へ放熱させることが可能である。
また、例えば図7(A)に示すように、リードフレームのステージ2上の半導体チップ実装領域2Aの全面に第1金属を含む層(ここではAg層)5を形成し、図7(B)に示すように、半導体チップ1の裏面の一部(外周部)に第2金属を含む層(ここではSn層)6を形成しても良い。そして、図7(C)に示すように、ステージ2の半導体チップ実装領域2A上に半導体チップ1を位置合わせし、図7(D)に示すように、Sn−Ag合金層9を形成して、半導体チップ1をステージ2の半導体チップ実装領域2Aに接合する。これにより、半導体チップ1の裏面の一部(外周部)に形成された第2金属を含む層6及びこれに対向する領域に形成された第1金属を含む層5だけが溶融し、それ以外の領域(外周部の内側の領域)に形成された第1金属を含む層5は溶融せずに固体のままになるため、半導体チップ1に移動や回転等の位置ずれが生じてしまうのを防ぐことができる。特に、このように、半導体チップ1の裏面の外周部に第2金属を含む層6を形成することで、加熱接合時に、半導体チップ実装領域2Aの周囲に第1金属及び第2金属を含む合金を含む層9が染み出すおそれがある。このため、リードフレームのステージ2上の半導体チップ実装領域2Aの周囲の領域に、第1金属及び第2金属の少なくとも一方と反応しない第3金属を含む層(ここではCr層)8を形成するのが好ましい。これにより、Snの溶融時の染み出し、即ち、Sn−Ag合金層9の染み出しを抑制することが可能となる。また、このようにして作製した半導体装置における半導体チップ1の動作時の熱抵抗値を測定したところ、約0.3℃/W以下であり、はんだによる接合によって作製した半導体装置と同等の熱抵抗値を示した。このようにして半導体チップ1をリードフレームのステージ2に接合した場合であっても、Ag層5、Sn−Ag合金層9、及び、リードフレームのステージ2を介して、半導体チップ1の発熱を効率良く外部へ放熱させることが可能である。なお、図7(A)〜図7(D)では、リードフレームのステージ2上の半導体チップ実装領域2Aの周囲の領域にCr層8を形成する場合を例に挙げて示しているが、これに限られるものではなく、Cr層8を形成しなくても良い。
また、例えば、リードフレームのステージ2上の半導体チップ実装領域2Aの全面に第2金属を含む層6を形成し、半導体チップ1の裏面の一部に第1金属を含む層5を形成しても良い。これにより、半導体チップ1の裏面の一部に形成された第1金属を含む層5及びこれに対向する領域に形成された第2金属を含む層6だけが溶融し、それ以外の領域に形成された第2金属を含む層6は溶融せずに固体のままになるため、半導体チップ1に移動や回転等の位置ずれが生じてしまうのを防ぐことができる。特に、半導体チップ1の裏面の外周部に第1金属を含む層5を形成する場合、半導体チップ実装領域2Aの周囲に第1金属及び第2金属を含む合金を含む層9が染み出すおそれがある。このため、リードフレームのステージ2上の半導体チップ実装領域2Aの周囲の領域に、第1金属及び第2金属の少なくとも一方と反応しない第3金属を含む層8を形成するのが好ましい。これにより、Snの溶融時の染み出しを抑制することが可能となる。
また、上述の実施形態では、リードフレームのステージ2上の半導体チップ実装領域2Aの全面に第1金属を含む層(Ag層)5を形成し、半導体チップ1の裏面の一部(中央部の一箇所)に第2金属を含む層(Sn層)6を形成しているため、製造された半導体装置は、ステージ2と半導体チップ1との間に設けられた第1金属を含む層(Ag層)5及び第1金属及び第2金属を含む合金を含む層(Sn−Ag合金層;第1金属を合金化した合金を含む層)9とを備えるものとなるが、これに限られるものではない。
[第2実施形態]
次に、第2実施形態にかかる電源装置について、図10を参照しながら説明する。
以下、サーバに用いられる電源装置に備えられるPFC(power factor correction)回路に、上述の半導体パッケージに含まれるGaN−HEMTを用いる場合を例に挙げて説明する。
ここでは、本PFC回路は、回路基板上に、ダイオードブリッジ30、チョークコイル31、第1コンデンサ32、上述の半導体パッケージに含まれるGaN−HEMT33、ダイオード34、及び、第2コンデンサ35が実装されて構成されている。
なお、ここでは、上述の半導体装置(GaN−HEMT又はGaN−HEMTを含む半導体パッケージ)を、サーバに用いられる電源装置に備えられるPFC回路に用いる場合を例に挙げて説明しているが、これに限られるものではない。例えば、上述の半導体装置(GaN−HEMT又はGaN−HEMTを含む半導体パッケージ)を、サーバ以外のコンピュータなどの電子機器(電子装置)に用いても良い。また、上述の半導体装置(半導体パッケージ)を、電源装置に備えられる他の回路(例えばDC−DCコンバータなど)に用いても良い。
[その他]
なお、本発明は、上述した各実施形態及び変形例に記載した構成に限定されるものではなく、本発明の趣旨を逸脱しない範囲で種々変形することが可能である。
以下、上述の各実施形態及び変形例に関し、更に、付記を開示する。
(付記1)
支持板の半導体チップ実装領域及び半導体チップの裏面の一方に、第1金属を含む層及び第2金属を含む層の一方を形成し、
前記半導体チップ実装領域及び前記半導体チップの裏面の他方の、前記第1金属を含む層及び前記第2金属を含む層の一方が形成された領域の一部に相当する領域に、前記第1金属を含む層及び前記第2金属を含む層の他方を形成し、
前記半導体チップ実装領域に前記半導体チップを位置合わせし、前記第1金属及び前記第2金属を含む合金を含む層を形成して、前記半導体チップを前記半導体チップ実装領域に接合することを特徴とする半導体装置の製造方法。
前記第1金属を含む層及び前記第2金属を含む層の一方を、前記半導体チップ実装領域及び前記半導体チップの裏面の一方の全面に形成し、
前記第1金属を含む層及び前記第2金属を含む層の他方を、前記半導体チップ実装領域及び前記半導体チップの裏面の他方の一部に形成することを特徴とする、付記1に記載の半導体装置の製造方法。
前記第1金属を含む層及び前記第2金属を含む層の他方を、前記半導体チップ実装領域及び前記半導体チップの裏面の他方の中央部に形成することを特徴とする、付記1又は2に記載の半導体装置の製造方法。
(付記4)
前記第1金属を含む層及び前記第2金属を含む層の他方を、前記半導体チップ実装領域及び前記半導体チップの裏面の他方の複数の箇所に形成することを特徴とする、付記1又は2に記載の半導体装置の製造方法。
前記第1金属を含む層及び前記第2金属を含む層の他方を、前記半導体チップ実装領域及び前記半導体チップの裏面の他方の外周部に形成することを特徴とする、付記1又は2に記載の半導体装置の製造方法。
(付記6)
前記半導体チップを前記半導体チップ実装領域に接合する前に、前記支持板上の前記半導体チップ実装領域の周囲の領域に、前記第1金属及び前記第2金属の少なくとも一方と反応しない第3金属を含む層を形成することを特徴とする、付記1〜5のいずれか1項に記載の半導体装置の製造方法。
前記第1金属は、Ag、Cu、Au、Bi、In、Ni、Pb、Sbのいずれかの金属であり、
前記第2金属は、前記第1金属と反応して合金を形成しうる金属であることを特徴とする、付記1〜6のいずれか1項に記載の半導体装置の製造方法。
前記第2金属は、Sn、Bi、In、Zn、Ag、Sb、Cu、Ni、Pbのいずれかの金属であることを特徴とする、付記7に記載の半導体装置の製造方法。
(付記9)
前記第1金属は、Ag、Cu、Au、Bi、In、Ni、Pb、Sbのいずれかの金属であり、
前記第2金属は、前記第1金属と反応して合金を形成しうる金属であって、Sn、Bi、In、Zn、Ag、Sb、Cu、Ni、Pbのいずれかの金属であり、
前記第3金属は、前記第2金属と反応しない金属であって、Cr、Fe、Ti、Zrのいずれかの金属であることを特徴とする、付記6に記載の半導体装置の製造方法。
前記半導体チップを前記半導体チップ実装領域に接合する前に、前記第1金属を含む層及び前記第2金属を含む層の一方の表面に突起部を形成することを特徴とする、付記1〜9のいずれか1項に記載の半導体装置の製造方法。
(付記11)
前記半導体チップの裏面に前記第1金属を含む層又は前記第2金属を含む層を形成する前に、前記半導体チップの裏面に密着層を形成することを特徴とする、付記1〜10のいずれか1項に記載の半導体装置の製造方法。
支持板と、
前記支持板上に設けられた半導体チップと、
前記支持板と前記半導体チップとの間に設けられ、前記支持板及び前記半導体チップのいずれか一方に接合された金属を含む層と、
前記支持板と前記半導体チップとの間に設けられ、前記支持板と前記半導体チップとを接合している、前記金属を合金化した合金を含む層とを備えることを特徴とする半導体装置。
前記合金を含む層は、前記支持板の半導体チップ実装領域の中央部に設けられており、
前記金属を含む層は、前記支持板の前記半導体チップ実装領域の前記中央部の外側に設けられていることを特徴とする、付記12に記載の半導体装置。
(付記14)
前記合金を含む層は、前記支持板の半導体チップ実装領域の複数の箇所に設けられており、
前記金属を含む層は、前記支持板の前記半導体チップ実装領域の前記複数の箇所に設けられた前記合金を含む層の周囲に設けられていることを特徴とする、付記12に記載の半導体装置。
前記合金を含む層は、前記支持板の半導体チップ実装領域の外周部に設けられており、
前記金属を含む層は、前記支持板の前記半導体チップ実装領域の前記外周部の内側に設けられていることを特徴とする、付記12に記載の半導体装置。
(付記16)
前記半導体チップ実装領域の周囲の領域に設けられ、前記合金を含む層に含まれている金属と反応しない他の金属を含む層を備えることを特徴とする、付記12〜15のいずれか1項に記載の半導体装置。
前記金属を含む層は、表面に突起部を備えることを特徴とする、付記12〜16のいずれか1項に記載の半導体装置。
(付記18)
前記金属を含む層及び前記合金を含む層は、さらに樹脂を含むことを特徴とする、付記12〜17のいずれか1項に記載の半導体装置。
前記半導体チップと前記合金を含む層との間に密着層を備えることを特徴とする、付記12〜18のいずれか1項に記載の半導体装置。
(付記20)
支持板と、
前記支持板上に設けられた半導体チップと、
前記支持板と前記半導体チップとの間に設けられ、前記支持板及び前記半導体チップのいずれか一方に接合された金属を含む層と、
前記支持板と前記半導体チップとの間に設けられ、前記支持板と前記半導体チップとを接合している、前記金属を合金化した合金を含む層とを備える半導体装置を備えることを特徴とする電源装置。
2 ステージ
2A 半導体チップ実装領域
3 接合層
4 ワイヤ
5 Ag層(第1金属を含む層)
6 Sn層(第2金属を含む層)
7 封止樹脂(モールド樹脂)
8 Cr層(第3金属を含む層)
9 Sn−Ag合金層(第1金属及び第2金属を含む合金を含む層)
10 突起部
11 回路基板(パッケージ基板)
12 BGAボール
21 ゲートリード
22 ソースリード
23 ドレインリード
24 ゲートパッド
25 ソースパッド
26 ドレインパッド
30 ダイオードブリッジ
31 チョークコイル
32 第1コンデンサ
33 GaN−HEMT
34 ダイオード
35 第2コンデンサ
Claims (4)
- 支持板の半導体チップ実装領域及び半導体チップの裏面の一方に、第1金属を含む層及び第2金属を含む層の一方を形成し、
前記半導体チップ実装領域及び前記半導体チップの裏面の他方の、前記第1金属を含む層及び前記第2金属を含む層の一方が形成された領域の一部に相当する領域に、前記第1金属を含む層及び前記第2金属を含む層の他方を形成し、
前記半導体チップ実装領域に前記半導体チップを位置合わせし、前記第1金属及び前記第2金属を含む合金を含む層を形成して、前記半導体チップを前記半導体チップ実装領域に接合することを特徴とする半導体装置の製造方法。 - 前記第1金属を含む層及び前記第2金属を含む層の一方を、前記半導体チップ実装領域及び前記半導体チップの裏面の一方の全面に形成し、
前記第1金属を含む層及び前記第2金属を含む層の他方を、前記半導体チップ実装領域及び前記半導体チップの裏面の他方の一部に形成することを特徴とする、請求項1に記載の半導体装置の製造方法。 - 支持板と、
前記支持板上に設けられた半導体チップと、
前記支持板と前記半導体チップとの間に設けられ、前記支持板及び前記半導体チップのいずれか一方に接合された金属を含む層と、
前記支持板と前記半導体チップとの間に設けられ、前記支持板と前記半導体チップとを接合している、前記金属を合金化した合金を含む層とを備え、
前記金属を含む層は、前記合金を含む層の側方の周囲に設けられていることを特徴とする半導体装置。 - 支持板と、
前記支持板上に設けられた半導体チップと、
前記支持板と前記半導体チップとの間に設けられ、前記支持板及び前記半導体チップのいずれか一方に接合された金属を含む層と、
前記支持板と前記半導体チップとの間に設けられ、前記支持板と前記半導体チップとを接合している、前記金属を合金化した合金を含む層とを備え、
前記金属を含む層は、前記合金を含む層の側方の周囲に設けられている半導体装置を備えることを特徴とする電源装置。
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