CN102646609B - 半导体器件、半导体器件的制造方法以及电源器件 - Google Patents

半导体器件、半导体器件的制造方法以及电源器件 Download PDF

Info

Publication number
CN102646609B
CN102646609B CN201210031859.XA CN201210031859A CN102646609B CN 102646609 B CN102646609 B CN 102646609B CN 201210031859 A CN201210031859 A CN 201210031859A CN 102646609 B CN102646609 B CN 102646609B
Authority
CN
China
Prior art keywords
layer
semiconductor chip
metal
semiconductor device
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201210031859.XA
Other languages
English (en)
Other versions
CN102646609A (zh
Inventor
清水浩三
冈本圭史郎
今泉延弘
今田忠纮
渡部庆二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CN102646609A publication Critical patent/CN102646609A/zh
Application granted granted Critical
Publication of CN102646609B publication Critical patent/CN102646609B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05169—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/27444—Manufacturing methods by blanket deposition of the material of the layer connector in gaseous form
    • H01L2224/2745—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2746—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29016—Shape in side view
    • H01L2224/29018—Shape in side view comprising protrusions or indentations
    • H01L2224/29019—Shape in side view comprising protrusions or indentations at the bonding interface of the layer connector, i.e. on the surface of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2902—Disposition
    • H01L2224/29034—Disposition the layer connector covering only portions of the surface to be connected
    • H01L2224/29036—Disposition the layer connector covering only portions of the surface to be connected covering only the central area of the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/2912—Antimony [Sb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29499—Shape or distribution of the fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32501—Material at the bonding interface
    • H01L2224/32502—Material at the bonding interface comprising an eutectic alloy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32505—Material outside the bonding interface, e.g. in the bulk of the layer connector
    • H01L2224/32506—Material outside the bonding interface, e.g. in the bulk of the layer connector comprising an eutectic alloy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48744—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明涉及半导体器件、半导体器件的制造方法、以及电源器件。一种制造半导体器件的方法，包括：在支撑板的半导体芯片安装区域和半导体芯片的背表面中的一个上形成具有第一金属的层和具有第二金属的层中的一个；在半导体芯片安装区域和半导体芯片的背表面中的另一个的与其中具有第一金属的层和具有第二金属的层中的一个的区域的一部分对应的区域上，形成具有第一金属的层和具有第二金属的层中的另一个；以及在半导体芯片安装区域中定位半导体芯片之后，形成包括具有第一金属和第二金属的合金的层以将半导体芯片与半导体芯片安装区域接合。

Description

半导体器件、半导体器件的制造方法以及电源器件
技术领域
本文所述实施方案涉及半导体器件、半导体器件的制造方法、以及电源器件。
背景技术
存在具有包括载流子传输层和载流子供给层的半导体层叠结构的常规高电子迁移率晶体管(HEMT)。近年来，GaN-HEMT已经得到积极地开发。通过使用AIGaN/GaN的异质结作为GaN基化合物半导体，形成GaN-HEMT的HEMT结构，其中层叠作为电子传输层的GaN和作为电子供给层的AIGaN。
GaN为具有高击穿场强的材料，其带隙为约3.4eV，其大于Si的带隙(约1.1eV)和GaAs的带隙(约1.4eV)。GaN为具有高的饱和电子速度的材料。因此，预期GaN用于实现用于可以利用高电压操作并可获得高输出的电源的半导体器件。预期GaN-HEMT用作开关元件，具有用于提供于电子装置中的电源器件的高的效果。
具有上述GaN-HEMT的半导体芯片安装于电路基板的支撑板、引线框的载台等上。存在通过使用晶粒接合剂例如钎料和粘合剂经由半导体芯片的背表面与支撑板的半导体芯片安装区域的接合来用于将半导体芯片安装于支撑板上的技术。例如，日本专利公开号2006-156437、日本专利公开号6-132442和日本专利公开号58-207645作为相关技术被公开。
发明内容
考虑到上述内容，本实施方案的一个目的是提供一种半导体器件及其制造方法以及电源，用于抑制在半导体芯片安装于基板的载台上时由于移动或旋转导致的位移。
根据本发明的一个方面，半导体器件的制造包括：在支撑板的半导体芯片安装区域和半导体芯片的背表面中的一个上形成具有第一金属的层和具有第二金属的层中的一个；在半导体芯片安装区域和半导体芯片的背表面中的另一个的、与其中具有第一金属的层和具有第二金属的层中的一个的区域的一部分对应的区域上，形成具有第一金属的层和具有第二金属的层中的另一个；以及在半导体芯片安装区域中定位半导体芯片之后，形成包括具有第一金属和第二金属的合金的层以将半导体芯片与半导体芯片安装区域接合。
附图说明
图1A和图1B为示出根据第一实施方案的半导体器件和半导体器件制造方法的一个实例的平面图；
图1C和图1D为示出根据第一实施方案的半导体器件和该半导体器件的制造方法的一个实例的截面图；
图2为示出根据第一实施方案的半导体器件的一个实例的平面图；
图3为示出根据第一实施方案的半导体器件的另一实例的截面图；
图4为示出使用晶粒接合剂的常规情形的问题的截面图；
图5A～5C为示出根据第一实施方案的半导体器件和半导体器件制造方法的一个变化实例的图，图5A为平面图，图5B和5C为截面图；
图6A～6D为示出半导体器件的另一变化实例和半导体器件的制造方法的图，图6A和6B为平面图，图6C和6D为截面图；
图7A～7D为示出半导体器件的另一变化实例和半导体器件的制造方法的图，图7A和7B为平面图，图7C和7D为截面图；
图8A～8D为示出半导体器件的另一变化实例和半导体器件的制造方法的图，图8A和8B为平面图，图8C和8D为截面图；
图9为示出根据第一实施方案的变化方案的半导体器件的一个实例的截面图；
图10为示出包括于根据第二实施方案的电源器件中的PFC电路的一个实例的图；和
图11为示出本发明问题的平面图。
具体实施方式
以下将参考附图描述根据实施方案的半导体器件、半导体器件的制造方法以及电源器件。参考图1～4，将描述根据第一实施方案的半导体器件和半导体器件的制造方法。
根据第一实施方案的半导体器件为使用例如氮化物基化合物半导体(例如GaN基化合物半导体)的化合物半导体器件，其为利用树脂封装具有载流子传输层和载流子供给层的氮化物基半导体层叠结构的半导体芯片的半导体封装件。半导体芯片也称为通过高电流操作的半导体元件或功率半导体元件。以下描述中给出分立封装件作为一个实例。
如图2和3所示，半导体器件包括：半导体芯片1、其上安装半导体芯片1的载台2、接合层3、栅极引线21、源极引线22、漏极引线23、接合线(在此情形下，为Al线)4和模制化合物7。模制化合物7也称为模制树脂。载台2为例如引线框的载台。载台2也称为支撑板。
利用Al线4将安装于载台2上的半导体芯片1的栅极垫24、源极垫25和漏极垫26分别与栅极引线21、源极引线22和漏极引线23耦接，并利用模制化合物7封装。在此情形下，将与半导体芯片1的背表面(基板的背表面)固定的载台2与漏极引线23电耦接。第一实施方案不限于此情形。载台2可与源极引线22电耦接。
在这种情况下，半导体芯片1包括GaN-HEMT，其具有包括GaN电子传输层和AIGaN电子供给层的GaN基半导体层叠结构。半导体芯片为例如用于用作设置于电子器件或电源器件中的开关元件的电源的GaN-HEMT芯片。GaN基HEMT芯片1包括：在GaN基半导体层叠结构的上部中的栅电极、源电极和漏电极。GaN基HEMT芯片1包括配线层，其包括绝缘膜和在上述电极的上部中的配线。栅极垫24、源极垫25和漏极垫26暴露在GaN基HEMT芯片1的表面上。GaN-HEMT也称为GaN基HEMT。GaN-HEMT芯片也称为GaN基HEMT芯片。
以下将描述根据第一实施方案的半导体器件(分立封装件)的制造方法。半导体器件的制造方法也称为半导体芯片的安装方法。包括载流子传输层和载流子供给层的氮化物半导体层叠结构的半导体芯片1固定在引线框的载台2上。例如，通过利用接合线4例如Al线接合，半导体芯片1的栅极垫24与栅极引线21耦接，漏极垫26与漏极引线23耦接，源极垫25与源极引线22耦接。
例如通过传递模塑方法利用树脂封装半导体芯片1。即，使用于封装半导体芯片1的模制化合物7成形。从引线框移除半导体芯片1，获得半导体器件(分立封装件)。如图11所示，例如，如果晶粒粘合剂例如包括钎料或导热树脂的粘合剂将半导体芯片1固定在引线框的载台2上，则可产生半导体芯片1的位置偏移例如移动或旋转。
根据第一实施方案，以如下方式将半导体芯片1固定在引线框的载台2上。如图1A所示，在引线框的载台2上的半导体芯片安装区域2A的整个表面上，通过例如电解电镀方法形成Ag层5作为具有第一金属的层。例如，Ag层5的厚度为约5μm。其中形成Ag层5的区域可例如通过抗蚀剂图案化来指定。半导体芯片安装区域2A的尺寸(面积)与半导体芯片1的背表面的尺寸(面积)几乎相等。半导体芯片安装区域2A也称为引线框安装区域。在这种情况下，例如，通过向Cu添加少量Zr(锆)获得的材料可用作引线框。
在此阶段中，如图5A所示，通过例如电解电镀方法，在引线框的载台2上的半导体芯片安装区域2A周围的区域中，可形成与Sn不相容的Cr层8作为具有第三金属的层，其与第一金属和第二金属中的至少之一不具有反应性。例如，Cr层8的厚度可为约2μm。在这种情况下，其中形成Cr层8的区域可通过例如抗蚀剂图案化来指定。这防止Sn层6在下述熔融操作中渗出。
如图1B所示，通过例如电解电镀方法在半导体芯片1的背表面的一部分中形成Sn层6作为包括第二金属的层。例如，Sn层6的厚度为约2.6μm。在这种情况下，Sn层6在半导体芯片1的背表面的中心部分中形成。以此方式，通过在半导体芯片1的背表面的中心部分中形成Sn层6，防止Sn层6在下述热接合中在半导体芯片安装区域2A周围的区域中渗出。其中形成Sn层6的区域可通过例如抗蚀剂图案化来指定。Sn层6在半导体芯片1的背表面的一部分中形成。如下所述，通过利用Ag层5合金化，Sn层6具有用于在半导体芯片安装区域2A中定位半导体芯片1的功能。结果，Sn层也称为定位金属层或定位凸点。
在这种情况下，优选对半导体芯片1的背表面例如支撑GaN基半导体层叠结构的SiC基板的背表面实施Ti/Ni/Au的金属化加工。即，优选在通过例如溅射方法、镀覆方法(例如电解电镀法和化学镀法)等形成其中依次层叠Ti、Ni和Au的粘合层之后，在粘合层上形成Sn层6。例如，形成粘合层的Ti层、Ni层和Au层的厚度分别为约100nm、200nm和100nm。其中形成粘合层的区域可通过例如抗蚀剂图案化来指定。除了其中依次层叠Ti、Ni和Au的粘合层之外，其中Ti、Pt和Au依次层叠的粘合层可用作用于将Sn层6粘合于半导体芯片1的背表面的粘合层。即，优选可对半导体芯片1的背表面例如支撑GaN基半导体层叠结构的SiC基板的背表面实施Ti/Pt/Au的金属化加工。
如图1C所示，在载台2上的半导体芯片安装区域2A上定位半导体芯片1。如图1D所示，形成Sn-Ag合金层9作为包括具有Ag和Sn的合金的层，并且使半导体芯片1与载台2上的半导体芯片安装区域2A接合。即，在载台2上的半导体芯片安装区域2A中定位半导体芯片1，并且将半导体芯片1面朝上地安装于半导体芯片安装区域2A中，使得在半导体芯片安装区域2A的整个表面上形成的Ag层5与在半导体芯片1的背表面的一部分中形成的Sn层6接触。通过利用约221℃以上到最高240℃的温度的热接合，形成Sn-Ag合金层9，并且通过Sn-Ag合金层9将半导体芯片1与载台2上的半导体芯片安装区域2A接合。结果，半导体芯片1固定于引线框的载台2上。即，通过利用Sn-Ag合金层9的金属接合，半导体芯片1与引线框的载台2上的半导体芯片安装区域2A确保地接合。在这种情况下，作为用于将半导体芯片1与引线框的载台2接合的接合材料的Sn-Ag合金，因为Sn-Ag合金具有低的热阻，所以可获得高的散热效果。
如图5A所示，如果在引线框的载台2上的半导体芯片安装区域2A周围的区域中形成Cr层8，则半导体芯片1定位在载台2上的半导体芯片安装区域2A上，如图5B所示。如图5C所示，形成Sn-Ag合金层9，并且半导体芯片1与载台2上的半导体芯片安装区域2A接合。
如上所述，如果温度为约221℃以上同时Ag层5与Sn层6接触，则Ag与Sn具有共晶反应。因此，其中Ag层5与Sn层6接触的部分熔融并合金化，使得形成Sn-Ag合金层9。约221℃的温度为Sn-Ag合金的熔点，其是Sn和Ag的二元相图中的固相线温度。在这种情况下，因为Sn层6仅仅在半导体芯片1的背表面的部分(在这种情况下，中心部分)中简单地提供。因此，该部分中的Ag层5和Sn层6熔融并合金化，使得形成Sn-Ag合金层9。在这种情况下，Ag与Sn具有共晶反应。根据Sn和Ag的二元相图，在固相线温度221℃下产生液相，在等于或低于221℃的温度下产生Ag3Sn和Sn的固相。根据Sn和Ag的二元相图，Ag3Sn的溶解度极限表现出约73.2wt％的Ag和约26.8wt％的Sn。因此，如果Ag扩散熔融入Sn中进行直至约73.2wt％以上的Ag，则Ag3Sn处于固相中。因此，Ag扩散熔融入Sn中没有更进一步地进行。即，Ag层5和Sn层6不熔融或扩散。结果，如果Ag层和Sn层的厚度比例为73.2∶26.8，Ag层5和层6在其中形成Sn层6的区域中、即在半导体芯片1的背表面的部分(在这种情况下，中心部分)中熔融和合金化，使得形成Sn-Ag合金层9。此外，即使Ag层5和Sn层6的厚度比例不是73.2∶26.8，如果Ag层5的厚度增加，Ag层5和Sn层6在小于其中形成Sn层6的区域的区域中、即在半导体芯片1的背表面的部分(在这种情况下，中心部分)中熔融和合金化，使得形成Sn-Ag合金层9。因此，在除了与其中形成Sn层6的区域相对的区域之外的区域中形成的Ag层5熔融，使得Sn-Ag合金层9不渗出。即，在半导体芯片1的背表面的部分(在这种情况下，中心部分)中形成的Sn层6和在与该部分相对的区域中形成的Ag层5熔融。在除了上述区域之外的区域(在这种情况下，在中心部分之外的区域)中形成的Ag层5不熔融而仍为固体。
以下将描述半导体器件的结构，即以上述方式形成的半导体芯片的安装结构。即，如图1D所示，根据第一实施方案的半导体器件包括：载台2、设置在载台2上的半导体芯片1、以及设置于载台2和半导体芯片1之间的包括Ag层5和Sn-Ag合金层9的接合层3。在这种情况下，虽然Ag层5与载台2接合，但是Ag层5仅与半导体芯片1接触。使用Sn-Ag合金层9将载台2与半导体芯片1接合。Sn-Ag合金层9设置于载台2上的半导体芯片安装区域2A的中心部分中，Ag层5设置在载台2上的半导体芯片安装区域2A的中心部分外。
如图5A所示，如果在引线框的载台2上的半导体芯片安装区域2A周围的区域中形成Cr层8，则在半导体芯片安装区域2A周围的区域具有与包含于Sn-Ag合金层9中的Sn不具有反应性的Cr层8，如图5C所示。在半导体芯片1和Sn-Ag合金层9之间可提供粘合层。
根据第一实施方案的半导体器件和半导体器件的制造方法，优势在于：在半导体芯片1安装在引线框的载台2上时，不产生半导体芯片1的位置偏移例如移动或旋转。即，在半导体芯片1安装于引线框的载台2上时，半导体芯片1可以高精度地固定(安装)于引线框的载台2上的指定位置上，而没有接合缺陷例如位置偏移。用于将载台2与半导体芯片1的引线框接合的接合层3中包含的Sn-Ag合金的熔点为约221℃，其高于半导体芯片1的操作中的温度。这防止半导体芯片1由于在操作中生热而导致的位置偏移。此外，根据第一实施方案，因为在半导体芯片安装区域2A的中心部分中形成Sn-Ag合金层9，所以防止Sn-Ag合金层9在引线框的载台2上的半导体芯片安装区域2A周围的区域中渗出。特别地，如果在引线框的载台2上的半导体芯片安装区域2A周围的区域中形成Cr层8，则确保地防止Sn-Ag合金层9渗出。例如，这防止通过引线接合形成的接合表面(引线接合电极)受到污染。结果，制造具有高可靠性的半导体器件，制造良品率得到大大改善。
如图4所示，如果半导体芯片1与其中在半导体芯片1的背表面和半导体芯片安装区域2A中之一的整个表面上施加钎料、Ag浆料或晶粒接合剂103例如导热剂的载台2上的半导体芯片安装区域2A接合，则难以以高可靠性制造半导体器件。即，因为树脂硬化时产生半导体芯片1的位置偏移例如移动或旋转或者通过引线接合形成的接合线4的接合表面被钎料渗出或扩散所污染，所以难以制造具有高可靠性的半导体器件。
以上述方式形成的半导体器件的半导体芯片的操作中的热阻等于或低于约0.3℃/W。该热阻与通过钎料接合形成的半导体器件的热阻几乎相等。即使半导体芯片1与引线框的载台2以上述方式接合，半导体芯片1的热也可通过Ag层5或者Sn-Ag合金层9以及引线框的载台2有效地散至外部。例如，在用于包括于具有高电压和高功率的电子器件中的电源的半导体器件中，通过半导体芯片1产生的热量增加，使得控制电路的可靠性可受到影响。然而，因为半导体芯片1的热以上述方式有效地散至外部，所以可实现具有高可靠性的半导体器件。
根据上述第一实施方案，形成Ag层5作为具有第一金属的层，形成Sn层6作为具有第二金属的层，形成Sn-Ag合金层9作为具有通过使第一金属和第二金属合金化获得的合金的层。然而，具有第一金属的层、具有第二金属的层、以及包括具有第一金属和第二金属的合金的层不限于上述层。即，具有第一金属的层5可包括Ag、Cu、Au、Bi、In、Ni、Pb和Sb中的一种作为第一金属。具有第一金属的层5可为具有第一金属的第一金属层。具有第一金属的层5可为具有第一金属和另一金属的层。具有第一金属的层5可为具有第一金属和树脂的层。在这种情况下，具有第一金属和树脂的层为添加有第一金属粉末的树脂层，例如即与第一金属混合的导热树脂层。树脂层也称为粘合剂。导热树脂层也称为导热粘合剂。如果具有第一金属的层5为具有第一金属和树脂的层或者如果具有第一金属的层5通过使用包括第一金属和熔剂的浆料(例如Ag浆料)形成，则可使用印刷方法例如点胶(dispense)法、丝网印刷法等。根据上述实施方案，为形成添加有Ag粉末的树脂层作为具有第一金属的层5，例如，形成包括约50体积％的平均粒径为约5μm的Ag粉环氧基树脂材料为具有约50μm的厚度。如上述第一实施方案一样，在半导体芯片1安装于引线框的载台2上时，可防止半导体芯片1的位置偏移例如移动或旋转。以上述方式形成的半导体器件中的半导体芯片的操作中的热阻等于或低于约0.5℃/W。该热阻等于在通过与导热剂接合制造的半导体器件操作中的热阻。即使半导体芯片1与引线框的载台2以上述方式接合，半导体芯片1的热也可通过具有Ag和树脂的层5、具有Sn-Ag合金层和树脂的层9、以及引线框的载台2有效地散至外部。
具有第二金属的层6可包括与第一金属Ag、Cu、Au、Bi、In、Ni、Pb和Sb中的一种具有反应性的金属作为第二金属，即熔融和合金化的金属。例如，具有第二金属的层6可包括Sn、Bi、In、Zn、Ag、Sb、Cu、Ni和Pb中的一种作为第二金属。即，具有第二金属的层6可为具有Sn的Sn层。具有第二金属的层6可包括Sn作为主要组分、以及Bi、In、Zn、Ag、Sb、Cu、Ni和Pb中的至少一种。具有第二金属的层6可包括Bi、In、Zn、Ag、Sb、Cu、Ni和Pb中的至少一种。具有第二金属的层6可为具有第二金属的第二金属层。具有第二金属的层6可包括第二金属和另一金属。具有第二金属的层6可包括第二金属和树脂。在这种情况下，具有第二金属和树脂的层为例如添加有第二金属粉末的树脂层，即与第二金属混合的导热树脂层。如果具有第二金属的层6包括第二金属和树脂或者如果具有第二金属的层通过使用包括第二金属和熔剂的浆料(例如Sn浆料)形成，则可使用分配方法、印刷方法例如点胶法、丝网印刷法等。例如，根据上述实施方案，为通过使用Sn浆料形成具有第二金属的层6，例如通过丝网印刷方法形成Sn浆料。然后，使Sn浆料进行回流加工，以在近似等于或高于Sn的熔点232℃或者最高250℃的并且持续时间为约30秒以上的条件下形成。在这种情况下，如上述实施方案一样，在半导体芯片1安装于引线框的载台2上时，可防止半导体芯片1的位置偏移例如移动或旋转。以上述方式形成的半导体器件中的半导体芯片的操作中的热阻等于或低于约0.3℃/W。该热阻与通过钎料接合制造的半导体器件的热阻几乎相等。即使半导体芯片1与引线框的载台2以上述方式接合，半导体芯片1的热也可通过Ag层5，Sn-Ag合金层9和引线框的载台2散至外部。
包括具有第一金属和第二金属的合金的层9为具有第一金属Ag、Cu、Au、Bi、In、Ni、Pb和Sb以及与第一金属具有反应性的第二金属中的一种的层并且形成合金。例如，包括具有第一金属和第二金属的合金的层为包括第一金属Ag、Cu、Au、Bi、In、Ni、Pb和Sb中的一种、以及第二金属Sn、Bi、In、Zn、Ag、Sb、Cu、Ni和Pb中的一种的层。包括具有第一金属和第二金属的合金的层可为具有第一金属和第二金属的合金层。包括具有第一金属和第二金属的合金的层可为具有第一金属、第二金属和另一金属的合金层。包括具有第一金属和第二金属的合金的层可为具有第一金属和第二金属的合金、第一金属以及第二金属的层。包括具有第一金属和第二金属的合金的层可为具有树脂以及具有第一金属和第二金属的合金的层。在这种情况下，包括具有第二金属和第二金属的合金以及树脂的层为例如与包括第一金属和第二金属的合金混合的导热树脂层。
根据上述第一实施方案，可形成Cr层8作为具有第三金属的层。具有第三金属的层不限于此情形。具有第三金属的层8包括与第二金属不具有反应性的金属，即与第二金属不形成固溶体的金属。例如，具有第三金属的层8包括Cr、Fe、Ti和Zr中的一种。
根据上述实施方案，在引线框的载台2上的半导体芯片安装区域2A的整个表面上形成具有第一金属的层5，在半导体芯片1的背表面的一部分(中心部分的一部分)中形成具有第二金属的层6。然而，层5和层6不限于上述情形。即，在引线框的载台2上的半导体芯片安装区域2A和半导体芯片1的背表面中的一个上形成具有第一金属的层5和具有第二金属的层6中的一个。具有第一金属的层5和具有第二金属的层6中的另一个可在与其中半导体芯片安装区域2A和半导体芯片1的背表面的另一个的具有第一金属的层5和具有第二金属的层6中的一个的区域中的一部分对应的区域中形成。
例如，可在引线框的载台2上的半导体芯片安装区域2A的一部分(中心部分的一部分)中形成具有第一金属的层5，可在半导体芯片1的背表面的整个表面上形成具有第二金属的层6。在引线框的载台2上的半导体芯片安装区域2A的一部分(中心部分的一部分)中形成的具有第一金属的层5和在与该部分相对的区域中形成的具有第二金属的层6熔融。在除了该区域之外的区域(在中心部分之外的区域)中形成的具有第二金属的层6不熔融而仍为固体。这防止半导体芯片1的位置偏移例如移动或旋转。在引线框的载台2上的半导体芯片安装区域2A的中心部分中形成具有第一金属的层5。由于这个，所以防止包括第一金属和第二金属的层9在半导体芯片安装区域2A周围渗出。
如图6A所示，可在引线框的载台2上的半导体芯片安装区域2A的整个表面上形成具有第一金属的层5(在这种情况下，Ag层)。如图6B所示，在半导体芯片1的背表面的一部分(多个部分)中可形成具有第二金属的层6(在这种情况下，Sn层)。例如，优选具有第二金属的层6(在这种情况下，Sn层)在半导体芯片1的背表面的对角线上的两个位置中形成。Sn层6可例如通过电解电镀方法或者丝网印刷方法形成。如图6C所示，在载台2的半导体芯片安装区域2A上定位半导体芯片1。如图6D所示，形成Sn-Ag合金层9，并且半导体芯片1与载台2上的半导体芯片安装区域2A接合。因此，在半导体芯片1的背表面的部分(多个部分)中形成的具有第二金属的层6和在与该部分相对的区域中形成的具有第一金属的层5、以及在除了该区域(在多个部分周围的区域)之外的区域中形成的具有第一金属的层5不熔融而仍为固体。这防止半导体芯片1的位置偏移例如移动或旋转。因为在半导体芯片1的背表面的多个位置中形成具有第二金属的层6，所以在热接合的情况下，防止半导体芯片1旋转。在不与引线框的载台2上的半导体芯片安装区域2A的外边缘接触的区域(除了周边之外的区域)的多个部分中形成具有第二金属的层6。这防止包括具有第一金属和第二金属的合金的层9在热接合中在半导体芯片安装区域2A周围渗出。在这种情况下，在引线框的载台2上的半导体芯片安装区域2A周围的区域中形成Cr层8。这确保防止Sn-Ag合金层9渗出。以上述方式形成的半导体器件中的半导体芯片的操作中的热阻值等于或低于约0.3℃/W。该热阻值与通过钎料接合制造的半导体器件的热阻值相当。即使半导体芯片1与引线框的载台2接合，半导体芯片1的热也可通过Ag层5，Sn-Ag合金层9和引线框的载台2而散至外部。图6A至6D示出在引线框的载台2上的半导体芯片安装区域2A周围的区域中形成Cr层8情形的一个实例。然而，第一实施方案不限于该情形。例如，通常不形成Cr层8。
相反地，在引线框的载台2上的半导体芯片安装区域2A的一部分(多个部分)中形成具有第一金属的层5，可在半导体芯片1的背表面的整个表面上形成具有第二金属的层6。在这种情况下，获得与上述情形相当的操作和效果。如图7A所示，例如，可在引线框的载台2上的半导体芯片安装区域2A的整个表面上形成具有第一金属的层5(在这种情况下，Ag层)。如图7B所示，可在半导体芯片1的背表面的一部分(周边)中形成具有第二金属的层6(在这种情况下，Sn层)。如图7C所示，在载台2上的半导体芯片安装区域2A上定位半导体芯片1。如图7D所示，形成Sn-Ag合金层9，并且半导体芯片1与载台2上的半导体芯片安装区域2A接合。因此，在半导体芯片1的背表面的部分(周边)中形成的具有第二金属的层6和在与该部分相对的区域中形成的具有第二金属的层6熔融。在除了该区域之外的区域(周边内部的区域)中形成的具有第一金属的层5不熔融而仍为固体。这防止半导体芯片1的位置偏移例如移动或旋转。特别地，因为以上述方式在半导体芯片1的周边中形成具有第二金属的层，所以包括具有第一金属和第二金属的合金的层9可在半导体芯片安装区域2A周围渗出。优选在引线框的载台2上的半导体芯片安装区域2A周围的区域中形成具有与第一金属和第二金属中的至少一个不具有反应性的第三金属的层8(在这种情况下，Cr层)。由于这个，所以防止锡在熔融操作中渗出，即防止Sn-Ag合金层9渗出。以上述方式形成的半导体器件中的半导体芯片的操作中的热阻等于或低于约0.3℃/W。该热阻与通过钎料接合制造的半导体器件的热阻相等。即使半导体芯片1与引线框的载台2接合，半导体芯片1的热也可通过Ag层5，Sn-Ag合金层9和引线框的载台2而有效地散至外部。图7A至7D示出在引线框的载台2上的半导体芯片安装区域2A周围的区域中形成Cr层8情形的一个实例。然而，第一实施方案不限于该情形。可不形成Cr层8。
相反地，在引线框的载台2上的半导体芯片安装区域2A的一部分(周边部分)中形成具有第一金属的层5。在这种情况下，获得与上述情形相当的操作和效果。例如，可在引线框的载台2上的半导体芯片安装区域2A的整个表面上形成具有第二金属的层6，并且可在半导体芯片1的背表面的一部分中形成具有第一金属的层5。因此，在半导体芯片1的背表面的一部分中形成的具有第一金属的层5和在与该部分对应的区域中形成的具有第二金属的层6熔融。在除了上述区域之外的区域中形成的具有第二金属的层6不熔融而仍为固体。这防止半导体芯片1的位置偏移例如移动或旋转。特别地，当在半导体芯片1的背表面的周边上形成具有第一金属的层5时，包括具有第一金属和第二金属的合金的层9可在半导体芯片安装区域2A周围渗出。因此，优选在引线框的载台2上的半导体芯片安装区域2A周围的区域中形成具有与第一金属和第二金属中的至少一个不具有反应性的第三金属的层8。结果，防止Sn在熔融操作中渗出。
相反地，可在引线框的载台2上的半导体芯片安装区域2A的一部分中形成具有第二金属的层6，并且可在半导体芯片1的背表面的整个表面上形成层5。在这种情况下，获得与上述情形相当的操作和效果。根据上述第一实施方案，在引线框的载台2上的半导体芯片安装区域2A的整个表面上形成具有第一金属的层(Ag层)5，并且在半导体芯片1的背表面上的一部分(中心部分的一部分)中形成具有第二金属的层(Sn层)6。因此，制造的半导体器件包括：设置于载台2和半导体芯片1之间的具有第一金属的层(Ag层)5，并且包括具有第一金属和第二金属的合金的层(Sn-Ag合金层；具有通过合金化第一金属获得的合金的层)9。然而，第一实施方案不限于该情形。
例如，如果在引线框的载台2上的半导体芯片安装区域2A的整个表面上形成具有第二金属的层6和如果在半导体芯片1的背表面的一部分上形成具有第一金属的层5，制造的半导体器件包括设置于载台2和半导体芯片1之间的具有第二金属的层6，并且包括：包括具有第一金属和第二金属的合金的层(具有通过合金化第二金属获得的合金的层)9。在这种情况下，具有第二金属的层6与载台2接合并与半导体芯片1接触。
例如，如果在引线框的载台2上的半导体芯片安装区域2A的的一部分中形成具有第一金属的层5和如果在半导体芯片1的背表面的整个表面上形成具有第二金属的层6，则制造的半导体器件包括设置于载台2和半导体芯片1之间的具有第二金属的层6，并且包括：包括具有第一金属和第二金属的合金的层(具有通过合金化第二金属获得的合金的层)9。在这种情况下，具有第二金属的层6与半导体芯片1接合并与载台2接触。
例如，如果在引线框的载台2上的半导体芯片安装区域2A的的一部分中形成具有第二金属的层6和如果在半导体芯片1的背表面的整个表面上形成具有第一金属的层5，则制造的半导体器件包括设置于载台2和半导体芯片1之间的具有第一金属的层5，并且包括：包括具有第一金属和第二金属的合金的层(具有通过合金化第一金属获得的合金的层)9。在这种情况下，具有第一金属的层5与半导体芯片1接合并与载台2接触。
根据上述实施方案，因为在引线框的载台2上的半导体芯片安装区域2A的整个表面上形成具有第一金属的层(Ag层5)和在半导体芯片1的一部分(中心部分的一部分)中形成具有第二金属的层(Sn层)6，所以制造的半导体器件包括在载台2上的半导体芯片安装区域2A的中心部分中的层(Sn-Ag合金层；具有通过合金化第一金属获得的合金的层)9，其包括具有第一金属和第二金属的合金；并且包括在载台2上的半导体芯片安装区域的中心部分外的具有第一金属的层(Ag层)5。第一实施方案不限于此情形。
例如，如果在引线框的载台2上的半导体芯片安装区域2A的一部分(中心部分的一部分)中形成具有第一金属的层5和如果在半导体芯片1的背表面的整个表面上形成具有第二金属的层6，制造的半导体器件包括在载台2上的半导体芯片安装区域2A的中心部分中的层(具有合金化第二金属获得的合金的层)9，其包括具有第一金属和第二金属的合金，并且包括在载台2上的半导体芯片安装区域2A的中心部分外的具有第二金属的层6。
例如，如果在引线框的载台2上的半导体芯片安装区域2A的整个表面上形成具有第一金属的层5和如果在半导体芯片1的背表面的一部分(多个部分)中形成具有第二金属的层6，制造的半导体器件包括在载台2上的半导体芯片安装区域2A的多个部分中的具有第一金属和第二金属合金的层9，并且包括在提供于载台2上的半导体芯片安装区域2A的多个部分中的具有合金的层9周围的具有第一金属的层5。相反地，如果在引线框的载台2上的半导体芯片安装区域2A的一部分(多个部分)中形成具有第一金属的层5和如果在半导体芯片1的背表面的整个表面上形成具有第二金属的层6，则制造的半导体器件包括在载台2上的半导体芯片安装区域2A的多个部分中的层(具有合金化第二金属获得的合金的层)9，其包括具有第一金属和第二金属的合金；并且包括在设置于载台2上的半导体芯片安装区域2A的多个部分中的具有合金的层周围的具有第二金属的层6。
例如，如果在引线框的载台2上的半导体芯片安装区域2A的整个表面上形成具有第一金属的层5和如果在半导体芯片1的背表面的一部分(周边部分)中形成具有第二金属的层6，则制造的半导体器件包括在载台2上的半导体芯片安装区域2A的周边中的具有第一金属和第二金属的层9(该层具有合金化第一金属获得的合金)，并且包括在载台2上的半导体芯片安装区域2A的周边部分内部的具有第一金属的层5。相反地，如果在引线框的载台2上的半导体芯片安装区域2A的一部分(周边)中形成具有第一金属的层5和如果在半导体芯片1的背表面的整个表面上形成具有第二金属的层6，则制造的半导体器件包括在载台2上的半导体芯片安装区域2A的周边中的层(具有通过合金化第二金属获得的合金的层)9，其包括具有第一金属和第二金属的合金，并且包括在载台2上的半导体芯片安装区域2A的周边内部的具有第二金属的层6。
例如，如果在引线框的载台2上的半导体芯片安装区域2A的周围的区域中形成具有与第一金属和第二金属中的至少一个不具有反应性的第三金属，则制造的半导体器件包括：具有与包含于具有合金的层9中的第一金属和第二金属中的至少一个不具有反应性的第三金属的层8，即具有与包含于具有合金的层9中的金属不具有反应性的另一金属的层8。
根据实施方案的变化实例(见图7A～7D)，例如，如图8A～8D所示，在半导体芯片1与半导体芯片安装区域2A接合之前，可在具有第一金属的层5的表面上形成突出部10。例如，存在三种用于形成突出部10的方法。第一种为：在通过例如电解电镀方法形成Ag层5时通过改变电流密度和以岛形形式施加Ag来形成突出部10的方法。例如，在通过电解电镀方法形成厚度为约5μm的Ag层5时，通过改变电流密度形成表面粗糙度为±3μm的Ag层5。第二种为：通过利用氧化铝、石榴石和粒径为#100～#200的玻璃珠对Ag层5实施喷砂加工使得Ag层5的表面粗糙以在Ag层5的表面上形成突出部10的方法。第三种为：通过喷雾平均粒径为约10μm～20μm的Ag粉或Ag浆料以将Ag粉或Ag浆料固定于Ag层5在Ag层5的表面上形成突出部10的方法。在这种情况下，关于制造的半导体器件，在Ag层5的表面上形成突出部10。以此方式，在半导体芯片1与半导体芯片安装区域2A接合之前，可在形成于半导体芯片安装区域2A和半导体芯片1的背表面中的一个的整个表面上的具有第二金属的层6和具有第一金属的层5中的一个的表面上形成突出部10。在这种情况下，关于制造的半导体器件，在具有金属的层(在这种情况下，Ag层)的表面上形成突出部10。因此，在半导体芯片1与引线框的载台2上的半导体芯片安装区域2A接合时，突出部10塑性变形。因此，载台2上的半导体芯片安装区域2A和半导体芯片1的表面的接触面积增加，使得可实现热阻减小。以上述方式形成的半导体器件中的半导体芯片的操作中的热阻等于或低于约0.1℃/W。该热阻小于通过钎料接合制造的半导体器件的热阻。即使半导体芯片1与引线框的载台2以上述方式接合，半导体芯片1的热也可通过Ag层5、Sn-Ag合金层9和突出部10以及载台2而有效地散至外部。图8A至8D示出在引线框的载台2上的半导体芯片安装区域2A周围的区域中形成Cr层8的情形。然而，第一实施方案不限于该情形。可不形成Cr层8。图8A至8D示出应用于上述实施方案的变化实例的情形。第一实施方案不限于该情形。该情形适用于上述实施方案(见图1A～1D)和另一实施方案(见图5A～5C和图6A～6D)。
根据上述第一实施方案，给出分立封装作为一个实例。然而，第一实施方案不限于分立封装。其它半导体封装件也是适用的。根据上述第一实施方案，因为通过利用引线框制造的半导体器件，所以制造的半导体器件包括引线框的载台2上的半导体芯片1。然而，第一实施方案不限于此情形。如图9所示，例如，在电路基板11例如具有球阵列封装(BGA)球12的封装基板上提供半导体芯片1，并且利用接合线4(例如Au线)使半导体芯片1与电路基板11耦接。在利用模制化合物7封装的半导体器件(半导体封装件)中，本发明适用于用于将半导体芯片1与电路基板11接合的接合层3。本发明可适用于在电路基板例如印刷基板(配线基板)等上包括半导体芯片的半导体器件。电路基板例如封装基板或印刷基板称为支撑板。
参考图10，将描述根据第二实施方案的电源器件。
根据第二实施方案的电源器件包括具有上述GaN-HEMT的半导体封装件。例如，在上述半导体封装件中包括的GaN-HEMT用于包括于用于服务器的电源器件中的功率因子校正(PFC)电路。
如图10所示，PFC电路包括：二极管桥30、扼流圈31、第一电容器32、包括于上述半导体封装件中的GaN-HEMT 33、二极管34以及第二电容器35。在这种情况下，PFC电路具有其中二极管桥30、扼流圈31、第一电容器32、包括于上述半导体封装件中的GaN-HEMT 33、二极管34和第二电容器35安装于电路基板上的结构。
根据第二实施方案，将上述半导体封装件的漏极引线23、源极引线22和栅极引线21分别插入电路基板的漏极引线插入装置、源极引线插入装置和栅极引线插入装置中，并任何利用例如钎料进行固定。以此方式，包括于上述半导体封装件中的GaN-HEMT 33与形成于电路基板上PFC电路的耦接。
在PFC电路上，扼流圈31的端子之一和二极管34的阳极端子与GaN-HEMT 33的漏电极D耦接。扼流圈31的另一端子与第一电容器32的端子之一耦接，二极管34的阴极端子与第二电容器的端子之一耦接。第一电容器32的另一端子、GaN-HEMT 33的源电极S和第二电容器35的另一端子接地。第一电容器32的两个端子与二极管桥30的一对端子耦接。二极管桥30的另一对端子与输入交流(AC)电压的输入端子耦接。第二电容器35的两个端子与输出直流(DC)电压的输出端子耦接。GaN-HEMT 33的栅电极G与栅极驱动器(未示出)耦接。如果那GaN-HEMT 33通过栅极驱动器驱动，则PFC电路将从输入端子输入的交流电压转换为直流电压，并然后将直流电压从输出端子输出。
因此，根据第二实施方案的电源器件具有改善可靠性的优势。即，因为根据第一实施方案的半导体封装件具有高可靠性，所以存在可构造出具有高可靠性的电源器件的优势。在这种情况下，已经在用于包括于用于服务器的电源器件中的PFC电路的情形中描述了上述半导体器件(GaN-HEMT或具有GaN-HEMT的半导体封装件)。然而，第二实施方案不限于此情形。例如，除了服务器之外，上述半导体器件(GaN-HEMT或具有GaN-HEMT的半导体封装件)也可用于电子设备(电子器件)例如计算机中。上述半导体器件(半导体封装件)可用于包括于电源器件中的另一电路(例如DC-DC转换器)。本发明不限于上述实施方案和变化实例中描述的结构。
例如，在上述实施方案和变化实例的描述中，给出包括GaN-HEMT的半导体芯片作为实例。然而，半导体芯片不限于该实例。
本文记载的所有实例和附条件的措辞均为意图教导目的，以有助于读者理解本发明和本发明人为改进现有技术做出的构思，并且应被认为是不限于这种具体记载的实例和条件，并且在本说明书中这种实例的组织也不涉及显示本发明的优势和不足。虽然已经详述了本发明的一个或更多个实施方案，但是应理解可对其做出各种变化、替代和变更，而未脱离本发明的精神和范围。

Claims (19)

1.一种制造半导体器件的方法，包括：
在支撑板的半导体芯片安装区域和所述半导体芯片的背表面中的一个上形成具有第一金属的层和具有第二金属的层中的一个；
在所述半导体芯片安装区域和所述半导体芯片的背表面中的另一个的与其中具有所述第一金属的层和具有所述第二金属的层中的一个的区域的一部分对应的区域上，形成具有所述第一金属的层和具有所述第二金属的层中的另一个，以及
在所述半导体芯片安装区域中定位所述半导体芯片之后，形成包括具有所述第一金属和所述第二金属的合金的层以将所述半导体芯片与所述半导体芯片安装区域接合，
其中具有所述第一金属的层和具有所述第二金属的层中的一个形成在所述半导体芯片安装区域和所述半导体芯片的背表面中的一个的整个表面上，和
其中具有所述第一金属的层和具有所述第二金属的层中的另一个形成在所述半导体芯片安装区域和所述半导体芯片的背表面中的另一个的部分上。
2.根据权利要求1所述的制造半导体器件的方法，具有所述第一金属的层和具有所述第二金属的层中的另一个形成在所述半导体芯片安装区域和所述半导体芯片的背表面中的另一个的中心部分中。
3.根据权利要求1所述的制造半导体器件的方法，其中具有所述第一金属的层和具有所述第二金属的层中的另一个形成在所述半导体芯片安装区域和所述半导体芯片的背表面中的另一个的多个部分中。
4.根据权利要求1所述的制造半导体器件的方法，其中具有所述第一金属的层和具有所述第二金属的层中的另一个形成在所述半导体芯片安装区域和所述半导体芯片的背表面中的另一个的周边上。
5.根据权利要求1所述的制造半导体器件的方法，还包括：
在所述支撑板上的所述半导体芯片安装区域周围的区域中，形成具有与所述第一金属和所述第二金属中的至少一个不具有反应性的第三金属的层。
6.根据权利要求1所述的制造半导体器件的方法，其中所述第一金属为Ag、Cu、Au、Bi、In、Ni、Pb和Sb中的一种，和
其中所述第二金属通过与所述第一金属反应形成合金。
7.根据权利要求6所述的制造半导体器件的方法，其中所述第二金属为Sn、Bi、In、Zn、Ag、Sb、Cu、Ni和Pb中的一种。
8.根据权利要求5所述的制造半导体器件的方法，其中所述第一金属为Ag、Cu、Au、Bi、In、Ni、Pb和Sb中的一种，
其中通过与所述第一金属反应形成合金的所述第二金属为Sn、Bi、In、Zn、Ag、Sb、Cu、Ni和Pb中的一种，和
其中与所述第二金属不具有反应性的所述第三金属为Cr、Fe、Ti和Zr中的一种。
9.根据权利要求1所述的制造半导体器件的方法，还包括：
在具有所述第一金属的层和具有所述第二金属的层中的一个的表面上形成突出部。
10.根据权利要求1所述的制造半导体器件的方法，还包括：
在所述半导体芯片的背表面上形成具有所述第一金属的层或具有所述第二金属的层之前，在所述半导体芯片的所述背表面上形成粘合层。
11.一种半导体器件，包括：
支撑板；
设置在所述支撑板上的半导体芯片；
设置在所述支撑板和所述半导体芯片之间的层，所述层具有与所述支撑板和所述半导体芯片中的一个接合的金属；和
设置在所述支撑板和所述半导体芯片之间的另一层，所述层具有通过使用于将所述支撑板接合于所述半导体芯片的金属合金化所获得的合金。
12.根据权利要求11所述的半导体器件，其中具有所述合金的层设置在所述支撑板的所述半导体芯片安装区域的中心部分中，和
其中具有所述金属的层设置在所述支撑板上的所述半导体芯片安装区域的中心部分以外。
13.根据权利要求11所述的半导体器件，其中具有所述合金的层设置在所述支撑板的所述半导体芯片安装区域的多个部分中，和
其中具有所述金属的层设置于在所述支撑板的所述半导体芯片安装区域的所述多个部分中设置的具有所述合金的层的周边上。
14.根据权利要求11所述的半导体器件，其中具有所述合金的层设置在所述支撑板的所述半导体芯片安装区域的周边上；和其中具有所述金属的层设置在所述支撑板的所述半导体芯片安装区域的周边以内。
15.根据权利要求11所述的半导体器件，其中所述半导体器件包括：设置在所述半导体芯片区域的周边上并且包括与包含在具有所述合金的层中的所述金属不具有反应性的另一金属的层。
16.根据权利要求11所述的半导体器件，其中具有所述金属的层包括在其表面上的突出部。
17.根据权利要求11所述的半导体器件，其中具有所述金属的层和具有所述合金的层还包括树脂。
18.根据权利要求11所述的半导体器件，其中在所述半导体芯片和具有所述合金的层之间设置有粘合层。
19.一种电源器件，包括：
支撑板；
设置在所述支撑板上的半导体芯片；
设置在所述支撑板和所述半导体芯片之间的层，其具有与所述支撑板和所述半导体芯片中的一个接合的金属；和
半导体器件，其包括设置在所述支撑板和所述半导体芯片之间的另一层，所述层具有通过使用于将所述支撑板接合于所述半导体芯片的所述金属合金化所获得的合金。
CN201210031859.XA 2011-02-22 2012-02-13 半导体器件、半导体器件的制造方法以及电源器件 Expired - Fee Related CN102646609B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011036254A JP5772050B2 (ja) 2011-02-22 2011-02-22 半導体装置及びその製造方法、電源装置
JP2011-036254 2011-02-22

Publications (2)

Publication Number Publication Date
CN102646609A CN102646609A (zh) 2012-08-22
CN102646609B true CN102646609B (zh) 2014-12-03

Family

ID=46652090

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210031859.XA Expired - Fee Related CN102646609B (zh) 2011-02-22 2012-02-13 半导体器件、半导体器件的制造方法以及电源器件

Country Status (4)

Country Link
US (2) US8728867B2 (zh)
JP (1) JP5772050B2 (zh)
CN (1) CN102646609B (zh)
TW (1) TWI536467B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103916001A (zh) * 2012-12-30 2014-07-09 比亚迪股份有限公司 一种自主功率因数校正装置
JP6613194B2 (ja) * 2016-03-30 2019-11-27 東レエンジニアリング株式会社 半導体装置の製造方法及び製造装置
JP6682391B2 (ja) * 2016-07-22 2020-04-15 株式会社東芝 半導体装置、電源回路、及び、コンピュータ
US10741644B2 (en) * 2016-11-22 2020-08-11 Delta Electronics, Inc. Semiconductor devices with via structure and package structures comprising the same
US11107755B2 (en) * 2019-05-12 2021-08-31 Zhanming LI Packaging for lateral high voltage GaN power devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1288591A (zh) * 1998-01-20 2001-03-21 时至准钟表股份有限公司 半导体装置和制造方法及其安装构造和安装方法
CN1465098A (zh) * 2001-07-31 2003-12-31 索尼公司 半导体器件及其制造方法
US6781247B2 (en) * 2001-10-23 2004-08-24 Rohm Co., Ltd. Semiconductor device
CN1819172A (zh) * 2005-01-20 2006-08-16 日产自动车株式会社 半导体装置及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58207645A (ja) 1982-05-28 1983-12-03 Fujitsu Ltd 半導体装置
JPH06132442A (ja) 1992-10-19 1994-05-13 Hitachi Ltd 半導体装置およびその製造方法
US5436503A (en) * 1992-11-18 1995-07-25 Matsushita Electronics Corporation Semiconductor device and method of manufacturing the same
KR0181615B1 (ko) * 1995-01-30 1999-04-15 모리시다 요이치 반도체 장치의 실장체, 그 실장방법 및 실장용 밀봉재
JP3409957B2 (ja) * 1996-03-06 2003-05-26 松下電器産業株式会社 半導体ユニット及びその形成方法
US7193326B2 (en) * 2003-06-23 2007-03-20 Denso Corporation Mold type semiconductor device
JP4882229B2 (ja) * 2004-09-08 2012-02-22 株式会社デンソー 半導体装置およびその製造方法
JP2006156437A (ja) 2004-11-25 2006-06-15 Seiko Epson Corp リードフレーム及び半導体装置
JP4325571B2 (ja) 2005-02-28 2009-09-02 株式会社日立製作所 電子装置の製造方法
JP2007150119A (ja) * 2005-11-30 2007-06-14 Nec Corp 半導体パッケージ及びそれに用いるＡｕＳｎ膜付け工法
JP2009158725A (ja) * 2007-12-27 2009-07-16 Panasonic Corp 半導体装置およびダイボンド材

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1288591A (zh) * 1998-01-20 2001-03-21 时至准钟表股份有限公司 半导体装置和制造方法及其安装构造和安装方法
CN1465098A (zh) * 2001-07-31 2003-12-31 索尼公司 半导体器件及其制造方法
US6781247B2 (en) * 2001-10-23 2004-08-24 Rohm Co., Ltd. Semiconductor device
CN1819172A (zh) * 2005-01-20 2006-08-16 日产自动车株式会社 半导体装置及其制造方法

Also Published As

Publication number Publication date
US8728867B2 (en) 2014-05-20
US20140203444A1 (en) 2014-07-24
US9082756B2 (en) 2015-07-14
TWI536467B (zh) 2016-06-01
CN102646609A (zh) 2012-08-22
US20120211901A1 (en) 2012-08-23
JP2012174926A (ja) 2012-09-10
JP5772050B2 (ja) 2015-09-02
TW201250877A (en) 2012-12-16

Similar Documents

Publication Publication Date Title
US10297522B2 (en) Semiconductor package structure and manufacturing method thereof
TWI485817B (zh) 微電子封裝及其散熱方法
CN101996894B (zh) 半导体器件和围绕管芯周边形成坝材料以减小翘曲的方法
US9018744B2 (en) Semiconductor device having a clip contact
CN102244012B (zh) 半导体器件及其制造方法
CN102237281B (zh) 半导体器件及其制造方法
US8916474B2 (en) Semiconductor modules and methods of formation thereof
CN102646609B (zh) 半导体器件、半导体器件的制造方法以及电源器件
US20160126197A1 (en) Semiconductor device having a stress-compensated chip electrode
CN104253105A (zh) 半导体器件和形成低廓形3d扇出封装的方法
US11145581B2 (en) Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks
US7829384B2 (en) Semiconductor device and method of laser-marking wafers with tape applied to its active surface
CN102403239A (zh) 半导体器件及形成用于在Fo-WLCSP中安装半导体小片的引线上键合互连的方法
CN101996893A (zh) 半导体器件及其制造方法
TW201104761A (en) Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure
US20140001480A1 (en) Lead Frame Packages and Methods of Formation Thereof
US9449902B2 (en) Semiconductor packages having multiple lead frames and methods of formation thereof
US8674520B2 (en) Semiconductor device, method for manufacturing the same, and power supply unit
US8822327B2 (en) Contact pads with sidewall spacers and method of making contact pads with sidewall spacers
JP5613100B2 (ja) 半導体装置の製造方法
US20140048958A1 (en) Pad Sidewall Spacers and Method of Making Pad Sidewall Spacers
JP2015082581A (ja) 電力用半導体装置およびその製造方法
KR20150142916A (ko) 반도체 패키지 및 그 제조방법
KR101474618B1 (ko) 전력 모듈 패키지
CN115732449A (zh) 具有含Ni层的半导体装置及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20141203

Termination date: 20210213