TWI287358B - Delay locked loop device - Google Patents

Delay locked loop device Download PDF

Info

Publication number
TWI287358B
TWI287358B TW093118215A TW93118215A TWI287358B TW I287358 B TWI287358 B TW I287358B TW 093118215 A TW093118215 A TW 093118215A TW 93118215 A TW93118215 A TW 93118215A TW I287358 B TWI287358 B TW I287358B
Authority
TW
Taiwan
Prior art keywords
signal
delay
block
inverter
comparison
Prior art date
Application number
TW093118215A
Other languages
English (en)
Chinese (zh)
Other versions
TW200537814A (en
Inventor
Jong-Tae Kwak
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200537814A publication Critical patent/TW200537814A/zh
Application granted granted Critical
Publication of TWI287358B publication Critical patent/TWI287358B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B5/00—Measuring arrangements characterised by the use of mechanical techniques
    • G01B5/30—Measuring arrangements characterised by the use of mechanical techniques for measuring the deformation in a solid, e.g. mechanical strain gauge
    • E—FIXED CONSTRUCTIONS
    • E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
    • E02D—FOUNDATIONS; EXCAVATIONS; EMBANKMENTS; UNDERGROUND OR UNDERWATER STRUCTURES
    • E02D1/00—Investigation of foundation soil in situ
    • E02D1/08—Investigation of foundation soil in situ after finishing the foundation structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Landscapes

  • Life Sciences & Earth Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Mining & Mineral Resources (AREA)
  • Paleontology (AREA)
  • Analytical Chemistry (AREA)
  • Soil Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • General Life Sciences & Earth Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Civil Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Structural Engineering (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
TW093118215A 2004-05-06 2004-06-24 Delay locked loop device TWI287358B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2004-0031983A KR100537202B1 (ko) 2004-05-06 2004-05-06 지연고정루프의 지연고정상태 정보의 이용이 가능한반도체 소자

Publications (2)

Publication Number Publication Date
TW200537814A TW200537814A (en) 2005-11-16
TWI287358B true TWI287358B (en) 2007-09-21

Family

ID=35239297

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093118215A TWI287358B (en) 2004-05-06 2004-06-24 Delay locked loop device

Country Status (6)

Country Link
US (1) US7099232B2 (enExample)
JP (2) JP2005323323A (enExample)
KR (1) KR100537202B1 (enExample)
CN (1) CN1694181B (enExample)
DE (1) DE102004031450B4 (enExample)
TW (1) TWI287358B (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100537202B1 (ko) * 2004-05-06 2005-12-16 주식회사 하이닉스반도체 지연고정루프의 지연고정상태 정보의 이용이 가능한반도체 소자
KR100713082B1 (ko) * 2005-03-02 2007-05-02 주식회사 하이닉스반도체 클럭의 듀티 비율을 조정할 수 있는 지연 고정 루프
KR100834400B1 (ko) 2005-09-28 2008-06-04 주식회사 하이닉스반도체 Ｄｒａｍ의 동작 주파수를 높이기 위한 지연고정루프 및 그의 출력드라이버
KR100743493B1 (ko) * 2006-02-21 2007-07-30 삼성전자주식회사 적응식 지연 고정 루프
JP4714037B2 (ja) * 2006-02-23 2011-06-29 シャープ株式会社 同期型メモリのコントロールシステム
KR100757921B1 (ko) 2006-03-07 2007-09-11 주식회사 하이닉스반도체 반도체 메모리 장치의 ｄｌｌ 회로 및 클럭 지연 고정 방법
JP5134779B2 (ja) * 2006-03-13 2013-01-30 ルネサスエレクトロニクス株式会社 遅延同期回路
KR100813528B1 (ko) 2006-06-27 2008-03-17 주식회사 하이닉스반도체 지연 고정 루프의 딜레이 라인 및 그 딜레이 타임 제어방법
JP2008217209A (ja) 2007-03-01 2008-09-18 Hitachi Ltd 差分スナップショット管理方法、計算機システム及びｎａｓ計算機
KR100856070B1 (ko) * 2007-03-30 2008-09-02 주식회사 하이닉스반도체 반도체 메모리 장치 및 그의 구동방법
KR100863016B1 (ko) * 2007-05-31 2008-10-13 주식회사 하이닉스반도체 동작 모드 설정 장치, 이를 포함하는 반도체 집적 회로 및반도체 집적 회로의 제어 방법
JP2009021706A (ja) * 2007-07-10 2009-01-29 Elpida Memory Inc Ｄｌｌ回路及びこれを用いた半導体記憶装置、並びに、データ処理システム
JP5377843B2 (ja) * 2007-09-13 2013-12-25 ピーエスフォー ルクスコ エスエイアールエル タイミング制御回路及び半導体記憶装置
KR20090045773A (ko) * 2007-11-02 2009-05-08 주식회사 하이닉스반도체 고속으로 동작하는 반도체 장치의 지연 고정 회로
US7795937B2 (en) * 2008-03-26 2010-09-14 Mstar Semiconductor, Inc. Semi-digital delay locked loop circuit and method
KR100968460B1 (ko) * 2008-11-11 2010-07-07 주식회사 하이닉스반도체 Ｄｌｌ 회로 및 ｄｌｌ 회로의 업데이트 제어 장치
KR101123073B1 (ko) * 2009-05-21 2012-03-05 주식회사 하이닉스반도체 지연고정루프회로 및 이를 이용한 반도체 메모리 장치
KR101222064B1 (ko) * 2010-04-28 2013-01-15 에스케이하이닉스 주식회사 반도체 집적회로의 지연고정루프 및 그의 구동방법
US9553594B1 (en) 2015-12-15 2017-01-24 Freescale Semiconductor, Inc. Delay-locked loop with false-lock detection and recovery circuit
CN114079457A (zh) * 2020-08-11 2022-02-22 长鑫存储技术有限公司 延迟锁定环电路

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577635A (en) * 1980-06-17 1982-01-14 Fujitsu Ltd Measuring method of phase synchronizing circuit
JP2525457B2 (ja) 1988-06-03 1996-08-21 日本電気ホームエレクトロニクス株式会社 同期補捉追跡方法および装置
US6222894B1 (en) * 1996-12-18 2001-04-24 Samsung Electronics Co., Ltd. Digital delay locked loop for reducing power consumption of synchronous semiconductor memory device
US5940609A (en) * 1997-08-29 1999-08-17 Micorn Technology, Inc. Synchronous clock generator including a false lock detector
US5926047A (en) * 1997-08-29 1999-07-20 Micron Technology, Inc. Synchronous clock generator including a delay-locked loop signal loss detector
JP3908356B2 (ja) 1997-10-20 2007-04-25 富士通株式会社 半導体集積回路
JP3789222B2 (ja) * 1998-01-16 2006-06-21 富士通株式会社 Ｄｌｌ回路及びそれを内蔵するメモリデバイス
US6269451B1 (en) * 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
JP3523069B2 (ja) * 1998-06-30 2004-04-26 株式会社東芝 遅延型位相同期回路
JP3769940B2 (ja) * 1998-08-06 2006-04-26 株式会社日立製作所 半導体装置
US6345068B1 (en) * 1998-09-16 2002-02-05 Infineon Technologies Ag Hierarchical delay lock loop code tracking system with multipath correction
JP2001023383A (ja) 1999-07-02 2001-01-26 Hitachi Ltd 半導体装置、メモリカード及びデータ処理システム
KR100521418B1 (ko) * 1999-12-30 2005-10-17 주식회사 하이닉스반도체 지연고정루프에서 짧은 록킹 시간과 높은 잡음 제거를갖는 딜레이 제어기
US6346839B1 (en) * 2000-04-03 2002-02-12 Mosel Vitelic Inc. Low power consumption integrated circuit delay locked loop and method for controlling the same
US6333959B1 (en) * 2000-04-25 2001-12-25 Winbond Electronics Corporation Cross feedback latch-type bi-directional shift register in a delay lock loop circuit
JP2002124873A (ja) * 2000-10-18 2002-04-26 Mitsubishi Electric Corp 半導体装置
US6437616B1 (en) * 2000-12-19 2002-08-20 Ami Semiconductor, Inc. Delay lock loop with wide frequency range capability
JP2002324398A (ja) * 2001-04-25 2002-11-08 Mitsubishi Electric Corp 半導体記憶装置、メモリシステムおよびメモリモジュール
JP3779713B2 (ja) * 2001-05-30 2006-05-31 ザインエレクトロニクス株式会社 半導体集積回路
JP2003037486A (ja) * 2001-07-23 2003-02-07 Mitsubishi Electric Corp 位相差検出回路
US6628154B2 (en) * 2001-07-31 2003-09-30 Cypress Semiconductor Corp. Digitally controlled analog delay locked loop (DLL)
KR100437611B1 (ko) * 2001-09-20 2004-06-30 주식회사 하이닉스반도체 혼합형 지연 록 루프 회로
KR100537202B1 (ko) * 2004-05-06 2005-12-16 주식회사 하이닉스반도체 지연고정루프의 지연고정상태 정보의 이용이 가능한반도체 소자

Also Published As

Publication number Publication date
US20050249027A1 (en) 2005-11-10
DE102004031450A1 (de) 2005-12-01
DE102004031450B4 (de) 2011-01-13
JP5055448B2 (ja) 2012-10-24
KR20050106915A (ko) 2005-11-11
CN1694179A (zh) 2005-11-09
KR100537202B1 (ko) 2005-12-16
JP2005323323A (ja) 2005-11-17
CN1694181B (zh) 2010-05-26
TW200537814A (en) 2005-11-16
US7099232B2 (en) 2006-08-29
JP2011142665A (ja) 2011-07-21

Similar Documents

Publication Publication Date Title
TWI287358B (en) Delay locked loop device
US8867302B2 (en) Data input circuit
US7706210B2 (en) Semiconductor memory device including delay locked loop and method for driving the same
KR100956774B1 (ko) 지연 고정 루프 회로 및 그 제어 방법
US8519758B2 (en) Digital DLL including skewed gate type duty correction circuit and duty correction method thereof
US20050248997A1 (en) Semiconductor memory device for controlling output timing of data depending on frequency variation
US8031553B2 (en) Data strobe signal generating device and a semiconductor memory apparatus using the same
JP5149076B2 (ja) 遅延固定ループ
US7983106B2 (en) Voltage stabilization circuit and semiconductor memory apparatus using the same
US8503256B2 (en) Column command buffer and latency circuit including the same
JP2011060364A (ja) クロック生成回路及びこれを備える半導体装置並びにデータ処理システム
US20110051531A1 (en) Data output control circuit of a double data rate (ddr) synchronous semiconductor memory device responsive to a delay locked loop (dll) clock
KR101589542B1 (ko) 라이트드라이빙 장치
US7408394B2 (en) Measure control delay and method having latching circuit integral with delay circuit
TW527597B (en) Internal clock generating circuit of synchronous type semiconductor memory device and method thereof
KR100911190B1 (ko) 내부 클럭 드라이버 회로
US7161856B2 (en) Circuit for generating data strobe signal of semiconductor memory device
CN110349610B (zh) 动态随机存取存储器中控制延迟锁相环的控制电路与方法
US7710158B2 (en) Command decoder and command signal generating circuit
US7764099B2 (en) Semiconductor integrated circuit device
TWI420533B (zh) 半導體積體電路中輸出資料之裝置
US7952957B2 (en) Circuit for generating read and signal and circuit for generating internal clock using the same
US7995416B2 (en) Semiconductor memory device and operation method thereof
KR100921828B1 (ko) 반도체 소자와 그의 구동 방법
CN116230061A (zh) 用于延迟测量初始化的设备及方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees