JP2005323323A - ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子 - Google Patents

ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子 Download PDF

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Publication number
JP2005323323A
JP2005323323A JP2004190213A JP2004190213A JP2005323323A JP 2005323323 A JP2005323323 A JP 2005323323A JP 2004190213 A JP2004190213 A JP 2004190213A JP 2004190213 A JP2004190213 A JP 2004190213A JP 2005323323 A JP2005323323 A JP 2005323323A
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JP
Japan
Prior art keywords
signal
delay
inverter
semiconductor device
phase
Prior art date
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Pending
Application number
JP2004190213A
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English (en)
Japanese (ja)
Inventor
Jong-Tae Kwak
鍾太 郭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
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Hynix Semiconductor Inc
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Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of JP2005323323A publication Critical patent/JP2005323323A/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B5/00—Measuring arrangements characterised by the use of mechanical techniques
    • G01B5/30—Measuring arrangements characterised by the use of mechanical techniques for measuring the deformation in a solid, e.g. mechanical strain gauge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • E—FIXED CONSTRUCTIONS
    • E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
    • E02D—FOUNDATIONS; EXCAVATIONS; EMBANKMENTS; UNDERGROUND OR UNDERWATER STRUCTURES
    • E02D1/00—Investigation of foundation soil in situ
    • E02D1/08—Investigation of foundation soil in situ after finishing the foundation structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

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  • Life Sciences & Earth Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Mining & Mineral Resources (AREA)
  • Paleontology (AREA)
  • Analytical Chemistry (AREA)
  • Soil Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • General Life Sciences & Earth Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Civil Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Structural Engineering (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
JP2004190213A 2004-05-06 2004-06-28 ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子 Pending JP2005323323A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2004-0031983A KR100537202B1 (ko) 2004-05-06 2004-05-06 지연고정루프의 지연고정상태 정보의 이용이 가능한반도체 소자

Related Child Applications (1)

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JP2011040461A Division JP5055448B2 (ja) 2004-05-06 2011-02-25 ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子

Publications (1)

Publication Number Publication Date
JP2005323323A true JP2005323323A (ja) 2005-11-17

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Family Applications (2)

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JP2004190213A Pending JP2005323323A (ja) 2004-05-06 2004-06-28 ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子
JP2011040461A Expired - Fee Related JP5055448B2 (ja) 2004-05-06 2011-02-25 ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子

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JP2011040461A Expired - Fee Related JP5055448B2 (ja) 2004-05-06 2011-02-25 ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子

Country Status (6)

Country Link
US (1) US7099232B2 (enExample)
JP (2) JP2005323323A (enExample)
KR (1) KR100537202B1 (enExample)
CN (1) CN1694181B (enExample)
DE (1) DE102004031450B4 (enExample)
TW (1) TWI287358B (enExample)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007226903A (ja) * 2006-02-23 2007-09-06 Sharp Corp 同期型メモリのコントロールシステム
JP2007243877A (ja) * 2006-03-13 2007-09-20 Renesas Technology Corp 遅延同期回路及び半導体集積回路装置
US7365583B2 (en) 2005-09-28 2008-04-29 Hynix Semiconductor Inc. Delay locked loop for high speed semiconductor memory device
US7414446B2 (en) 2006-03-07 2008-08-19 Hynix Semiconductor Inc. DLL circuit of semiconductor memory apparatus and method of delaying and locking clock in semiconductor memory apparatus
JP2008301473A (ja) * 2007-05-31 2008-12-11 Hynix Semiconductor Inc 動作モード設定装置、それを含む半導体集積回路および半導体集積回路の制御方法
US7890716B2 (en) 2007-03-01 2011-02-15 Hitachi, Ltd. Method of managing time-based differential snapshot
US7944258B2 (en) 2006-06-27 2011-05-17 Hynix Semiconductor Inc. Semiconductor integrated circuit including delay line of delay locked loop and method of controlling delay time using the same
JP2011142665A (ja) * 2004-05-06 2011-07-21 Hynix Semiconductor Inc ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子

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KR100713082B1 (ko) * 2005-03-02 2007-05-02 주식회사 하이닉스반도체 클럭의 듀티 비율을 조정할 수 있는 지연 고정 루프
KR100743493B1 (ko) * 2006-02-21 2007-07-30 삼성전자주식회사 적응식 지연 고정 루프
KR100856070B1 (ko) * 2007-03-30 2008-09-02 주식회사 하이닉스반도체 반도체 메모리 장치 및 그의 구동방법
JP2009021706A (ja) * 2007-07-10 2009-01-29 Elpida Memory Inc Ｄｌｌ回路及びこれを用いた半導体記憶装置、並びに、データ処理システム
JP5377843B2 (ja) * 2007-09-13 2013-12-25 ピーエスフォー ルクスコ エスエイアールエル タイミング制御回路及び半導体記憶装置
KR20090045773A (ko) * 2007-11-02 2009-05-08 주식회사 하이닉스반도체 고속으로 동작하는 반도체 장치의 지연 고정 회로
US7795937B2 (en) * 2008-03-26 2010-09-14 Mstar Semiconductor, Inc. Semi-digital delay locked loop circuit and method
KR100968460B1 (ko) * 2008-11-11 2010-07-07 주식회사 하이닉스반도체 Ｄｌｌ 회로 및 ｄｌｌ 회로의 업데이트 제어 장치
KR101123073B1 (ko) * 2009-05-21 2012-03-05 주식회사 하이닉스반도체 지연고정루프회로 및 이를 이용한 반도체 메모리 장치
KR101222064B1 (ko) * 2010-04-28 2013-01-15 에스케이하이닉스 주식회사 반도체 집적회로의 지연고정루프 및 그의 구동방법
US9553594B1 (en) 2015-12-15 2017-01-24 Freescale Semiconductor, Inc. Delay-locked loop with false-lock detection and recovery circuit
CN114079457A (zh) * 2020-08-11 2022-02-22 长鑫存储技术有限公司 延迟锁定环电路

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JP2525457B2 (ja) 1988-06-03 1996-08-21 日本電気ホームエレクトロニクス株式会社 同期補捉追跡方法および装置
US6222894B1 (en) * 1996-12-18 2001-04-24 Samsung Electronics Co., Ltd. Digital delay locked loop for reducing power consumption of synchronous semiconductor memory device
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US5926047A (en) * 1997-08-29 1999-07-20 Micron Technology, Inc. Synchronous clock generator including a delay-locked loop signal loss detector
JP3908356B2 (ja) 1997-10-20 2007-04-25 富士通株式会社 半導体集積回路
JP3789222B2 (ja) * 1998-01-16 2006-06-21 富士通株式会社 Ｄｌｌ回路及びそれを内蔵するメモリデバイス
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JP3769940B2 (ja) * 1998-08-06 2006-04-26 株式会社日立製作所 半導体装置
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JP2001023383A (ja) 1999-07-02 2001-01-26 Hitachi Ltd 半導体装置、メモリカード及びデータ処理システム
KR100521418B1 (ko) * 1999-12-30 2005-10-17 주식회사 하이닉스반도체 지연고정루프에서 짧은 록킹 시간과 높은 잡음 제거를갖는 딜레이 제어기
US6346839B1 (en) * 2000-04-03 2002-02-12 Mosel Vitelic Inc. Low power consumption integrated circuit delay locked loop and method for controlling the same
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JP3779713B2 (ja) * 2001-05-30 2006-05-31 ザインエレクトロニクス株式会社 半導体集積回路
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KR100437611B1 (ko) * 2001-09-20 2004-06-30 주식회사 하이닉스반도체 혼합형 지연 록 루프 회로
KR100537202B1 (ko) * 2004-05-06 2005-12-16 주식회사 하이닉스반도체 지연고정루프의 지연고정상태 정보의 이용이 가능한반도체 소자

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011142665A (ja) * 2004-05-06 2011-07-21 Hynix Semiconductor Inc ディレイロックループのディレイロック状態の情報の使用が可能な半導体素子
US7365583B2 (en) 2005-09-28 2008-04-29 Hynix Semiconductor Inc. Delay locked loop for high speed semiconductor memory device
US7649390B2 (en) 2005-09-28 2010-01-19 Hynix Semiconductor, Inc. Delay locked loop for high speed semiconductor memory device
JP2007226903A (ja) * 2006-02-23 2007-09-06 Sharp Corp 同期型メモリのコントロールシステム
US7414446B2 (en) 2006-03-07 2008-08-19 Hynix Semiconductor Inc. DLL circuit of semiconductor memory apparatus and method of delaying and locking clock in semiconductor memory apparatus
US7612591B2 (en) 2006-03-07 2009-11-03 Hynix Semiconductor Inc. DLL circuit of semiconductor memory apparatus and method of delaying and locking clock in semiconductor memory apparatus
JP2007243877A (ja) * 2006-03-13 2007-09-20 Renesas Technology Corp 遅延同期回路及び半導体集積回路装置
US7944258B2 (en) 2006-06-27 2011-05-17 Hynix Semiconductor Inc. Semiconductor integrated circuit including delay line of delay locked loop and method of controlling delay time using the same
US7890716B2 (en) 2007-03-01 2011-02-15 Hitachi, Ltd. Method of managing time-based differential snapshot
JP2008301473A (ja) * 2007-05-31 2008-12-11 Hynix Semiconductor Inc 動作モード設定装置、それを含む半導体集積回路および半導体集積回路の制御方法

Also Published As

Publication number Publication date
US20050249027A1 (en) 2005-11-10
DE102004031450A1 (de) 2005-12-01
DE102004031450B4 (de) 2011-01-13
JP5055448B2 (ja) 2012-10-24
KR20050106915A (ko) 2005-11-11
CN1694179A (zh) 2005-11-09
KR100537202B1 (ko) 2005-12-16
CN1694181B (zh) 2010-05-26
TW200537814A (en) 2005-11-16
US7099232B2 (en) 2006-08-29
TWI287358B (en) 2007-09-21
JP2011142665A (ja) 2011-07-21

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