TWI278048B - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
TWI278048B
TWI278048B TW093134108A TW93134108A TWI278048B TW I278048 B TWI278048 B TW I278048B TW 093134108 A TW093134108 A TW 093134108A TW 93134108 A TW93134108 A TW 93134108A TW I278048 B TWI278048 B TW I278048B
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Taiwan
Prior art keywords
semiconductor device
layer
wiring
semiconductor
rewiring
Prior art date
Application number
TW093134108A
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English (en)
Other versions
TW200529338A (en
Inventor
Shinji Wakisaka
Hiroyasu Jobetto
Takeshi Wakabayashi
Ichiro Mihara
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2003379547A external-priority patent/JP4379693B2/ja
Priority claimed from JP2003395313A external-priority patent/JP4321758B2/ja
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Publication of TW200529338A publication Critical patent/TW200529338A/zh
Application granted granted Critical
Publication of TWI278048B publication Critical patent/TWI278048B/zh

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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
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Description

1278048 九、發明說明： 【發明所屬之技術區域】 本發明係關於半導體裝置及其製造方法。 【先前技術】 以往之多晶片（multi-chip)半導體裝置已知者，例如， 如日本專利公開公報特開2002-3 6 8 1 84號所揭示那樣，在 導線框（lead frame)之島件上搭載多數之半導體晶片，將各 個半導體晶片與內部導線（lead)施予金屬線結合（wire bonding)，然後將這些被搭載之多數半導體晶片總括一體 施予塑模封裝（resin mold)。不過，這樣的半導體裝置因係 將多數之半導體晶片配列在一張之導線框上而行封裝 (pakaging)，故封裝面積大，另外，因係爲使用導線框藉金 屬線結合之方法，故價格也高。 另外，爲了縮小封裝面積，有如日本專利公開公報特 開2003 -273 3 2 1號所記載那樣，將裝設半導體晶片的多數 晶片基板結構體層疊在各個雙面電路基板之一面上，然後 藉加熱壓接方式等將其等總括一體作成積層構造者。另外 ，也有如日本專利公開公報特開200 1 -094046號所記載那 樣，在底板之上面中央部疊積搭載兩種裸晶片（bare chiP) ，將設於各裸晶片之上面周邊部之連接墊和設於底板上之 上面周邊部之連接墊，用結合引線連接者。這種情形’因 作成使下側之裸晶片能貫施金屬線結合’故上側之裸晶片 之尺寸係小於下側之裸晶片之尺寸，設在上側裸晶片之上 面周邊部之連接墊之配置位置’係比設在下側裸晶片之上 -6- 1278048 面周邊部之連接墊之配置位置位在內側。又，因在執行下 側之裸晶片之金屬線結合後才執行上側之裸晶片之金屬線 結合，故在底板之上面，下側之裸晶片用之連接墊係配置 在下側之裸晶片搭載區域之外側，而上側之裸晶片用之連 接墊則配置在下側之裸晶片用之連接墊之外側。 【發明內容】 (發明之揭示） (發明欲解決之課題） 日本專利公開公報特開2003 -273 3 2 1號記載之半導體 裝置係作成爲將搭載半導體晶片之各個雙面電路基板和形 成在各個雙面電路基板之導電連接端子重疊結合而成之構 造，因各電路基板厚且價昂，故整體也變成厚又價格高。 另外，因各層係藉結合（bonding)而重疊積層，故不易得出 不受環境變化之影響之可靠性之元件。日本專利公開公報 特開200 1 -094046號揭示之半導體裝置係作成爲下側之裸 晶片用之連接墊係配置在底板之上面，而上側之裸晶片用 之連接墊則配置在其等之外側，因此，半導體晶片之積層 數多時底板之面積也變大，從而半導體裝置整體之面積也 變大，又，配線之長度也變長之故，電阻値增大導致不適 用於高頻方面之用途。 因此，本發明之目的係提供能實現薄型化及安裝面積 縮小化，且能確保連接部在強度上之可靠性之半導體裝置 及其製造方法。 (解決課題之措施） -7- 1278048 依本發明，係提供一種半導體裝置’其特徵爲包含： 設在具有多數外部連接用電極（14)之第1半導體結構體（4) 和前述第1半導體結構體（4)周圍之絕緣材（16)、設在前述 第1半導體結構體（4)及前述絕緣材（16)之上面側之上層配 線構造（17, 20, 21，24)、設在前述第1半導體結構體（4)及 前述絕緣材（16)之下面側之下層配線構造（2，1，3，31，33, 34，37)、及至少搭載於前述上層配線構造（17，20，21，24) 上或前述下層配線構造（2, 1，3, 31，3 3, 3 4, 3 7)上之第2半 導體結構體（40, 71，77)。 另外，依本發明，係提供一種半導體裝置之製造方法 ，其特徵爲包括：藉底板（1)、絕緣材（16)及上層絕緣膜（17) 將各個具有多數之外部連接用電極之第1半導體結構體（4) 分別密封形成之工程、在前述上層絕緣膜（1 7)上形成上層 再配線（20)之工程、在前述底板（1)之下部形成下層再配線 (3 3)之工程、至少在前述上層再配線（20)上或下層再配線 (3 3)上搭載第2半導體結構體（40)之工程、及切斷前述底板 (1)、前述絕緣材（16)及前述上層絕緣膜（17)而得出多數個 具有至少一個前述第1半導體結構體（4)及至少一個前述第 2半導體結構體（40)之半導體裝置之工程。 (發明效果） 依本發明，係將具有多數之外部連接用電極之第1半 導體結構體搭載於底板上，周圍及上面分別包覆絕緣材及 上層絕緣膜而成密封狀態，在前述上層絕緣膜上設置上層 再配線，在前述底板上直接或隔介下層絕緣膜設置下層再 1278048 配線，至少在前述上層再配線或前述下層再配線上連接第 2半導體結構體而行安裝，因此能維持小的安裝面積之同 時更形薄型化，且能確保連接部在強度上之可靠性。 【實施方式】 (第1實施形態） 第1圖係表示本發明一個實施形態之半導體裝置之斷 面圖。該半導體裝置具備由玻璃布基材環氧樹脂（epoxy resin)等作成之平面矩形之底板1。在底板1名上面設置由 銅箔作成之上層配線2 ,，下面設置也是由銅范作成之下層 配線3。這種情形，上層配線2係爲由扁平圖案（pattern) 所形成之接地（ground)配線、，下層配屬„爲由扁平圖案所 形成之電、源配緣」 比底板1之尺寸小某程度之小尺寸平面矩形形狀之半 導體結構體4之下面，係隔介由晶片結合（die bond)材作成 之接著層5而接著於上層配線2之上面。這種情形，半導 體結構體4具有下述之再配線、柱狀電極、封止膜，一般 稱爲CSP(Chip size pakage :晶片規模封裝），尤其，如下 述那樣，用於採用在矽晶圓上形成再配線、柱狀電極、封 止膜後藉切割（dicing)而得出各個半導體結構體4之方法， 特別是，也稱爲晶圓層級CSP(Wafer level CSPKSP)。 下面將說明半導體結構體4之結構。 半導體結構體4具備矽基板（半導體基板）6。矽基板6 係隔介接著層5而接著於底板1。在矽基板6之上面配置 具有既定功能（例如CPU之功能）之積體電路（未圖示），另 1278048 在上面周邊部上連接有由|g (aluminium)系金屬等作成之多 數連接墊7俾與積體電路連接。在連接墊7之中央部除外 之砂基板6的上面設有由氧化砂（s i 1丨c 〇 n 〇 X丨d e)等作成之絕 緣膜8，連接墊7之中央部係經設在絕緣膜8上之開口部9 而露出。 在絕緣膜 8之上面設置由環氧系樹脂、聚醯亞胺 (polyimide)系樹脂等作成之保護膜（絕緣膜）1()。這種情形 ，保護膜1 0上對應絕緣膜8之開口部9之部分設有開口部 11。在保護膜10之上面設有由銅等作成之基底金屬層12 。在基底金屬層1 2之上面整面設有由銅作成之再配線1 3 。包含基底金屬層1 2之再配線1 3之一個端部係透過兩開 口部9，1 1而接於連接墊7。 再配線1 3之連接墊部上面設有由銅作成之柱狀電極 (外部連接用電極）14。各柱狀電極14之高度係爲60〜150 # m。由環氧系樹脂、聚醯亞胺糸樹脂作成之封止膜（絕緣 膜）1 5係以其上面與柱狀電極1 4之上面齊平那樣，設在包 含再配線1 3的保護膜1 0上面。這樣子，稱爲W - C S P之半 導體結構體4係包含矽基板6、連接墊7、絕緣膜8，另外 也包含保護膜1 〇、再配線1 3、柱狀電極1 4、封止膜1 5而 組成者。 矩形框狀之絕緣層1 6係以其上面幾乎與半導體結構 體4之上面齊平那樣，設置在底板1之上面，該底板包含 半導體結構體4之周圍的上層配線2。絕緣層1 6係由，例 如，熱硬化性樹脂，或將玻璃纖維、矽塡料等之補強材分 -10- 1278048 散在熱硬化性樹脂中之物質所形成。 在半導體結構體4及絕緣層1 6之上面設置上面形成 坦之第1上層絕緣膜17。第1上層絕緣膜1 7係用於增 (build-up)基板上之通常稱爲增強材者，例如，將纖維、 料等之補強材分散在環氧系樹脂、BT樹脂等之熱硬化性 脂中之物質。這種情形，纖維係爲玻璃纖維、芳香族醯 (ar am id)纖維等。塡料係爲氧化矽塡料、陶瓷系塡料等。 在第1上層絕緣膜1 7上對應柱狀電極1 4之上面中 部之部分設有開口部1 8。在第1上層絕緣膜1 7之上面 有銅等作成之第丨上層基底金屬層19。在第1上層基底 屬層1 9之上面整面設有由銅作成之第1上層再配線2 0 包含第1上層基底金屬層19的第1上層再配線20之一 端部，係經第1上層絕緣膜1 7之開口部1 8而接於柱狀 極1 4之上面。 在包含第1上層再配線2 0的第1上層絕緣膜1 7之 面，設有與第1上層絕緣膜1 7相同之材料所作成之第2 層絕緣膜21。在第2上層絕緣膜21上對應第1上層再 線20之連接墊之至少一部分的部分上設有開口部22。 第2上層絕緣膜21之上面設有由銅等作成之第2上層基 金屬層23。在第2上層基底金屬層23之上面整面設有 銅作成之第2上層再配線24。包含第2上層基底金屬層 的第2上層再配線24之至少一部分之一個端部，係經第 上層絕緣膜2 1之開口部22而接於第1上層再配線20之 接墊部。 在包含第2上層再配線24的第2上層絕緣膜2 1之 平 強 塡 樹 胺 央 設 金 〇 個 電 上 上 配 在 底 由 23 ；2 連 上 -11- 1278048 面’設有由ί几焊料劑（s 〇 1 d e r r e s i s t)等作成之最上層絕緣膜 2 5。在最上層絕緣膜2 5上對應第2上層再配線24之連接 墊部之部分上設有開口部26。在開口部26內及其上方設 有焊錫球27並與第2上層再配線24之連接墊部連接。多 數之焊錫球27係在最上層絕緣膜25上配置成矩陣狀。 在包含下層配線3的基板1之下面，設有由與第1上 層絕緣膜1 7相同之材料作成，下面呈平坦之第1下層絕緣 膜31。在第1下層絕緣膜31之下面設有由銅等作成之第1 下層基底金屬層32。在第1下層基底金屬層32之下面整 面設有由銅作成之第1下層再配線3 3。 在包含第1下層再配線3 3的第1下層絕緣膜3 1之下 面，設有與第1上層絕緣膜1 7相同材料作成之第2下層絕 緣膜3 4。在第2下層絕緣膜3 4對應第1下層再配線3 3之 連接墊部之部分上設有開口部3 5。在第2下層絕緣膜3 4 之下面設有由銅等作成之第2下層基底金屬層36。在第2 下層基底金屬層36之下面整面設有由銅作成之第2下層再 配線37。在包含第2下層基底金屬層36的第2下層再配 線3 7之至少一部分之一個端部，係透過第2下層絕緣膜 3 4之開口部3 5而接於第1下層再配線3 3之連接墊部。 在包含第2下層再配線37的第2下層絕緣膜34之下 面，設有由抗焊料劑等作成之最下層絕緣膜3 8。在最下層 絕緣膜3 8對應第2下層再配線3 7之連接墊部之部分上設 有開口部3 9。多數之半導體結構體4 0係以設在其上面之 焊錫球4 1經最下層絕緣膜3 8之開口部3 9接於第2下層再 -12- 1278048 配線3 7之連接墊部而被安裝在最下層絕緣膜3 8之下面。 半導體結構體40雖未詳細圖示，但裸晶片、BGA(ball grid array :球格陣列）、CSP等皆可’係作成爲在由矽等作 成之半導體基板之上面設置既定功能（例如半導體記憶體 功能）之積體電路，在上面周邊部設置由鋁系金屬等作成之 多數連接墊並與各個積體電路連接’在由連接墊本身或接 於該連接墊之柱狀電極等作成之外部連接用電極上設置焊 錫球4 1之構造。 包含第1上層絕緣膜1 7、絕緣層1 6、上層配線2及下 層配線3的底板1，包含第1下層絕緣膜3 1、設在第1圖 上未示出之位置上之第1下層基底金屬層32的第1下層再 配線33及第2下層絕緣膜34之既定地點，係被貫通孔42 貫通，另外，包含第2上層基底金屬層23之第2上層再配 線24，包含第1上層基底金屬層1 9之第1上層再配線2 0 、上層配線2或下層配線3、包含第2下層基底金屬層3 6 之第2下層再配線3 7，係藉由設在貫通孔42之內壁面上 之銅等作成之基底金屬層43a和銅層43b作成之上下導通 部4 3而連接在一起。這裡，上層配線2係接在第2圖左側 之上下導通部4 3，下層配線3則接在第2圖右側之上下導 通部4 3。 這種情形爲了使上下配線之電性導通良好，於上下導 通部43內充塡銅糊（paste)、銀糊，由導電性樹脂等作成之 導電材44，但也可充塡絕緣樹脂，或者也可留空不充塡任 何材料。 -13- 1278048 這裡，茲舉一例，半導體結構體4之接地用之柱狀電 極1 4係經第1上層再配線2 0及上下導通部4 3而接於組成 接地配線之上層配線2。半導體結構體4之電源用之柱狀 電極1 4係經第1上層再配線20及上下導通部43而接於組 成電源配線之下層配線3。 半導體結構體40之接地用之焊錫球4 1係經第2下層 再配線3 7及上下導通部43而接於組成接地配線之上層配 線2。半導體結構體4 0之電源用焊錫球41係經第2下層 再配線3 7及上下導通部43而接於組成電源配線之下層配 線3 〇 半導體結構體4之信號用之柱狀電極1 4和半導體結構 體40之信號用之焊錫球41，係經第1上層再配線20、上下 導通部43、第1下層再配線33及第2下層再配線37而連 接。然後，接地配線連接至接地用焊錫球27，電源配線接 至電源用之焊錫球2 7，信號配線接至信號用之焊錫球2 7。 半導體裝置各部之厚度尺寸之一例如下：矽基板6係 爲0.1〜0.35mm、柱狀電極14係爲0.06〜0.15mm、半導體 結構體4整體係爲〇 . 2 5〜0 · 5 mm、從第1上層絕緣膜1 7〜 最上層絕緣膜25止合計係爲0.2〜0.25mm、從底板1到最 下層絕緣膜38止合計係爲0.25〜0.3mm、半導體結構體40 係爲〇.25mm〜0.3mm、及整體之厚度係爲1.0〜1.2mm。 但是，底板1之尺寸作成比半導體結構體4之尺寸大 某程度之理由，係因對應矽基板6上之連接墊7之數量之 增加，而將焊錫球27之配置區域作成比半導體結構體4之 -14- 1278048 尺寸大某程度，因爲如此’故將第2上層再配線2 4之連接 墊部（最上層絕緣膜25之開口部26內之部分）之尺寸及間 距（pitch)作成比柱狀電極14之尺寸及間距大。 因此之故，配置成矩陣狀之第2上層再配線24之連接 墊部不僅配置在對應半導體結構體4之區域，也配置在對 應設在半導體結構體4之周邊側面之外側的絕緣層1 6之區 域上。即，在配置成矩陣狀之焊錫球27之中’至少最外周 之焊錫球2 7係配置在比半導體結構體4較靠外側之位置之 周圍。 另外，該半導體裝置，在上下面上設有在具有上層配 線2及下層配線3之底板1上組成CPU之半導體結構體4 ，在底板θ設有組成半導體記憶體之多數半導體結構體 40，因此即便具備功能不同之半導體結構體4, 40，也能縮 小安裝面積。又，在底板1之上下面設有由銅箔作成之上 層配線2及下層配線3，因此相較於藉增強這些配線2, 3 之工程而形成之情形，能減少工程量。 其次，在說明該半導體裝置之製造方法之一例前先說 明半導體結構體4之製造方法之一例。這種情形，首先， 如第2圖所示，在晶圓狀態之矽基板（半導體基板）6上設置 由鋁系金屬等作成之連接墊7，由氧化矽等作成之絕緣膜8 及由環氧系樹脂、聚醯亞胺系樹脂等作成之保護膜1 0，連 接墊7之中央部係爲經形成在絕緣膜8及保護膜1 0上之開 口部9及1 1而露出之構件。上述之情形係在晶圓狀態之矽 基板6上，於各半導體結構體形成之區域上形成具有既定 -15- 1278048 功能之積體電路，連接墊7係分別與形成在對應區域上之 積體電路行電性之連接。. 接著，如第3圖所示，在包含經兩開口部9，11露出之 連接墊7之上面的保護膜10之上面，整面形成基底金屬層 1 2。這種情形，基底金屬層1 2也可只係爲藉無電解電鍍形 成之銅層，且也可只係爲藉濺鍍（sputter)形成之銅層’更 甚者，也可係爲在藉濺鍍形成之鈦（titan)等之薄膜層上藉 灘鍍形成之銅層。 接著，在基底金屬層12之上面形成抗電鍍（plate-resist) 膜5 1之圖案（pattern)。這種情形，在抗電鍍膜5 1對應再 配線1 3形成區域之部分上形成開口部52。然後，以基底 金屬層1 2爲電鍍電流路而執行銅之電解電鍍，藉此，在抗 電鍍膜51之開口部52內的基底金屬層12之上面形成再配 線1 3。然後，剝離抗電鍍膜5 1。 接著，如第4圖所示，在包含再配線1 3之基底金屬層 1 2之上面形成抗電鍍膜5 3之圖案。這種情形，在抗電鍍 膜5 3對應形成柱狀電極1 4之區域之部分上形成開口部5 4 。然後，以基底金屬層1 2作爲電鍍電流路執行銅之電解電 鍍，藉此，在抗電鍍膜5 3之開口部5 4內之再配線1 3之連 接墊部上面形成柱狀電極1 4。然後，剝離抗電鍍膜5 3，接 著，以再配線1 3作遮罩（mask)對基底金屬層1 2之不要部 分進行蝕刻（e t c h i n g)而予以去除後則，如第5圖所示，僅 在再配線1 3下面殘存基底金屬層1 2。 接著，如第6圖所示，藉絲網（screen)印刷法、旋轉塗 -16- 1278048 佈（spin-coating)法、連續式模塗法（die-coat)等，在保護膜 1 〇，包含柱狀電極1 4及再配線1 3之上面整面形成環氧系 樹脂、聚醯亞胺系樹脂等作成之封止膜1 5，該封止膜15 之厚度係形成比柱狀電極1 4之高度高。因此，在這種狀態 下，柱狀電極1 4之上面係被封止膜1 5包覆。 接著，適宜地硏磨封止膜1 5及柱狀電極1 4之上面側 ，如第7圖所示，使柱狀電極1 4之上面露出，且平坦化包 含該露出之柱狀電極14之上面的封止膜15之上面。這裡 ，適宜地硏磨柱狀電極1 4之上面側之理由係因藉電解電鍍 形成之柱狀電極1 4之高度不均，爲了消除該不均而使柱狀 電極14之高度均一之故。 接著，如第8圖所示，在矽基板6之下面整面接著接 著層5。接著層5係由環氧系樹脂、聚醯亞胺系樹脂等之 晶片結合（die-bond)材作成，藉加熱加壓，以半硬化狀態固 著於矽基板6上。其次，將固著於矽基板6之接著層6黏 貼在切割膠帶（dicing tape)(未圖示）上，經第9圖所示之切 割工程後自切割膠帶剝離後則，如第1圖所示，得出多個 在矽基板6之下面具有接著層5之半導體結構體4。 這樣子得出之半導體結構體4因在矽基板6之下面具 有接著層5之故，在切割工程後不需要進行在各個半導體 結構體4之矽基板6之下面分別設置接著層之極爲麻煩之 作業。另外，在切割工程後從切割膠帶剝離之作業相較於 在切割工程後分別在各半導體結構體4之矽基板6之下面 設置接著層之作業係極爲簡單。 -17- 1278048 下面將使用這樣子得出之半導體結構體4，說明製造 第1圖所示之半導體裝置之情形之一例。首先，如第1 〇圖 所示，大小爲可採用多數第1圖所示之基板1，雖無限定 之意，但製作平面形狀係爲矩形形狀之底板1。這種情形 ，在底板1之上下面上初始即有積層銅箔，但藉光刻法 (photolithography)將這些銅箔圖案化（patterning)，而形成 上層配線2及下層配線3。 接著，將接著在各個半導體結構體4之矽基板6之下 面的接著層5，接著於底板1之上面之既定之多數地點。 這裡所提之接著係指加熱加壓使接著層5真正硬化。然後 ’在半導體結構體4之間及配置在最外周之半導體結構體 4之外側之底板1上面，藉例如，絲網印刷法或旋轉塗佈 法等形成第1絕緣材料1 6 a，另在其上面配置薄片狀之第2 絕緣材料1 7a。又，在底板1之下面配置薄片狀之第3絕 緣材料3 1 a。 第1絕緣材料1 6 a係爲，例如，在熱硬化性樹脂，或 者’在熱硬化性樹脂中分散玻璃纖維、二氧化矽塡料等之 補強材者。薄片狀之第2、第3絕緣材料1 7 a、3 1 a雖非限 疋之意’但最好是爲增強材，作爲這種增強材有在環氧系 樹脂、BT樹脂等之熱硬化性樹脂中混入二氧化矽塡料，並 使熱硬化性樹脂成半硬化狀態者。不過，第2、第3絕緣 材料1 7a、3 1 a也能在玻璃纖維中含浸環氧系樹脂等之熱硬 化性樹脂，使熱硬化性樹脂成半硬化狀態而形成薄片狀之 預漬（prepreg)材或者不混入塡料（fiuer)而僅使用由熱硬 1278048 化性樹脂作成之材料。 接著，使用第1 1圖所示之一對加熱加壓板5 5，5 6，對 第1〜第3之絕緣材料16a，17a，31a進行加熱加壓。結果 ，在配置於半導體結構體4之間及最外周之半導體結構體 4之外側中，於底板1之上面形成絕緣層1 6，在半導體結 構體4及絕緣層1 6之上面形成第1上層絕緣膜1 7，在底 板1之下面形成第1下層絕緣膜3 1。 這種情形，第1上層絕緣膜1 7之上面因被上側之加熱 加壓板55之下面壓接之故而成平坦面。另外，第1下層絕 緣膜3 1之下面因被下側之加熱加壓板5 6之上面壓接之故 而成平坦面。因此，不需要爲了平坦化第1上層絕緣膜1 7 之上面及第1下層絕緣膜3 1之下面而進行硏磨工程。因此 之故，即使底板1之尺寸例如，係爲5 00x500mm程度之較 大之情形，也能對配置在其上之多數半導體結構體4，包 括第1上層絕緣膜1 7之上面及第1下層絕緣膜3 1之下面 ，一體簡單地進行平坦化。 接著，如第1 2圖所示，藉照射雷射光束以行雷射加工 ，在第1上層絕緣膜17對應柱狀電極14之上面中央部之 部分上形成開口部1 8。這種情形，在第1下層絕緣膜3 1 上不形成開口部。然後’視需要’藉去塗污（de-smear)處理 將在第1上層絕緣膜1 7之開口部1 8內等產生之環氧塗污 (smear)去除。 接著，如第13圖所示’藉銅之無電解電鍍等，在包含 經開口部1 8露出之柱狀電極1 4之上面的第1上層絕緣膜 -19- 1278048 17之上面整面，及第1下層絕緣膜31之下面整面，形成 第1上層基底金屬層19及第1下層基底金屬層32。然後 ，在第1上層基底金屬層19之上面形成上層抗電鍍膜61 圖案，另外，在第1下層基底金屬層32之下面形成下層抗 電鍍膜62圖案。這種情形，上層抗電鍍膜61對應第1上 層再配線2 0之形成區域之部分上形成開口部6 3。另外， 在下層抗電鍍膜62對應第1下層再配線3 3之形成區域之 部分上形成開口部64。 接著，將基底金屬層1 9、3 2作爲電鍍電流路以進行銅 之電解電鑛，藉此，在上層抗電鍍膜61之開口部63內的 第1上層基底金屬層19之上面，形成第1上層再配線20 ，另外，在下層抗電鍍膜62之開口部64內的第1下層基 底金屬層3 2之下面形成第1下層再配線3 3。 接著，剝離兩抗電鍍膜6 1、62，然後將第1上層再配 線20及第1下層再配線33作爲遮罩（mask)進行蝕刻，以 去除第1上層基底金屬層19及第1下層基底金屬層32之 不要部分，結果，如第14圖所示，只在第1上層再配線 20下面殘存第1上層基底金屬層19,另外，只在第1下層 再配線3 3上面殘存第1下層基底金屬層3 2。 接著，如第15圖所示，藉絲網印刷（screen-print)法、 旋轉塗佈（spin-coating)法、連續式模塗（die-coat)法等，在 包含第1上層再配線20的第1上層絕緣膜17之上面，形 成第2上層絕緣膜2 1，另外，在包含第1下層再配線3 3 的第1下層絕緣膜3 1之下面，形成第2下層絕緣膜3 4。 -20- 1278048 第2上層絕緣膜2 1及第2下層絕緣膜3 4之材料雖能使用 與第1上層絕緣膜1 7相同之材料，但對有關第1上層絕緣 膜1 7，記載之材料中也可使用與第1上層絕緣膜1 7不同 之材料形成。 接著，如第1 6圖所示，照射雷射光束以行雷射加工， 藉此在第2上層絕緣膜2 1對應第1上層再配線2 0之連接 墊部之至少一部分之部分上形成第2開口部22，另外，在 第2下層絕緣膜3 4對應第1下層再配線3 3之連接墊部之 至少一部分之部分上形成開口部3 5。 接著，使用機械鑽孔（mechamical drill)，或藉照射C02 雷射光束之雷射加工，或者打洞（Punching)等，在第2上層 絕緣膜21、包含第1上層基底金屬層19的第1上層再配 線20、第1上層絕緣膜1 7、絕緣層16、包含上層配線2 或下層配線3的底板1、第1下層絕緣膜3 1、包含設在第 16圖上未示出之位置上之第1下層基底金屬層32的第1 下層再配線3 3、及第2下層絕緣膜3 4之既定地點上，形 成貫通孔42。然後，視需要，藉去塗污處理去除在開口部 22、35內及貫通孔42內產生之環氧塗污等。 接著，如第17圖所示，藉銅之無電解電鍍等，在第2 上層絕緣膜2 1上面整面，包含經開口部22露出之第1上 層再配線20之連接墊部，在第2下層絕緣膜34之下面整 面，包含經開口部3 5露出之第1下層再配線3 3之連接墊 部，整面及貫通孔42之內壁面上，形成第2上層基底金屬 層23、第2下層基底金爵層36及基底金屬層43a。 -21- 1278048 接著，在第2上層基底金屬層23之上面形成上層抗電 鍍膜65之圖案，另外，在第2下層基底金屬層36之下面 形成下層抗電鍍膜66之圖案。這種情形，在上層抗電鍍膜 65對應包含貫通孔42的第2上層再配線24之形成區域部 分上，形成開口部67。在下層抗電鍍膜66對應包含貫通 孔42的第2下層再配線3 7之形成區域之部分上，形成開 口部 6 8。 接著，將基底金屬層23、36、43a作爲電鍍電流路以 進行銅之電解電鍍，藉此，在上層抗電鍍膜65之開口部 67內的第2上層基底金屬層23之上面，形成第2上層再 配線24，另外，在下層抗電鍍膜66之開口部68內的第2 下層基底金屬層36之下面，形成第2下層再配線37，再 者，在貫通孔42內之基底金屬層43a之表面上形成銅層 43b ° 接著，剝離兩抗電鍍膜65、66，然後將第2上層再配 線24及第2下層再配線37作爲遮罩（mask)，藉蝕刻將第2 上層基底金屬層23及第2下層基底金屬層36之不要的部 分去除，結果，如第1 8圖所示，只在第2上層再配線24 之下面殘存第2上層基底金屬層23，另外，只在第2下層 再配線37上面殘存第2下層基底金屬層36。 半導體結構體4之信號用柱狀電極1 4和半導體結構體 40之信號用焊錫球41，係透過第1上層再配線20、上下 導通部4 3、第1下層再配線3 3及第2下層再配線3 7而連 接。 -22- 1278048 接著，如第1 9圖所示，藉絲網印刷法在上下導通部 43內充塡由銅糊、銀糊、導電性樹脂等作成之導電材44 。然後，視需要’藉拋光布（buff)硏磨等除去從貫通孔42 突出之多餘之導電材4 4。接著，藉絲網印刷法、旋轉塗佈 法等在第2上層絕緣膜2 1之上面，包含第2上層再配線 24，形成由抗焊料劑等作成之最上層絕緣膜25。這種情形 ，在最上層絕緣膜2 5對應第2上層再配線2 4之連接墊部 之部分上，形成開口部2 6。 接著，藉絲網印刷法、旋轉塗佈法等在第2下層絕緣 膜3 4之下面，包含第2下層再配線3 7，形成由抗焊料劑 所作成之最下層絕緣膜3 8。這種情形，在最下層絕緣膜3 8 對應第2下層再配線3 7之連接墊部之部分上，形成開口部 39 ° 接著，將設在多數半導體結構體40之上面之焊錫球 4 1，經最下層絕緣膜3 8之開口部3 7，接至第2下層再配 線37之連接墊部，如此將多數半導體結構體40安裝在最 下層絕緣膜3 8之下面。然後，在開口部26內及其上方形 成焊錫球2 7並使其與第2上層再配線24之連接墊部連接 。最後，在相互鄰接之半導體結構體4之間切斷最上層絕 緣膜25、第2上層絕緣膜21、第1上層絕緣膜1 7、絕緣 層1 6、底板1、第1下層絕緣膜21、第2下層絕緣膜3 4 及最下層絕緣膜3 8，即得出多數個第1圖所示之半導體裝 置。 於此狀態，作爲一例，半導體結構體4之接地用柱狀 -23- 1278048 電極1 4係經第1上層再配線2 0及上下導通部4 3而與組成 接地配線之上層配線2連接。半導體結構體4之電源用柱 狀電極1 4係經第1上層再配線20及上下導通部43而與組 成電源配線之下層配線3連接。 ， 半導體結構體4 0之接地用之焊錫球4 1係經第2下層 、 再配線3 7及上下導通部43而與組成接地配線之上層配線 2連接。半導體結構體40之電源用焊錫球4 1係經第2下 層再配線3 7及上下導通部4 3而與組成電源配線之下層配 線3連接。 如上述，上述之製造方法係對配置在底板1上之多數 半導體結構體4總括一起形成上層配線2、下層配線3、第 1、第2上層再配線20、24、第1、第2下層再配線33、 37、上下導通部43及焊錫球27，然後予以分開而得出多 數個半導體裝置，因此能簡化製造工程。這時，各絕緣膜 、 及再配線係密接積層而成，因此，相較於以往者，能大幅 地薄型化整體之厚度。 另外，第11圖所示之製造工程之後，因能將底板1和 ® 多數之半導體結構體4 一起運送，故因此也能簡化製造工 程。另外，電極與再配線，再配線與再配線因係藉電鍍而 連接’故相較於藉熱壓接之方法，能確保在強度上之可靠 性。這種情形，柱狀電極14和第1上層再配線20之連接 ，柱狀電極1 4因具有〇 . 1 mm程度之高度，即使因環境條 件之變化，矽基板6與電路基板（未圖示）因熱膨脹係數之 不相同而產生應力之情形，也能在水平方向上搖動，進而 -24- 1278048 能緩和應力之集中。 再者，上述實施形態係針對將上層配線2作爲由扁平 圖案作成之接地配線，將下層配線3作爲由扁平圖案作成 之電源配線之情形說明，但並不限定這樣，也可作成相反 之情形。另外，也可藉上層配線2或下層配線3形成由扁 平圖案作成之遮蔽層，另外，也可形成通常之配線圖案。 另外，上述實施形態係針對藉半導體結構體4之矽基 板6組成CPU之情形說明，但並非限定於這種情形。例如 ，也可使用半導體結構體4之矽基板6，在矽基板上形成 絕緣膜，然後再在其上形成薄膜電晶體而組成SOI(Sil icon on insulator:絕緣矽）。這種情形，也可將上層配線2作爲 藉扁平圖案作成之接地配線，將接著層5作爲導電性接著 層，進而在矽基板上藉組成配線圖案和接地配線之上層配 線2而形成微波帶狀線（micro strip line)結構。 另外，上述實施形態係針對上層再配線及下層再配線 皆作成二層之情形說明，但並不限定於這種情形，也可作 成一層或三層以上，另外，也可作成不同數目之層。更甚 者，也可在最下層絕緣膜38之下部安裝由電容器、電阻器 等作成之晶片零件。 再者，上述實施形態，搭載在底板1上之半導體結構 體4係作成面朝上（face-up)之安裝，但也能在底板1上設 置焊墊部而作成面朝下（face-down)之安裝。另外，半導體 結構體40係安裝在屬於底板1之下面側之最下層之第2下 層再配線37上，但半導體結構體40也可僅安裝在屬於最 -25- 1278048 上層之第2上層再配線2 4上，或安裝在第2下層再配線 37上面及第2上層再配線24上面之兩面上。另外，半導 體結構體40若是安裝在底板1之下面側之情形’係設置第 2下層絕緣膜3 4、第2下層再配線3 7，然後，將半導體結 構體4 0結合於該第2下層再配線3 7，但也可在底板1之 下面設置下層再配線，將半導體結構體40安裝於該下層再 配線上。另外，半導體結構體40係作成面朝下之安裝，但 也能作成爲面朝上之封裝，以下將舉其一例當作第2實施 形態。 (第2實施形態） 第2 0圖所示之第2實施形態係與第1圖所示之第1實 施形態不同，安裝在第2下層再配線3 7上之第1半導體結 構體7 1及第2半導體結構體77係作成爲面朝上之安裝。 下面將主要說明第2實施形態之結構與第1實施形態不同 之點，與第1實施形態相同之結構附加相同之參考符號表 示，其說明則省略。 包含第2下層基底金屬層36之第2下層再配線37, 係與第1實施形態之情形相同地形成在第2下層絕緣膜3 4 之下面，但其圖案形狀係對應下述之第1外部半導體結構 體7 1及第2外部半導體結構體77之結合位置者。 在包含第2下層再配線3 7的第2下層絕緣膜3 4下面 ，設置由抗焊料劑等作成之最下層絕緣膜3 8。在最下層絕 緣膜3 8對應第2下層再配線3 7之連接墊部之部分上設有 開口部3 9。在開口部3 9內之第2下層再配線3 7之連接墊 -26- 1278048 部下面，設置由金作成之第1、第2表面處理層70a、70b 。這種情形，第1表面處理層7 0 a係配置在下述之第1外 部半導體結構體71之搭載區域之周圍，且在其周圍配置第 2表面處理層70b。 平面矩形形狀之第1外部半導體結構體7 1之下面係透 過由晶片結合（die bond)材作成之接著層72而接著於最下 層絕緣膜3 8之下面中央部。第1外部半導體結構體7 1通 常係稱爲裸晶片（bare chip)，在矽基板（半導體基板）73之 主面（第20圖之下面）之中央區域上設有積體電路，在該積 體電路之周邊部上設有由鋁系金屬等作成之多數連接墊74 並與積體電路連接，作成爲除掉連接墊74之中央部外，其 它部分皆被由氧化矽等作成之絕緣膜75包覆之結構。然後 ，第1外部半導體結構體7 1之連接墊74則透過由金作成 之第1結合引線（bonding wire)7 6而與第1表面處理層70a 連接。 平面矩形形狀之第2外部半導體結構體77之下面，係 透過由晶片結合材作成之接著層7 8而接著於第1外部半導 體結構體7 1之下面中央部。第2外部半導體結構體7 7係 與第1外部半導體結構體7 1相同地，通常被稱爲裸晶片者 ，其尺寸係只比第1外部半導體結構體7 1之尺寸小某一程 度，其它基本之結構係爲與第1外部半導體結構體7 1相同 ，因此省略其之詳細說明。至於，第2外部半導體結構體 77連接墊79係透過由金作成之第2結合引線8〇而與第2 表面處理層7 0 b連接。在包含第1、第2外部半導體結構 1278048 體71、77及第1、第2結合引線76、80之最下層絕緣膜 38之下面中央部，設有由環氧系樹脂、聚醯亞胺系樹脂等 作成之封止材8 1。 包含第2上層基底金屬層23之第2上層再配線24之 至少一部分，和包含第2下層基底金屬層36之第2下層再 配線3 7之至少一部分，係經設在第2上層絕緣膜2 1，包 含第1上層基底金屬層19之第1上層再配線20、第1上 層絕緣膜1 7、絕緣層1 6、包含上層配線2或下層配線3之 φ 底板1、包含第1下層絕緣膜31、第1下層基底金屬層32 之第1下層再配線3 3及第2下層絕緣膜3 4之特定處的貫 通孔42之內壁面上，由銅等作成之基底金屬層43 a和由銅 層43b作成之上下導通部43而連接。 · 這種情形，爲了使上下配線之電性導通良好，在上下 ~ 導通部4 3內充塡有銅糊、銀糊、由導電性樹脂等作成之導 電材44，但也可充塡絕緣性樹脂，另外，也可係爲不充塡 任何材料之空孔。 Φ 這裡，作爲一個例子，半導體結構體4之接地用柱狀 電極1 4係經第1上層再配線20及上下導通部43而接於組 成接地配線之上層配線2。半導體結構體4之電源用之柱 狀電極14係經第1上層再配線20及上下導通部43而接於 組成電源配線之下層配線3。 第1、第2之外部半導體結構體7 1、77之接地用之連 接墊74、79係經第2下層再配線37及上下導通部43而接 -28- 1278048 於組成接地配線之上層配線2。第1、第2之外部半導體結 構體71、77之電源用之連接墊74、79係經第2下層再配 線3 7及上下導通部43而接於組成電源配線之下層配線3 〇 半導體結構體4之信號用柱狀電極1 4和第1、第2外 部半導體結構體7 1、7 7之信號用之連接墊7 4、7 9係經第 1上層再配線20、上下導通部43、第1下層再配線33及 第2下層再配線3 7而連接。然後，接地配線接於接地用焊 錫球27、電源配線接於電源用之焊錫球27、信號配線接於 信號用之焊錫球27。 但是，底板1之尺寸作成比半導體結構體4之尺寸大 某一程度之理由係對應矽基板6上連接墊7之數量之增加 ，而將焊錫球2 7之配置區域作成比半導體結構體4之尺寸 大某一程度，藉此，第2上層再配線24之連接墊部（最上 層絕緣膜25之開口部26內之部分）之尺寸及間距也作成比 柱狀電極1 4之尺寸及間距大之故。 因此之故，配置成矩陣狀之第2上層再配線24之連接 墊部不只是配置於對應半導體結構體4之區域，也配置在 對應設在半導體結構體4之周側面之外側之絕緣層1 6上。 亦即，在配置成矩陣狀之焊錫球27中至少最外周之焊錫球 27係配置在位於比半導體結構體4之更外側位置之周圍。 另外，該半導體裝置，在底板1之下面設有第1、第2 下層再配線33、37，第1、第2上層再配線20、24之至少 一部分和第1、第2下層再配線3 3、3 7之至少一部分係經 •29- 1278048 上下導通部4 3而連接，因此，能將第1、第2外部半導體 結構體7 1、7 7積層搭載於最下層絕緣膜3 8之下面。然而 ，這種情形，與整體上實質地積層三個半導體結構體4、 7 1、7 7無關，因只有第1、第2外部半導體結構體71、7 7 行金屬線結合，故對於積層三個半導體結構體且全部行金 屬線結合之結構，最上段可省掉與外部半導體結構體行金 屬線結合，從而能抑制底板1之面積之增大，另外’能降 低電阻値。 下面將說明該半導體裝置之製造方法之一例。藉第1 實施形態上說明之方法作成第1 8圖所示之狀態。 爾後，如第2 1圖所示那樣，藉絲網印刷法等，在上下 導通部4 3內充塡銅糊、銀糊、由導電性樹脂等作成之導電 材44。接著，視需要，藉拋光布硏磨等除去從貫通孔42 突出之多餘之導電材44。然後，藉絲網印刷法、旋轉塗佈 法等在包含第2上層再配線2 4之第2上層絕緣膜2 1上面 ，形成由抗焊料劑等作成之最上層絕緣膜25。 另外，藉絲網印刷法、旋轉塗佈法等在包含第2下層 再配線3 4之第2下層絕緣膜3 4下面，形成由抗焊料劑等 作成之最下層絕緣膜3 8。這種情形，在最下層絕緣膜3 8 對應第2下層再配線3 7之連接墊部之部分上形成開口部 3 9，再者，這時，在最上層絕緣膜25對應第2上層再配線 24之連接墊部之部分上則形成開口部26。 這裡’包含第2上層基底金屬層23之第2上層再配線 24係完全分離。相對於此，包含第2下層基底金屬層36 -30- 1278048 _ 之第2下層再配線3 7則不完全分離，而是與形成於下述之 切斷線（相當於切割線）區域之電鍍電流路（未圖示）連接。這 裡，將最下層絕緣膜3 8作爲遮罩進行金的電解電鍍後即， 如第22圖所示那樣，在開口部39內之第2下層再配線37 之下面形成第1、第2表面處理層70a、70b。 接著，如第2 3圖所示那樣，在最上層絕緣膜2 5對應 第2上層再配線24之連接墊部之部分上形成開口部26。 其次，如第24圖所示，將第1外部半導體結構體71之接 著層72接著在最下層絕緣膜3 8之下面中央部，接著，將 β 第2外部半導體結構體77之接著層78接著於第1外部半 導體結構體7 1之下面中央部。其次，將第1外部半導體結 構體71之連接墊74和第1表面處理層70a透過由金作成 之第1結合引線7 6而連接。其次，將2外部半導體結構體 · 77之連接墊79和第2表面處理層70b透過由金作成之第2 結合引線80而連接。 另外，也可將第1外部半導體結構體7 1之接著層72 接著於最下層絕緣膜3 8之下面中央部，其次將第1外部半 ® 導體結構體71之連接墊74和第1表面處理層70a透過第 1結合引線連接，接著，將第2外部半導體結構體77之接 著層78接著於第1外部半導體結構體71之下面中央部， 其次，將第2外部半導體結構體77之連接墊79和第2表 面處理層70b透過第2結合引線80連接。 接著，藉金屬線結合法、絲網印刷法等，在包含第1 、第2外部半導體結構體71、77及第1、第2結合引線76 -31- 1278048 、80之最下層絕緣膜38下面，形成由環氧系樹脂、聚醯 亞胺系樹脂等作成之封止材8 1。其次’在開口部26內及 其上方形成焊錫球2 7並與第2上層再配線24之連接墊部 連接。最後，在相互接鄰之半導體結構體4之間切斷最上 層絕緣膜2 5、第2上層絕緣膜2 1、第1上層絕緣膜1 7、 絕緣層1 6、底板1、第1下層絕緣膜3 1、第2下層絕緣膜 34及最下層絕緣膜38後可得出多數個第20圖所示之半導 體裝置。 這種情形，依上述之切斷線切斷時，包含第2下層基 底金屬層36之第2下層再配線37因與形成在該切斷線區 域上之電鍍電流路分離，故包含第2下層基底金屬層36之 第2下層再配線37則完全分離。這裡，表面處理層70a、 7 〇b用電解電鍍形成，而不是無電解電鍍’理由係表面處 理層70a、70b之厚度若藉無電解電鍍時會較薄，藉電解電 鍍時則會較厚，表面處理層7〇a、70b之厚度若較薄時藉金 屬線結合作成之接合容易產生不良，相對於此，表面處理 層70a、70b之厚度若較厚時能使藉金屬線結合作成之接合 不易產生接合不良之故。 (第3實施形態） 第2 5圖係表示本發明之第3實施形態之半導體裝置之 斷面圖。該半導體裝置與第20圖上所示者最大不同之點係 爲在最上層絕緣膜2 5上積層設置第1、第2外部半導體結 構體71、77，在最下層絕緣膜38下面配置焊錫球27。另 外，這種情形，包覆第1、第2外部半導體結構體71、7 7 -32- 1278048 及第1 '第2結合引線76、80之封止材81係藉下注塑形 (Uansfei: mold)法等形成，在切斷以得出各個半導體裝置時 封止材8 1也一倂切斷。 (第4實施形態） 第26圖係表示本發明之第4實施形態之半導體裝置之 要部（例如’相當於去掉第2 5圖所示之封止材8 1及第1、 第1結合引線76、80等之狀態之半導體裝置）之平面圖。 該半導體裝置在半導體結構體4和第1外部半導體結構體 7 1之間因存在有最上層絕緣膜25等，故使用外形尺寸大 之半導體結構體4，在對應該半導體結構體4之區域內之 最上層絕緣膜25上面設有經第1、第2結合引線（未圖示） 與第1、第2外部半導體結構體71、77之連接墊（未圖示） 連接之第1、第2表面處理層70a、70b。 但是，若是將第1、第2外部半導體結構體7 1、7 7直 接疊積在設於底板1上之半導體結構體4上之情形時，則 需在底板1搭載半導體結構體4之區域之外側，設置經結 合引線與三個半導體結構體4、71、77連接之連接墊，從 而底板1之尺寸大幅增大。相對於此，第26圖所示之半導 體裝置，如上述，在對應半導體結構體4之區域內之最上 層絕緣膜25上，因設有經第1、第2結合引線與第1、第 2外部半導體結構體7 1、77之連接墊連接之第1、第2表 面處理層7 0 a、7 0 b，故能將底板1之尺寸作得很小。 (第5實施形態） 第27圖係表示本發明之第5實施形態之半導體裝置之 -33- 1278048 正面圖。該半導體裝置係積層多數’例如四個’相當於第 20圖所示之半導體裝置之半導體塊。這種情形’最下層之 半導體塊（block)91係爲基本上與第20圖所示之半導體裝 置相同，但尺寸係比第2 0圖所示之半導體裝置稍大，於其 上面封止材81之周圍設有上部連接墊部92。其它之半導 體塊93係爲基本上與最下層之半導體塊91相同’但無設 置焊錫球2 7，代之以在下部連接墊部9 4下設置焊錫球9 5 ，另外，在其上面封止材81之周圍設有上部連接墊部96 ，前述下部連接墊部94係設在半導體塊93之下面，對應 封止材81之周圍之區域上。 這裡，上部連接墊部92、96係藉第20圖所示之第2 下層再配線3 7之連接墊部之一部分形成。這種情形，也可 在最下層絕緣膜3 8之開口部3 9內形成表面處理層，俾使 用於形成上部連接墊部92、96之第2下層再配線37之連 接墊部露出。另外，下部連接墊部94係藉第20圖所示之 第2上層再配線24之連接墊部形成。這種情形，用於形成 下部連接墊部94之第2上層再配線24之連接墊部係只設 在對應封止材8 1之周圍之區域。 然後，第2層之半導體塊93藉其焊錫球95與最下層 之半導體塊91之上部連接墊部92接合在~起而搭載在最 下層半導體塊91上。第3層及第4層之半導體塊93則是 藉其焊錫球95與第2層及第3層之半導體塊93之上部連 接墊部96接合在一起而搭載於第2層及第3層之半導體塊 9 3上。另外，封止材8 1的厚度若是0 · 5〜0 · 6mm之情形時 -34- 1278048 則焊錫球95之直徑採用0.8〜1 .0mm者即可。 上述各實施形態係針對積層搭載兩個外部半導體結構 體之情形說明，但並不限定於這種情形，也可作成搭載一 個，或積層搭載三個以上。另外，上述實施形態係針對上 層再配線及下層再配線皆作成二層之情形說明，但並不限 定於這種情形，也可作成一層或三層以上，另外，兩者之 層數也可作成不同層數。但是，作成相同層數之情形，能 降低半導體裝置之彎曲。 另外，上述實施形態係在相互接鄰之半導體結構體4 之間切斷，但並不限定這樣，也可作成將二個或二個以上 之半導體結構體4作爲一組而行切斷。這種情形，對各個 半導體結構體4，其之各個多數之外部半導體結構體也可 作成積層結構。另外，由多數個作成一組之半導體結構體 4可係爲同類或不同類。 另外，上述實施形態，半導體結構體4係作成具有作 爲外部連接用電極之柱狀電極1 4，但並不限定這樣，也可 係爲無柱狀電極但具有再配線1 3，於該再配線1 3上設有 作爲外部連接用電極之連接墊部，另外，也可係爲無柱狀 電極及再配線，但具有作爲外部連接用電極之連接墊部7 (亦即^裸晶片）。 【圖式簡單說明】 第1圖係爲本發明之第1實施形態之半導體裝置之斷 面圖。 第2圖係爲用於說明第1圖所示之半導體裝置之製造 -35- 1278048 方法，最初製作之構件之斷面圖。 第3圖係爲接續第2圖之製造工程之斷面圖。 第4圖係爲接續第3圖之製造工程之斷面圖。 第5圖係爲接續第4圖之製造工程之斷面圖。 ， 第6圖係爲接續第5圖之製造工程之斷面圖。 第7圖係爲接續第6圖之製造工程之斷面圖。 第8圖係爲接續第7圖之製造工程之斷面圖。 第9圖係爲接續第8圖之製造工程之斷面圖。 第10圖係爲接續第9圖之製造工程之斷面圖。 φ 第1 1圖係爲接續第1 0圖之製造工程之斷面圖。 第12圖係爲接續第11圖之製造工程之斷面圖。 第1 3圖係爲接續第1 2圖之製造工程之斷面圖。 第14圖係爲接續第13圖之製造工程之斷面圖。 · 第15圖係爲接續第14圖之製造工程之斷面圖。 v 第16圖係爲接續第15圖之製造工程之斷面圖。 第1 7圖係爲接續第1 6圖之製造工程之斷面圖。 第18圖係爲接續第17圖之製造工程之斷面圖。 鲁 第19圖係爲接續第18圖之製造工程之斷面圖。 第20圖係爲本發明之第2實施形態之半導體裝置之_ 面圖。 第21圖係爲用於說明第20圖所示之半導體裝置之製 造方法之斷面圖。 第22圖係爲接續第21圖之製造工程之斷面圖。 第23圖係爲接續第22圖之製造工程之斷面圖。 -36- 1278048 第24圖係爲接續第23圖之 第25圖係爲本發明之第3實 面圖。 第26圖係爲本發明之第4實 面圖。 第27圖係爲本發明之第5實 面圖。 【主要元件符號說明】 1 底 板 2 上 層 配 線 3 下 層 配 線 4 半 導 體 結 構體 (第1 5 接 著 層 6 矽 基 板 7 連 接 墊 13 再 配 線 14 柱 狀 電 極 15 封 止 膜 16 絕 緣 層 (絕緣材） 17 第 1 上 層 絕緣 膜 20 第 1 上 層 再配 線 2 1 第 2 上 層 絕緣 膜 24 第 2 上 層 再配 線、 25 最 上 層 絕 緣膜 :造工程之斷面圖。 g形態之半導體裝置之斷 g形態之半導體裝置之斷 g形態之半導體裝置之斷 半導體結構體） 匕層配線 -37- 1278048 27 焊 錫 球 3 1 第 1 下 層 絕 緣 膜 3 3 第 1 下 層 再 配 線 34 第 2 下 層 絕 緣 膜 37 第 2 下 層 再 配 線 3 8 最 下 層 絕 緣 膜 40 半 導 體 結 構 體 (第 2半 導 體 結 構體） 42 貫 通 孔 43 上 下 導 通 部 70a，70b 表 面 處 理 層 7 1,77 半 導 體 結 構 體 (第 2半 導 體 裝 置） 76 第 1 結 合 引 線 80 第 2 結 合 引 線 8 1 封 止 材 9 1，9 3 半 導 體 塊 92 上 部 連 接 墊 部 94 下 部 連 接 墊 部 95 焊 錫 球
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Claims (1)

1278048 第93134108號「半導體裝置及其製造方法」專利案 (2006年1月16日修正） 十、申請專利範圍： 1. 一種半導體裝置，其特徵爲包含： 具有多數之外部連接用電極（14)之第1半導體結構 體⑷； 設在前述第1半導體結構體（4)之周圍之絕緣材（16) $ 設在前述第1半導體結構體（4)及前述絕緣材（16)之 上面側之上層配線構造（17，20，21，24); 設在前述第1半導體結構體（4)及前述絕緣材（16)之 下面側之下層配線構造（2，1，3，31，33，34，37);及 至少搭載在前述上層配線構造（17，20，21，24)上或 前述下層配線構造（2，1，3 , 3 1，3 3，3 4，3 7 )上之第2半導 體結構體（40，71，77)， 其中具有貫通前述絕緣材（16)而與前述上層配線構 造（17，20，21，24)和前述下層配線構造（2，1，3，31，33, 3 4, 3 7)行電性連接之上下導通部（43)。 2. 如申請專利範圍第1項之半導體裝置，其中前述第2半 導體結構體（4 0，7 1，7 7 )係只搭載在前述上層配線構造 (17, 20, 21，24)或前述下層配線構造（2, 1，3, 31，3 3, 3 4, 37)上，在未搭載前述第2半導體結構體（40, 71，77)之 前述上層配線構造（1 7，2 0，2 1，2 4)或前述下層配線構造 (2，1, 3, 3 1，33，34，37)上設有焊錫球（27)。 1278048 3 .如申請專利範圍第1項之半導體裝置，其中前述上層配 線構造（ 1 7, 20, 2 1, 2 4)具有多層之上層絕緣膜（17, 21)及 多層之上層再配線（2 0，2 4)。 4·如申請專利範圍第3項之半導體裝置，其中在前述多層 之上層再配線（20，24)中最上層之上層再配線（2 4)具有連 接墊部，前述上層配線構造（1 7，2 0，2 1，2 4)係包含最上 層絕緣膜（25)，其係包覆除掉前述連接墊部外之前述最 上層之上層再配線（24)上面。 5.如申請專利範圍第4項之半導體裝置，其中在前述最上 層之上層配線（24)之前述連接墊上設有焊錫球（27)。 6·如申請專利範圍第4項之半導體裝置，其中在前述最上 層之上層配線（2 4)上設有表面處理層（70 a，70b)。 7·如申請專利範圍第6項之半導體裝置，其中前述第2半 導體裝置（71，77)係搭載在前述最上層之絕緣膜（25)上。 8·如申請專利範圍第7項之半導體裝置，其中前述第2半 導體裝置（71，77)具有接於前述表面處理層（70a，70b)之 結合引線（7 6，8 0)。 9 ·如申請專利範圍第1項之半導體裝置，其中前述下層配 線構造（2，1，3，3 1，3 3，3 4，3 7 )包含底板（1 )、下層絕緣 膜（3 1 )及下層再配線（3 3 )。 10·如申請專利範圍第9項之半導體裝置，其中前述底板（1) 至少具有設在其上面之上層配線（2)或設在其下面之下層 -2- 1278048 配線（3)。 1 1 .如申請專利範圍第1 0項之半導體裝置，其中前述上層 配線（2)及前述下層配線（3)之至少之一係爲接地配線。 1 2 .如申請專利範圍第9項之半導體裝置，其中前述底板（1) 係由含有補強材之熱硬化性樹脂作成者。 1 3 .如申請專利範圍第1項之半導體裝置，其中前述下層配 線構造（2，1，3, 3 1，3 3, 3 4, 3 7)包含多層之下層絕緣膜（3 1， 3 4)及多層之下層再配線（3 3, 3 7)。 1 4 ·如申請專利範圍第1 3項之半導體裝置，其中在前述多 層之下層再配線（3 3，3 7 )中，最下層之下層再配線（3 7 )具 有連接墊部，前述下層配線構造（2，1，3，31，33，34，37) 包含最下層絕緣膜（3 8)，其係包覆除掉前述連接墊部外 之前述最下層之下層再配線（37)上面。 15.如申請專利範圍第14項之半導體裝置，其中在前述第2 半導體裝置（40)和前述最下層之下層再配線（24)之間有 設置焊錫球（4 1 )。 16·如申請專利範圍第14項之半導體裝置，其中在前述最 下層之下層再配線（3 7)上面設有表面處理層（70a，70b)。 17·如申請專利範圍第16項之半導體裝置，其中前述第2 半導體裝置（71，77)係搭載在前述最下層之絕緣膜（3 8)上 18.如申請專利範圍第17項之半導體裝置，其中前述第2 1278048 半導體裝置（71，77)具有接至前述表面處理層（7〇a，7〇b) 之結合引線（76，80)。 19·如申請專利範圍第〗項之半導體裝置，其中前述第1半 導體結構體（4)之前述外部連接用電極（14)係爲高度6〇// m 以上之柱狀電極。 20·如申請專利範圍第19項之半導體裝置，其中前述第1 半導體結構體（4 )含有保護膜（1 〇 )，前述外部連接用電極 (14)係設在前述保護膜（1〇)上。 21·如申請專利範圍第20項之半導體裝置，其中前述第1 半導體結構體（4)具有設在位於前述外部連接用電極（14) 之間之前述保護膜（10)上的絕緣膜（15)。 22·—種半導體裝置之製造方法，其特徵爲包括下述工程： 藉底板（1)、絕緣材（16)及上層絕緣膜（17)分別密封 形成各具有多數之外部連接用電極之第1半#體結構體 (4)； 在前述上層絕緣膜（17)上形成上層再配線（20); 在前述底板（1)下形成下層再配線（33); 至少在前述上層再配線（20)上或下層再配線（3 3)上 搭載第2半導體結構體（40);及 切斷前述底板（1)、前述絕緣材（16)及、前述上層絕緣 膜（17)，得出多個具有至少一個前述第1半導體結構體（4) 及至少一個前述第2半導體結構體（4〇)之半導體裝置； 在前述底板（U、前述絕緣材（1 6)及前述上層絕緣膜 (17)上形成貫通孔（42)之工程，及在前述貫通孔（42)內 1278048 形成使前述上層再配線（20)和前述下層再配線（3 3)連接 之上下導通部（43)之工程。 2 3 .如申請專利範圍第2 2項之半導體裝置之製造方法，其 中將前述第1半導體結構體（4)分別密封形成之工程包括 :製作能配列多個前述第1半導體結構體（4)之尺寸的底 板（1)之工程、將前述第1半導體結構體（4)相互分隔固 定設置於前述底板（1)上之工程、在前述底板（1)位在前 述各個第1半導體結構體之周圍上形成前述絕緣材（16) 之工程、及在前述第1半導體結構體（4)上形成前述上層 絕緣膜（17)之工程。 24·如申請專利範圍第23項之半導體裝置之製造方法，其 中將前述第1半導體結構體（4)分別密封形成之工程，包 括使用加熱加壓板（55，56)加熱加壓前述上層絕緣膜（17) 、前述第1半導體結構體（4)、前述絕緣材（16)及前述底 板⑴。 25.如申請專利範圍第22項之半導體裝置之製造方法，其 中前述底板（1)具有上層配線（2)及下層配線（3)。 2 6 ·如申請專利範圍第2 5項之半導體裝置之製造方法，其 中另包括在前述底板（1)、前述絕緣材（16)及前述上層絕 緣膜（17)上形成貫通孔（42)之工程，及在前述貫通孔（42) 內形成使前述上層再配線（20)與前述上層配線（2)及前述 下層配線（3)之至少之一連接的上下導通部（43)之工程。 27 .如申請專利範圍第25項之半導體裝置之製造方法，其 中前述上層配線（2)及前述下層配線（3)之至少之一係與 1278048 前述上下導通部（43)連接。 2 8 .如申請專利範圍第 22項之半導體裝置之製造方法，其 中前述第1半導體結構體（4)之前述外部連接用電極（14) 係爲具有60 // m以上高度之柱狀電極。 29. 如申請專利範圍第 28項之半導體裝置之製造方法，其 中前述第1半導體結構體（4)含有保護膜（1〇)，前述外部 連接用電極（14)係設在前述保護膜（10)上。 30. 如申請專利範圍第29項之半導體裝置之製造方法，其 中前述第1半導體結構體（4)具有設在位於前述外部連接 用電極（14)之間之前述保護膜上的保護膜（1 5) °
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DE602004009821T2 (de) 2008-03-06
US20080044944A1 (en) 2008-02-21
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US20080006943A1 (en) 2008-01-10
USRE43380E1 (en) 2012-05-15
US7368813B2 (en) 2008-05-06
EP1683198B1 (en) 2007-10-31
EP1683198A2 (en) 2006-07-26
DE602004009821D1 (de) 2007-12-13
US20050140021A1 (en) 2005-06-30
US7692282B2 (en) 2010-04-06
US7563640B2 (en) 2009-07-21
TW200529338A (en) 2005-09-01
KR20060086346A (ko) 2006-07-31
WO2005045902A3 (en) 2005-08-18

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