TW571421B - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
TW571421B
TW571421B TW091124700A TW91124700A TW571421B TW 571421 B TW571421 B TW 571421B TW 091124700 A TW091124700 A TW 091124700A TW 91124700 A TW91124700 A TW 91124700A TW 571421 B TW571421 B TW 571421B
Authority
TW
Taiwan
Prior art keywords
aforementioned
semiconductor device
terminal
semiconductor wafer
pins
Prior art date
Application number
TW091124700A
Other languages
English (en)
Inventor
Fujio Ito
Hiromichi Suzuki
Original Assignee
Hitachi Ltd
Hitachi Ulsi Sys Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Ulsi Sys Co Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW571421B publication Critical patent/TW571421B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32052—Shape in top view
    • H01L2224/32055—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4801—Structure
    • H01L2224/48011—Length
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48639—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48663—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48664—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/8212—Aligning
    • H01L2224/82148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/82169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, e.g. nozzle
    • H01L2224/8218—Translational movements
    • H01L2224/82181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

571421 ⑴ 玖、發明說明 (發明說明應敘明：發明所屬之拮 [發明的技術領域]域、先讀術謂、實峨及賴單糊 右=顿隸半㈣裝以«造技術，特縣關於可 有效適用於樹脂封裝型半導 [先前技藝] ^衣置之夕接腳化之技術。 QFN(QuadFlatN〇n-leadedpackage:扁 型封裝體）屬於利用模辨榭 引腳 ^ L ^月曰形成之封裝體封裝搭載於引 腳框之半導體晶片之樹脂封裝體之一種。 =係：經由焊接線電性連接至半導體晶片之多數引腳 之：1部由外周部之(下面）露出而構成端子，並呈 現將焊接線連接至與前述端子之 玉 接至封裝體内部之端目反側之面，即連 ^ 面而使刚述端子與半導體晶片電性 。而後’利用將此等端子焊接於印刷電路基板 之電極（腳印刷電極）而6 —牡 „ ^ ,,. 几成女农。此種構造與將引腳由封 衣肢（package)之側面向椹 咖舰tp〜:扁平；二延伸而構成端子之⑽ 右—壯品社$ 式四邊有引腳型封裝體）相比，具 有女· ^^面積更小之優點。 有關上述QFN之文齡+ , 文馱例如在曰本特開2〇0卜】894 1 〇號\ =特許（日f發明專利）第3㈣91號等曾有記載。 [S明所欲解決之問題] 化但，職伴隨㈣成於半導體晶片之⑸之高機能 化、尚性能化而欲增加嫂义 下列之問題。日加^數（多接腳化）時，卻可能發生 即’如前所述，由於_係將焊接線連接至與露出封裝 (2)
571421
體之S之端寸' 面；^θ Π： / f _>r XI 甸相反側之面，端子間距與引腳之焊接線連 接處之間距相同，„㈤2 ^ 且因鈿子面積必須可確保安裝時之可靠 性之特定面積，私/_i1 一 ^ 玟恶法太過亇以縮小。 □此奴在不改變封裝體尺寸之情況下謀求多接腳化時 ’由於端子數無法如願增加，故無法大幅達成多接腳化。 另一方面，欲增大封裝體尺寸，以謀求多接腳化時，由於 半導體晶片與焊接線連接處之距離變長，焊接線長度也會 '交長，故可能在金屬線焊接工序或樹脂模塑工序中發生相 鄰之金屬線彼此短路等之問題，以致於降低製造良率。 另外，基於降低製造成本之目的而緊縮半導體晶片時， 也由於半導體晶片與焊接線連接處之距離變長，而發生不 能施行焊接線之連接之問題。 本發明之目的在於提供可達成QFN之多接腳化之技術。 本發明之另一目的在於提供可獲得應付晶片緊縮需要之 QFN之技術。 本發明之前述及其他目的與新穎之特徵可由本專利說明 書之說明及附圖獲得更明確之暸解。 [解決問題之手段] 本案所揭示之發明中，較具有代表性之發明之概要可簡 單說明如下： 本發明之半導體I置係包含半導體晶片、搭載前成半導 體晶片之晶墊部、配置於前述半導體晶片之周圍之多數引 腳、電性連接如迷半¥體晶片與—迹弓|腳之多數金屬線、 密封前述半導體晶片、前述晶塾部、前述多數引腳及前述 (3)
571421 多數金屬線之封裝體，前述多數 本、M 卿“形成使接近於前述 /體晶片之—端部侧之間距小於位於與前述-端部側相 :側之他端部側之間距’在前述多數引腳之各引腳，選擇 也没置由前述封裝體之背面向外部突出之端子。 本發明之半導體裝置之製造方法包含以下而^工序。 _覆形成含前述晶墊部與前述多數引腳之圖案，並準 備在前述多㈣腳之各引腳之-面形成向垂直於前述一面 之方向突出之端子之引腳框之工序； ⑻在形成於前述引腳框之前述多數晶墊部之各晶塾部搭 载半導體晶片，利用金屬線連接前述半導體晶片與前述引 腳之一部分之工序者； ⑷準備含上模與下模之模具，以樹脂薄片包覆前述下模 士表：後，將前述引腳框載置於前述樹脂薄片i，而使形 、：刖述引卿之一面之舸述端子與前述樹脂薄片相接觸之 工序； 士⑷以^上模與前述下模夾定前述樹脂薄片及前述引腳 匡’亚使河述端子之前端部分嚴入前述樹脂薄片内之工序； (e.)將樹脂注入前述上槿乂 H 、，、別述下杈之間隙，藉以密封前 4 +守月豆曰日片、前述晶墊 . 「、刚述引腳及前述金屬線，同 H寸形成使丽述端早之前妒& 4 _ 而砟分突出外側之多數封裝體後， 由刚述杈具取出前述引腳樞之工序；及 (f)利用切割前述引腳樞 個體之工序。 向朌刚述多數封裝體分離成獨立 [發明之實施形態] (4)571421
、 依據圖式詳細說明本發明之# 明實施开；能夕所女 J之貝施形態。又，在今 心®之所有圖中，對於1 隹。兄 同-I碼予以顯示……機能之構件，附以 貫施形態中，在牿 °月。又，在以下之 樣部分作重複說明。 原則上不對同一或同 (貝、施形態一） 圖I係表示本實施形能之
圖2係表示QFN之外觀卜硯（表面側）之平面圖’ 之内部構造(表面側)之平 目’圖3係表示QFN (背面側)之平面圖R / ° 係表示QFN之内部構造 )之十面圖，圖5係QFN之剖面圖。 本實施形態之奸…具有利用 片2之表面安裝型之封甘蝴战 衣祖^搶封丨個半導體晶 x 12 “構造，其外形尺寸例如為縱X橫 mm x 12 _、厚吐〇 mm。 蚁 上述半導體晶片 月-仏以格載於金屬製之 :Γ_/之中央部。此半導體晶片2之-邊二： t述晶塾部4為了能夠搭戴例如-邊尺寸為4_ 二:ΤΓ内之多數種半導體晶u，呈現其直徑小於 直…“月小具片構造，在本實施形態中，呈 1 :直徑。晶塾部4係與此形成為-體，並被向封裝 之四角延伸之4支吊腳5 b所支持。 在上述晶墊部4之周圍，以包圍晶墊部4方式配置有由相 ㈣之金屬形成之多數支（例如H6支）引 心。此^丨腳5之—端部侧（接近於半導體晶片2之側）5a經 由金線6每性連接至车莫㈣曰 +守脰日日片2之主面之焊接墊7,與此相 ' 10 - (5)571421
上沛他知部側5c係以封裝體3之側面作為終端。 二：引腳5之各引腳為縮短與半導體晶片2之距離，將一 ::繞接至晶墊部4附近，其前端之間距（p3)形成窄間
V 部側5a Im〜〇.2叫。因此’鄰接之引腳5之間距在—端 時，g 。方]方、他纟而部侧5 C。以此方式形成引腳5之形狀 ^即可縮短連接引腳5之一端部侧5a與焊接墊7之金線6 ^艾本Λ施形恶中，為3 mm以下），故即使在多接腳化 窄^且配合多接腳化而使引腳5之間距’即金線6之間隔變 :^也可抑制在QFN1之製造工序（例如在金屬線焊接工 ，彳知模塑工序）中發生金線6彼此短路之瑕疵現象。 , 斤下在QFNl之背面（基板安裝面）設有多數個（例 、二6個）外部連接用端子8。此等端子8係沿著封裝體3之各 =別賴齒狀各配置2行，各端子8之前端騎由封裝體3 :背面露出’且突出於外側。端子8之直徑⑷為〇.3 _， 、接之☆而子8之間距在與同-行之端子8之間距(Ρι)為 .5 mm ’在與另-行之端子8之間距（p2)為◦奶匪。 本實施形態之端子8係與引腳5形成為—體，端子8之厚产 為125 _〜150 _程度。又，引腳5之端子8以外部分了^ ，一端部側5a及他端部側5c等之厚度為μ μπι〜75卜咖程产 。又’在突出封裝體3之外側之端子8之前端部分，利：： 鍍法或印刷法包覆著焊料層9。本實施形態之QFm係利: :此等端子8焊接於印刷電路基板之電極(腳印刷電極)而 完成安裝。 其次，說明上述QFN]之製造方法。首先，準備如圖6所 -11 - 571421 (6) 爾明說朝續頁 示之引腳框LF!。此引腳框LFi係由Cu、Cu合金或Fe-Ni合金 等之金屬板所構成，並呈現反覆在縱及橫方向形成含前述 之晶墊部4、引腳5、吊腳5b等之圖案之構成。即，引腳框 LF [係i現搭載多數個（例如24個）半導體晶片2之多連式構 造。 為了製造上述引腳框LFi，準備如圖7所示之板厚125 μιη
〜150 μΏ1程度之Cu、Cu合金或Fe-Ni合金等之金屬板10， 利用光阻膜11包覆形成晶墊部4、引腳5及吊腳汕之處之單 面又’形成外部連接用端子8之處則以光阻膜1 1包覆兩 面。而後，在此狀態下，利用藥液蝕刻金屬板丨〇，直到單 一面被光阻膜Π包覆之區域之金屬板1〇之板厚成為一半程 度（6) μηι〜乃μηι)(半蝕刻）為止。利用此方法施行蝕刻時， 一，又〜e ,心玄觸枚丨υ无全消失
在單一面被光阻膜η包覆之區域形成厚65 μηι〜75 之晶墊部4、引腳5及吊腳5b。又，兩面被光阻_包々 區域之金屬板则未受藥液㈣，故形成具有與姓心 同厚度（125叫〜15() μιη程度）之凸起狀之端子8。 其次，除去光阻膜U，接著，_腳5之一端部側& 面施以Ag電鍍而完成前述圖6所示之引腳框π。又，4 對力腳框LFi之全面施以Pd(鈀)電錢，以作為取代對弓| 端部側5amg電鐘之手段。pd電鑛與~電鑛相^ 電鍍層之膜厚較薄，故可提高引腳5與金線6之接合性。 ^腳框LF|之全面施以電鍍時，端子8之表面也會同 t成电鍍層，故可縮短電鍍工序。 -12 - 571421 ⑺ 發明說明纜買 如此，利用將構成引腳框L f i %竹t金屬板1〇之—部 分之單-面以光阻膜U包覆後’施以半蝕刻，使引腳5之板 厚薄化至金屬板1〇之—半程度時’即可高精確度地完成一 端部侧5a之間距極為狹窄(在本實施形態中，為Ο” _〜 0.2 mm間距）之引腳5之加 金屬板1 0之一部分之兩面 5 b之同時，形成端子8。 又可利用以光阻膜11包覆 ，在形成晶墊部4、引腳5及吊腳
其次，為了使用上述引腳框LFi製造QFm，首先，如圖 及圖9所示，使半導妒曰, 忱千守版日日片2之兀件形成面朝上而搭載於』 墊部4上’使ffiAu膏或環氧樹脂系之接著劑，將兩者接著。 施行上述作業時’如圖9所示’由於突起狀之端子8位方 引腳框LFl之背面.丨’故只要在支持引腳框LF〖之夾具後 朝向端子8之處形成溝31即可。如此-來，即可穩定地支# 引腳框LF!，故在將半導體晶片2搭载於晶墊部4上之際，7 防止引腳框LF|變形，或晶墊部4與+導體晶片2之位置丁偏老
荨麻煩問題發生。 >又==施形態之QFN1係構成撐起式翼片之構造，即在 半‘脸日日片2 I疋於模具而施行樹脂模塑之際，為了使半 導體曰^片2之上面側與下面侧之樹脂之流動保持均勻，可利 用折弓吊腳外之一部分，將晶墊部4配置於比吊腳％高之位 置。，因^，如圖9所示，可利用在夾具30A朝向晶墊部4之 處形成大起部3 2之方式穩定地支持引腳框LF j ,故在將半導 月丑日日片2格栽於晶墊部4上之際，可防止引腳框L i變形，或 晶墊部4與半導體晶片2之位置偏移等麻煩問題發生。 -13 - (8) (8)571421 發明說明繽m 其A，如圖10及圖i i所示，利用周知之球形接合裝置， 利用无、泉6連接半導體晶片2之焊接墊7與引腳5之一端部側 4^間。此時也如圖Π所示，可利用在支持引腳框LFl之夾 〃 〇0B朝向纟而子8之處形成溝31，或在朝向晶墊部*之處形成 突起部32之方式穩定地支持引腳框LFl，故可防止金線6與 引腳5之移位、及金線6與焊接墊7之移位。 "其次，將上述引腳框LFi裝定於圖12所示之模具4〇後，將 半導體晶片2樹脂圭、十梦。9 #主, 彳了細封衣圖12係表不模具4〇之一部分（約“固 QFN份之區域）之剖面圖。 使用此核具40將半導體晶片2樹脂封裝之際，首先，將薄 的樹脂薄片41舖在下模4〇β之表面，在此樹脂薄片41上載置 引腳框％。引腳框％係以形成突起狀之端子8之面朝下方 式被載置’使端子8與樹脂薄片41相接觸。而後，在此狀態 下’以上模40八與下模40B夾定接于脂薄片似引腳框 如此-來，如圖所示’位於引腳5下面之端子8即可利用模 具 40(上模 4〇Aife 下模 40JB)之 、 _ ”卜衩4UB)之推蜃力推壓樹脂薄片41，故可 使其前端部分嵌入樹脂薄片4丨中。 2結果’如圖Π所示，將溶融樹脂注人上模佩與下模 A與下拉柳時，即可使嵌人樹脂薄片41卜端子 之耵端部分由封裝體3之背面突出於外侧。 〜 又，引腳框LFk上面被上模4〇A所推壓時，彻 腳框[匕之金屬板之彈簧力，將向上之力作用於 之前端側之-端部側5a。因此，、為引腳） I貝施形恶之引腳框LF] -14 - 7l42l ⑼ 發明說明繽_ 所示，將端子8配置成2行時，錢子8形成於接近於一端部 、丨5a之方之引腳5、與端子8形成於離開一端部侧之一 方之引腳）中，端子8推壓樹脂薄片4 1之力會有差異。即， 形成於接近於一端部側“之一方之端子8推壓樹脂薄片Μ 之力比形成於離開一端部侧5a之一方卜接近於上模4〇A與 弓丨腳5之接觸部分之-方)之端子8推壓樹脂薄片41之力弱 。、其結果，形成於接近於一端部侧5a之一方之端子8、與形 成於離開-端部侧化之—方之端子8在由封裝體^之背面突 出於外側之高度會產生差異，在將此等端子8焊接於印刷電 Μ板之電極（腳印刷電極）上之際，一部分之端子8與電極 之間有發生不接觸之開放不良之疑慮。 有此種旋慮時，如圖i 4所示，/口、要將形成於接近於一端 部侧5a之—方之端子8之引腳5之寬(w。設定為寬於形成於 離開一端部侧5&之-方之端子8之引腳5之寬(W2)(W2<Wi) 即可。如此—來，端子8推壓樹脂薄片41之力在所有之引腳 5中均大致相同’故嵌入樹脂薄片41中之端子8之量，即由 封裝體。之背面突出於外侧之端子8之前端部分之高度在所 有之引腳5中均大致相同。 又士則所述，本貫施形態中所使用之引腳框LF j由於係 利用半敍刻方式形成圖案（晶塾部4、弓！腳5、巾腳外等卜、 故引腳5之板厚可薄化至通f之引腳框之〆半程度，因此， 模具40(上模4〇A及下模4〇B)推壓引腳框LFi之力比使用通 常之引腳框之情形為弱，故端子8推壓樹脂薄片4 1之力變弱 之、洁果，w降低突出於封裝體3外側之高度。 -15 - (10) (10)571421 發明說明繽裒 因/，希望增力口突出於封裝體3外側之端子8之高度時， ，二斤丁 〃要不對與上模4G A’接觸之部分（圖中用◦符 1圍成之部分）之引腳框lF祐主 相同厚度即可。 -…刻’使其與端子8保持 網_係以斜線表示上述模具㈣之上模術與引腳框叫妾 &之邛刀之平面圖。又，圖】7係表示此模具⑽之澆口位置 與注入於模腔之樹脂之流動方向之模式的平面圖。 如圖16所示，上述模具4〇係呈現僅弓（腳框^之外框部分 、及引腳5與引腳5之連結部分接觸於上模40A，其他之所 有區域均可被有效利料為注人樹脂之膜腔之構造。 又’如圖17所示’上述模具40之—邊設有多㈣口 Gl〜 g16’例> 里現經由澆口 Gi、G2將樹脂注入排在圖左端之縱 方向之3個模腔c ,〜C、，妳A法n r ^ 1 3 、、工甶九口 、G4將樹脂注入盥此等 鄰接之3個模腔C4〜C6之構造。；—方面，在與上述洗口 相對向之另一邊，設有假模腔dCi〜Dq及排氣孔 42,例如呈現經由淹口 G[、化將樹脂注入模腔Ci〜q時， 可使模腔Cl〜C3内之空氣流入假膜腔％，以防止模仏 内之樹脂產生孔隙之構造。 圖18係利用將樹月旨注入上述模月空Cl〜C1S而成型模塑樹 脂，以形成封裝體3後，由模具40所取出之引腳框LFi之平 面圖，圖19係沿著圖18之）（—X，線之剖面圖，圖2〇係之引 腳框LF 1之背面側之平面圖。 其次，在露出於引腳框LFl之背面之端子8之表面形成焊 料層9，接著，在封裝體3之表面印上製品名稱之標記後’ -16 - 571421
發明說钥續買 -I- 沿著圖18所示之切割線L切斷引腳框LFi及模塑樹脂之 分時，即可完成24個前述旧〜圖5所示之本實施形態< QFN1。X，在將qFNi安裝於印刷電路基板之際，希望招 大QFN：[與印刷電路基板之間㈣，即希望增大讲⑴之· 料存取里％ ’將形成於端子8之表面之焊料層9之膜厚增;| 至）〇 μιη程度。為了形成此種膜厚，例如可使用利用金屬澤 將焊料膏印刷在端子8之表面之方法。
如此，本實施形態之卿1由於將引腳5之-端部侧 接至晶塾部4附近’故可縮短一端部側&與半導體晶片2間 之距離’連接此等之金線6之長度也可縮短…即使將端 ^8配置成鋸齒狀，由於引腳5之一端部侧&之長度大致相 等，故-端部侧5a之前端可大致成一行排列在半導體晶片: 之各邊。因此’連接引腳5之一端部侧5a與半導體晶片2之 金線6之長度可大致保持均等，㈣金線6之環路形狀也可 大致保持均等。 因此，不會發生鄰接之金線6彼此短路，$其在半導體晶 片2之四角.附近金線6彼此交叉等之麻煩問題，故可提高金 屬線焊接之作#性。1因可縮小鄰接之金線6間之間距，故 可貫現QFN 1之多接腳化。 。又，由於將引腳5之一端部侧5a繞接至晶墊部4附近，故 I延長由端子8至引腳5之—端部側5a之距離，藉以=通過 ^出方；封1體3之外部之端子8而浸入封裝體3之内部之水 刀難以到達半導體晶片2，可防止水分導致焊接墊7之腐蝕 ’提鬲Q F N 1之可靠性。 -17 - 571421
(12) 又，由於將引腳5之一端部側5 a繞接至晶墊部4附近，故 即使緊縮半導體晶片2 ’金線6長度之增加也極為少量（例如 即使將半導體晶片2由4 mm見方緊縮至3 mm見方，金線6 也僅平均增加0.7 mm之程度），故可防止緊縮半導體晶片2 所帶來之金屬線焊接之作業性之降低。 (實施形態二）
在前述實施形態一中，係就使用小翼片構造之引腳框LF i 製造之QFN之情形加以說明，但例如如圖2丨及圖22所示， 也可使用在引腳5之一端部側5a貼上薄片狀之晶片支持體 u之引腳框LF2加以製造。在本實施形態中，上述晶片支持 體3 3係由絕緣膜所構成。 恶' 之引腳框L F1之方法制、生 日、仕 1 万/ί:衣化。即準備如圖23所示之相
出μ.Γη〜15Q _程度之金屬板1〇，利用光阻膜丨丨包覆^ 引腳5之處之單一面。又，形成外部連接用端子8之處貝 :面形成光阻膜U。而後，利用前述實施形態一所^ :法對金屬板1〇施行半㈣，同時形成厚65 _ 2之引卿5與厚125陶肩陶程度之端猶，對引 之—端部側5a之表面施以π ^ ^ I藏’琅後將絕緣薄膜3 3本 & —端部侧5a之上面。又，士 ^ Φ Μ ^ Β 也可利用薄金屬板等之導1 汁'+ |構成晶片支持濟 ,' 取代絕緣薄膜。此時，為· 止引腳5彼此之短路，口 勹 gp可Υ /、要使用、'，巴緣性之接著劑接著引 I」。又，也可利用在金屬窄々电 薄片等來構成曰片白之表面塗敷絕緣性之樹; 餅取日曰A支持體3 3。 > 18- (13)
571421 在使用上述之弓丨腳框LF時，也 板ίο之一部分—單……]用先阻把11遮蔽金屬 至…1Π 面…+钱刻’使引腳5之板厚薄化 至 之—半程度，故可高精確度地完成引腳5之-端 部側）&之間距極為狹窄（例如Q.18 _〜w mm間距）之引 _之加工。又’可利用以光阻膜u遮蔽金屬板i。之一部分 之兩面，俾與弓丨腳5同時形成突起狀之端子8。 上述引腳框lf2與實施形態一所使用引腳框LFi之不同， =需要支持晶塾部4之吊腳5b，故可使引腳5_端部侧5&之 如端間距具有相當於該部分之餘裕。 又’以引腳5支持晶片支持體33,可縮短引腳之一端部侧 〜與半導體晶片2之距離，故可進—步縮短金線6之長度。 =外’與利用4支吊腳5b支持晶墊部4之情形相比，更可確 貝支持晶片支持體33 ’故在模塑工序中，將熔融樹脂注入 模二内之IV、，可抑制晶片支持體3 3之變位，防止金線6彼此 之短路之不良現象。 使用此引腳框LF2之QFN1之製造方法如圖24所示，與前 述實施形態一所說明之方法概略上相同。 (實施形態三） 刚述貫施形態一、二中，係以引腳框材料構成外部連接 用端子8，但也可利用下列方法形成端子。 首先’卞備如圖2 5所示之板厚7$ 程度之金屬板1 〇，利 用光阻膜Π包覆預備形成晶墊部4、引腳5及吊腳5b之處之 兩面，而後，在此狀態下，蝕刻金屬板1〇，藉以形成晶墊 部4、引腳5及吊腳5b。其次，除去光阻膜1丨，接著，對引 -19 - 571421 〇4) 腳5之一端部侧5 a之表面施以Ag電鍍，以製造弓丨腳框 此引腳框Lb除了無外部連接用端子8之點以外 〇 ‘ … 乂 y| ，王現與前 述實施形態一之引腳框LF丨相同之構成。又，引腳框 可與，之引腳框则樣地’以晶片支=3也3 構成日日塾#。又，引腳框咕之晶墊部4、引腳$及吊⑽ 也可利用衝壓金屬板10之方式形成。 其次’如圖26所示’在引腳#LF3之一部分形成不作實際 之端子使用之假端子12。為了形成假端子丨2，首先，疒弓 腳框lf3之背面4合絲網印刷用之掩罩15，將聚酿亞= 1 2 a印刷在後面之工序中預備形成外部連接用端子之二曰 ，將此聚醯亞胺樹脂12a烘乾（圖26(b)〜（d))。假端子二之 大小係設定於與後面之工序中預備形成之實P祭端子大小相 问程度。又’在此，係就將聚酿亞胺樹月曰” 之表面而形成假端子12之情形力⑽明，但 = ，只要在後面之工序中可由 ^ " 」由弓I腳5之表面加以剝離，不管任 何材質或形成方法均可使用。 其次’依據前述實你你能 〜灵轭形恶一所說明之方法 片2載置於晶墊部4上，桩荃 才千〒胜日日 5(W26(e))0 纟者’以金線6連接焊接墊7與引腳 其次，如圖27(aUf - ^ ^ 不，依據前述實施形態一所說明之方 去，以膜塑樹脂成型半導麟曰 」（万 形成在引腳5之—面之二:广2而形成封裝體3。此時’ 之背面突出於外側/ 端子丨2之前端部分由封裝體3 其次’如圖2 7 (b)所-, 不，由弓丨腳5之一面剝離上述假端子j 2 -20 - 571421
叙端亍1 2由聚醯亞胺樹脂所構成時，可利用聯氨等有機 /合^ ’合知假纟而子1 2之方式加以剝離。剝離假端子1 2時，封 豆之月面冒形成凹部35而使引腳5之一面露出。 、 /、人如圖28U)所示，在封裝體3之背面疊合絲網印刷用 电罩16後如圖28(b)所示，將焊料膏13a供應至凹部μ 之内部。 π早ib傻，使焊 六一人 ，
(嘁狀悲’ D此，如圖29所示，可形成電性連接於露出 口 h)之内部之彳丨腳5，且前端部由封裝體3之背面突出外 之焊料凸塊1 3。 2 =就將焊料膏⑴印刷在引腳5之表面，以形成 二二之情形加以說明’但也可將事先成形為球形之 广“、應至凹部35之内部後，對此 處理，以形成焊料凸塊13。 十一化熱 *二= = 焊料凸一 *通常係在完 使其成為獨立之個二:二腳枢… 為獨立之個體後ifr/v , σ在刀離Qfn 1使其成 上诚本; 端子12㈣成焊料凸塊…
上迷本μ知形態之製造方法I 刻而形成端子8之太 、一 、$引腳框LF丨施以半蝕 基板之種類等之=开可：用適合於咖之用途及安裝 卞 < 材料而形成端子。 (實施形態四） 外部連接用端子也可利用下列方 示，準備板厚〜m程度之薄的全屬板:成:即’如圓30所 卸板20，利用與前述實施 -21 - 571421
發增観_繽翼 形恶二同樣之方法，對金屬板2〇施行蝕刻而製成具有晶墊 邛4、引腳5及未圖式之吊腳5b之引腳框lF4後，將各引腳5 之中途部衝壓成形為剖面形狀以鋸齒狀。採用吊腳5b之一 邛分向上折彎之撐起式翼片構造時，只要同時施行吊腳5b 之折彎與引腳5之成形即可。又，晶墊部4、引腳5及吊腳5 也可利用对刖述貫施形態一所使用之厚的金屬板1 0施以神 蝕刻或衝壓成形方式加以形成。 1次，如圖3 1所示，將半導體晶片2搭載於上述引腳框A ^晶墊部4上，接著，以金線6連接焊接墊7與〗丨腳5之一端 側Μ，以膜塑樹脂成型半導體晶片2，以形成封裝體3 -如此一來，在封裝體3之背面即可露出形成鋸齒狀之引腳 5之凸部。
' 图""所示，利用砂磨機等工具研磨露出封裝體3 之肯面之引腳5之下端部後’切斷各引腳5之中途部，將i 支引腳5分割成多數引腳5、5。 其次，如圖33所示，在由i支引腳5分割成多數引_ 2引腳形成端子36。| 了形成此端子36，只要使用導 月之印刷、焊料球供應法或電鍍法等即可。又，形成 子％之作業通常係在成型膜塑樹脂，以形成封裝體3後立 Π&Γ然後’切斷騎㈣4而分離㈣丨使其成為獨立 二。但也可在分離QFN1使其成為獨立之個體後，再形 端子3 6 ^
又 3 4所 ’使用上述本實施形態之端子形成方法時，例如如圖 不’在形成在離開半導體晶片2之位置與半導體晶片2 -22- 571421
發明說明續畐 之附近交互設有一端部侧5 a之寬度較寬之引腳5，將金線6 焊接於此引腳5之各一端部側5 &後，如圖3 5所示，也可將引 腳5之中途部研磨切斷，以形成多數引腳5。採用此方法時 ’可實質地消除與鄰接之引腳5之間隔，故可大幅增加QFN 1 之立而子數。 (貫施形態五）
圖36係表示使用於QFN之製造之引腳框lf5之一部分之 平面圖，圖3 7係表示使用此引腳框LF5所製造之qFN之内部 構造（表面侧）之平面圖。 本貝、施形悲之引腳框L F5係王現交互地改變包圍晶墊部4 之周圍之多數支引腳5之前端（一端部側5 a)之長度之構成 又，使用此引腳框L F5時，作為搭载於晶墊部*之半導體 晶片2,使用沿著其主面之各邊分別配置2行鋸齒狀之焊接 塾7之半導體晶片。,
配置鋸齒狀之半導體晶片2之焊接墊7時，如圖38所示 利用環路高度低且長度短之金線6連接接近於半導體㊣ 之行之焊接墊7與前端長度較長之弓丨腳5,利用 長&長之金線6連接内側之行之焊接墊7與前 &車父紐之引腳5。 因汰匕，隨莫伞括 ，即金線6二體晶片2之多接魏，而使引腳5之 ’之間搞變窄時，也 干擾，故可有& 相鄰接之金線6· 或樹脂模狗//卩制在Q F N f造工序（例如金1線悍接. ”中發生金線6彼此短路之不良現象。 -23 - 571421
上述引腳框LF5如圖39所示，也可使用於搭載將焊接墊7 配置成一行之半導體晶片2之情形。又，搭載半導體晶片2 之晶墊部4之形狀並不限定於圓形，例如如圖4〇所示之引腳 框LF6或如圖41所示之引腳框LF?一般，也可採用使晶墊部4 之寬度寬於吊腳5b之寬度之所謂交叉式翼片構造。此時， 如圖40所示，利用將接著劑14塗敷在墊部4上之多數處，以 接著半導體晶片2，故可有效防止半導體晶片2之旋轉方向 之移位，因此，可提高晶墊部4與半導體晶片2之相對的位 置精確度。又，利用將也兼具有作為吊腳汕之一部分之機 能之晶墊部4形成較寬之寬度，也可獲得提高吊腳几之剛性 之效果。〖，在上述之交叉式翼片構造之晶墊部4,當然也 可搭載尺寸不同之多數種半導體晶片2。 (實施形態六） QFN之端子也可利用下列方法开彡# 、， 」r幻乃沄形成。百先，如圖42(a)所 示，準備例如以前述實施形能二夕m ^ ς " 一 」〜κ他小心一之圖h所示之方法製造 引腳框LF3。其次，如圖42(b)〜⑷张-^ 口 1 )(句所不，將絲網印刷用之 掩罩17疊合在引腳框Lh之背面，將钿* ㈠ ^ 3月囬71寸銅I 18a印刷在預備形 成令而子之處俊’利用丈±L齡士相I客〗父 人、牝此銅㈢1 8a而形成銅端子1 8。 、其次’如圖42(e)所示，依據前述實施形態—所說明 法’將半導體晶片2载置於晶墊部4上，接著，以金線 焊接墊7與引腳5。 〜锋 六一人 法 形 之 〜V芯一尸/T I兄 ，以膜塑樹脂成型半導體晶片2而形成封裝體3。 成在引腳5之一面之前述銅端子18之前端部::由* -24- 571421
發明說明續裒 背面突出於外側。 其後，必要時，也可利用無電解電鍍法等，對銅蠕子1 8 之表面施以S η或A u之電鍍。 依據上述本實施形態之方法，與在引腳5之/面形成假端 子1 2後，除去假端子丨2而形成焊料凸塊丨3之前述貫施形態 二之方法相比，可簡化端子形成工序。 (實施形態七）
圖44所示之QFN1係將引腳5之一端部側（接近於半導體晶 片2之側）5 a向上方彎折之例。如此一來，引腳5之一端部側 5a與半導體晶片2之主面之階差會縮小，並可降低連接引腳 5與焊接墊7之金線6之環路高度，故可薄化封裝體3之厚度 約相當於該部分之厚度。 圖45所示之QFN 1係將引腳 同時使晶墊部4保持與引腳5之一端部側化大致同高，並 面朝下方式將半導體晶片2搭載於此晶墊部4之下面側之
。如此一來，可使引腳5之一端部側“及晶墊部4之各上 與封裝體3之上面間之樹脂厚度變成極薄，故可實現封裝 3之厚度僅0 · 5 mm之超薄型q FN。 將引腳5之一端部側5 a向上方彎拆夕μ、+、 弓饰之上4方式，例如如 46及圖47所也可適用於使用將絕緣 /似4 I曰日月支 脰3 3貼在引腳5之一端部側5 a之引腳框lf ^ ^ 、.， 21情形。晶片 持3 3與半導體晶片2之接著例如可介 + 丨^者形成於曰片 持體33之單一面之接著劑丨9施行。此乂、-日片 J 囚所述之理由 可薄化封裝體3之厚度。 w -25 - 571421
圖48及圖49係表示例如使用〜或A1等熱傳導性高之材料 加熱至佈裔23構成晶片支持體之例。將加熱塗佈器Μ兼用 作為晶片支持體，可實現放熱性良好之_。&，使用如 熱塗佈器23構成晶片支持體時，如圖50所示，也可使加熱 土佈态2j之一面露出封裝體3之表面，因此，可進一步提言 放熱性。 问
又，本貫施形態係適用於具有將引腳框半蝕刻所形成之 而子8之Q FN，但並不限定於此，當然也可適用於具有利用 前述各種方法所形成之端子之QFN。 (賞施形態八） 圖5 1係表示用於製造QFN之引腳框之一部分之平面 圖，圖52係表示用此引腳框Lb製造之QFN之外觀（背面圖 之平面圖。 」
在將QFN之封裝體尺寸保持—定不變之情況下，進行多 接腳化時，端子8之間距變得極窄小，故如前述實施形態1 所使用之引腳框LFl —般，欲將端子8之寬度擴大至比引腳土 之見度更覓時，引腳框之加工非常困難。 作為其對策’如本實施形態之引腳框Us 一般，最好將端 子8之見度設定為與引腳5之寬相同。因此，可實現例如於 子8及引腳5之寬度（d)為〇‘15_〜〇.18_1、與鄰接之端子而8 之間距在與同一行之端子8之間距（p i)為〇. 5 mm 在與另一 仃之端子8之間距（P2)為0,25 mm之窄間距之超多接腳之 QFN 〇 此時，由於端子8之寬度變f ’使端子8與安裝基板之接 -26 - 571421
發明說钥繪裏 觸面積變小，而可能降低連接可靠性，故作為其補償手段 ’最好利罔延長端子8之長度’以防止面積之降低。又，由 於引腳5之寬度變窄，引腳5之強度也會降低，故最好將晶 片支持體3 3貼在引腳5之前端，利用此晶片支持體3 3支持引 腳5，以防止引腳5之變形。晶片支持體3 3如圖5 3所示，也 可設於引腳5之中途部。將端子8之寬度設定為與引腳5之寬 相同之本貫施形態之引腳框L F s如圖5 4及圖5 5所示，當然可 適用於不具有晶片支持體33之QFN。 以上已就本發明人所創見之發明，依據發明之實施形態 予以具體說明，但本發明並不僅限定於前述發明之實施形 悲，在不脫離其要旨之範圍内，當然可作種種適當之變更。 例如使用剞述貫施例一所說明之模具40同時對搭載於 一塊引腳框LF!之多數半導體晶片2施行樹脂封裝時，有時 會因引腳框1^1與模塑樹脂之熱膨脹係數差而在引腳框 發生翹曲或變形。 為了防止此現象，例如如圖56所示，在弓丨腳框lf[之外框 1分設置缝隙22時，即可有效加崎止。且利用改變包含 於構成封裝體3之模塑樹脂之填料等之量，使封裝體3之熱 膨脹係數接近於引腳框LFl之熱膨脹係數，也屬有效。、、、
又，例如如57圖所示，可利用使晶墊部4露出於封裝 之背面，以實現放熱性高之QFN1…使晶墊部4露衣 封裝體3之背面，只要在例如將板厚較厚之金屬板1〇=飼 而形成板厚較薄之引腳5及吊腳5b之際，利用光阻膜勺驾 墊部4 ’以形成板厚較厚之晶墊部4即可。 匕 -27 - (22) (22)571421 發明說钥續買 又’在前述實施形態—中’係將板厚較厚之金屬板10半 钱刻而形成板厚較薄之晶墊部4、弓I腳5及㈣5b，但在較 大尺寸之半導體晶片2搭載於板厚較薄之吊腳讣時，吊腳讣 之剛性有時會不足。作為其對策，例如㈣圖所示’不將 ^腳Μ:部分或全體施以半則，而以較厚之板厚形成 日”為有效之方法。又’此時’吊腳5b之一部分卜戈全r ) 會露出封裝體3之背面，故將此+山立、θ U飞王収） 、匕路出部分焊接於印刷電路基 板時’可提高QFN1與印刷電路基板之連接可靠性 之放熱性。 二在：實施形態中’在形成封裝體3之際，係採用將 在模具Μ上模崎及下模卿）之間之模塑成 形方法，但如圖59所示， 塑成形方法而形成封，體，：？不使用樹脂薄片41之模 之際，如圖6。(二:心此時’由模具4。取出封裝體3 如__斤$，^8二二—J分有被樹脂包覆，或 示，只要利用砂磨機等之；二有:㈣ 之樹脂溢料1後It 手段37除去端子8之表面 鍍法形成金屬層即可。Ό8之表面’利用前述印刷法或電 [發明之功效] 本案所揭示之路 功效可簡單說明:下。，父具有代表性之發明所能獲得之 由於利用將配置 部側繞接至晶 片周圍之多數引腳之各一端 屬線之長度，=近’以縮短連接引腳與晶塾部之金 s夕接腳化而使引腳之間距，即金屬線 -28 -
571421 之間隔變窄時，亦可抑制在製造工序之途中發生金屬線彼 此短路之不良現象，並增進QFN之多接腳化。 [圖式之簡單說明] 圖1係表示本發明之一實施形態之半導體裝置之外觀（表 面側）之平面圖。 圖2係表示本發明之一實施形態之半導體裝置之外觀（背 面側）之平面圖。 圖3係表示本發明之一實施形態之半導體裝置之内部構 造（表面側）之平面圖。 圖4係表示本發明之一實施形態之半導體裝置之内部構 造（背面側）之平面圖。 ~ 圖5係本發明之一實施形態之半導體裝置之剖面圖。 圖6係使用於本發明之一實施形態之半導體裝置之製造 之引腳框之全體平面圖。 圖7係圖6所示之引腳框之製造方法之要部剖面圖。 圖8係表示本發明之一實施形態之半導體裝置之製造方 法之引腳框之要部平面圖。 圖9係表示本發明之一實施形態之半導體裝置之製造方 法之引腳框之要部剖面圖。 圖1 0係表示本發明之一實施形態之半導體裝置之製造方 法之引腳框之要部平面圖。 圖1 1係表示本發明之一實施形態之半導體裝置之製造方 法之引腳框之要部剖面圖。 圖1.2係表示本發明之一實施形態之半導體裝置之製造方 -29 - (24))/H2l
法之引腳框及模1 丨片，、心X。卩剖面圖。 法2 d L表不本發明之—實施形態之半導體裝置之製冰方 '之引腳框及模具之要部剖面圖。 心方 圖1 4係表示本發明—餘 法 貝、^形態之半導體裝置之製诰 法之W腳框之要部平面圖。 衣心 法：15係表示本發明之-實施形態之半導體裝置之製造 \弓丨腳框及模具之要部剖面圖。 圖16係表示使用於本發發 萝沣 之貝施形®之丰導體裝置 …具之上模接觸於引腳框之部分之平面圖。 圖Π係表示使用於本發明發 製a ^男' %形悲之+導體裝置 模工 、左入於模腔之樹脂之流動方向 镇式的平面圖。 圖1 8係表示本發明之—f说jjy At , 貝、^形態之半導體裝置之製诰 法之引腳框之全體平面圖（表面側卜 〜 圖I 9係表示本發明之一 f絲 t貝％形恶之半導體裝置之製造 /ir之引腳框之剖面圖。 圖2 0係表示本發明之一實絲 貝砭形恶之半導體裝置之製 法之引腳框之全體平面圖（背面側）。 圖2 I係表示使用於本發明之每 乃 貝、％形悲'之半導體 之製造之引腳框之要部平面圖。 圖22係表示使用於本發明之另一每 …匕 ， 汽形恶之半導體 之製造之引腳框之要部剖面圖。 圖23係表示使用於本發明之另一廢 / & , 貝&形悲之半導體 之製造之引腳框之：製造方法之要部剖面圖。 方 方 之 之 之 方 方 造方 裝置 裝置 裝置 -30 . 571421
發明說销續頁 圖24係表示使用圖21及圖22所示之引腳框之半導體裝置 之製造方法之要部剖面圖。 圖25係表示本發明之另一實施形態之半導體裝置之製造 方法之要部剖面圖。 圖26(a)〜（e)係表示本發明之另一實施形態之半導體裝 置之製造方法之要部剖面圖。 圖27(a)、（b)係表示本發明之另一實施形態之半導體裝置 之製造方法之要部剖面圖。 圖28(a)、（b)係表示本發明之另一實施形態之半導體裝置 之製造方法之要部剖面圖。 圖29係表示本發明之另一實施形態之半導體裝置之製造 方法之要部剖面圖。 圖30係表示本發明之另一實施形態之半導體裝置之製造 方法之要部剖面圖。 圖3 1係表示本發明之另一實施形態之半導體裝置之製造 方法之要部剖面圖。 圖32係表示本發明之另一實施形態之半導體裝置之製造 方法之要部剖面圖。 圖33係表示本發明之另一實施形態之半導體裝置之製造 方法之要部剖面圖。 圖34係表示本發明之另一實施形態之半導體裝置之製造 方法之引腳框之要部平面圖。 圖3 5係表示本發明之另一實施形態之半導體裝置之製造 方法之引腳框之要部平面圖。 -31 - 571421
發明說钥繽頁 圖3 6係表示使用於本發明之另一實施形態之半導體裝置 之製造方法之引腳框之要部平面圖。 圖37係表示本發明之另一實施形態之半導體裝置之内部 構造（表面側）之平面圖。 圖3 8係表示本發明之另一實施形態之半導體裝置之製造 方法之說明圖。
圖3 9係表示本發明之另一實施形態之半導體裝置之製造 方法之引腳框之要部平面圖。 圖40係表示使用於本發明之另一實施形態之半導體裝置 之製造方法之引腳框之要部平面圖。 圖4 1係表示使用於本發明之另一實施形態之半導體裝置 之製造方法之引腳框之要部平面圖。 圖42(a)〜（e)係表示本發明之另一實施形態之半導體裝 置之製造方法之要部平面圖。 ‘
圖43係表示本發明之另一實施形態之半導體裝置之製造 方法之剖面圖。 圖44係表示本發明之另一實施形態之半導體裝置之剖面 圖。 圖45係表示本發明之另一實施形態之半導體裝置之剖面 圖。 圖46係表示本發明之另一實施形態之半導體裝置之剖面 圖。 圖4 7係表示本發明之另一實施形態之半導體裝置之剖面 圖。 -32 - 571421
發明說明繽頁· 圖48係表示本發明之另一實施形態之半導體裝置之剖面 圖。 圖49係表示本發明之另一實施形態之半導體裝置之剖面 圖。 圖50(a)、（b)係表示本發明之另一實施形態之半導體裝置 之剖面圖。
圖5 1係表示使用於本發明之另一實施形態之半導體裝置 之製造方法之引腳框之要部平面圖。 圖5 2係表示本發明之另一實施形態之半導體裝置之外觀 (背面側）之平面圖。 圖53係表示使用於本發明之另一實施形態之半導體裝置 之製造方法之引腳框之要部平面圖。 圖54係表示使用於本發明之另一實施形態之半導體裝置 之製造方法之引腳框之要部平面圖。
圖55係表示使用於本發明之另一實施形態之半導體裝置 之製造方法之引腳框之要部平面圖。 圖5 6係表示使用於本發明之另一實施形態之半導體裝置 之製造之引腳框之要部平面圖。 圖57係表示本發明之另一實施形態之半導體裝置之剖面 圖。 圖5 8係表示本發明之另一實施形態之半導體裝置之内部 構造（背面侧）之平面圖。 圖59係表示本發明之另一實施形態之半導體裝置之製造 方法之模具之要部剖面圖。 -33 - 571421
發明說，繽頁 圖60(a)、（b)係由模具取出之封裝體之局部放大剖面圖。 圖6 1係表示本發明之另一實施形態之半導體裝置之製造 方法之剖面圖。 圖式代表符號說明 1 QFN 2 半導體晶片 3 封裝體 4 晶墊部 5 引腳 5 a 引腳之一端部侧 5b 吊腳 5 c 引腳之他端部側 6 金線 7 焊接墊 8 端子 9 焊料層 10 金屬板 11 光阻膜 12 假端子 12a 聚醯亞胺樹脂 13 焊料凸塊 13a 焊料膏 14 接著劑 15 、 16 、 17 掩罩
-34 - 571421 (29) 18a 銅膏 18 銅端子 19 接著劑 20 金屬板 2 1 端子 22 缝隙 23 加熱塗佈器 30A、30B 夾具 3 1 溝 32 突起部 ο ο JO 晶片支持體 34 假端子 35 凹部 36 端子 37 溢料除去手 40 模具 40Α 上模 40Β 下模 41 樹脂薄片 42 排氣孔 Cl 〜c24 模腔 d 端子直徑 DC「〜DC8 假膜腔 G!〜G丨6 澆口 -35 - 571421
L 切 LF丨〜LF8 引 Pi 端 P2 端 P3 引 割線 腳框 子間間距（同一行） 子間間距（不同行） 腳端部侧前端間距
-36 -

Claims (1)

  1. 571421 拾、申請專利範圍 1. -種半導體裝置，其特徵在於包含半導體晶片、搭載前 述半導體晶片之晶墊部、配置於前述半導體晶片之周圍 之夕數引腳、電性連接前述半導體晶片與前述引腳之多 放至屬、、泉岔封前述半導體晶片、前述晶墊部、前述多 數I1魏前述多數金屬線之封裝體， 心引〜夕數引腳係形成使接近於前述半導體晶片之一端 丨側之間距小於位於與前述一端部侧相反侧之他端部 侧之間距， 多匕 ^ ^ JSL- — ^ K 瓶 2. 4. 之月面向外部突出之端子者。 # 1 =、寸利軏圍第1項之半導體裝置，其中前述端子係 者則处引_之—部分由前述封裝體之背面向外部突出 由显於d:圍弟1項之半導體裝置，其中前述端子係 丄弓丨腳之導電材料所構成者。 :背：：：範圍第1項之半導體裝置，其中前述晶墊部 述！裝體之背面露出於外部者。 沪著前乾圍弟丨項之半導體裝置，其中前述蠕子俜 裝體之各邊以鑛齒狀各配置2行者。 聊中，:前：圍：5項之半導體裝置，其中前述多數引 之寬係寬:^二配置在接近於—端部侧之一方之引腳 之弓丨腳之寬二…子配置在接近於他端部側之-方 571421 申講·蓴刹範圍繽買 7. 如申請專利範圍第1項之半導體裝置，其中前述晶墊部 之面積係小於前述半導體晶片之面積者。 8. 如申請專利範圍第1項之半導體裝置，其中前述晶墊部 係被多數吊腳所支持者。 9. 一種半導體裝置，其特徵在於包含半導體晶片、搭載前 述半導體晶片之薄片狀之晶片支持體、配置於前述半導 體晶片之周圍之多數引腳、電性連接前述半導體晶片與 前述引腳之多數金屬線、密封前述半導體晶片、前述晶 片支持體、前述多數引腳及前述多數金屬線之封裝體， 前述多數引腳係形成使接近於前述半導體晶片之一端 部侧之間距小於位於與前述一端部侧相反側之他端部 側之間距， 在前述多數引腳之各引腳，電性連接由前述封裝體之 背面向外部突出之端子者。 10. 如申請專利範圍第9項之半導體裝置，其中前述晶片支 持體係被前述多數引腳所支持者。 1 1. 一種半導體裝置之製造方法，其特徵在於製造半導體裝 置，其係包含半導體晶片、搭載前述半導體晶片之晶墊 部、配置於前述半導體晶片之周圍之多數引腳、電性連 接前述半導體晶片與前述引腳之多數金屬線、密封前述 半導體晶片、前述晶墊部、前述多數引腳及前述多數金 屬線之封裝體者；且包含 (a)反覆形成含前述晶墊部與前述多數引腳之圖案，並 準備在前述多數引腳之各引腳之一面形成向垂直於前 571421 申請__範園繽翼 ^ 面之方向突出之端子之引腳框之工序； 立在形成於前述引腳框之前述多數晶墊部之各晶墊 j搭载半導體晶片，利用金屬線連接前述半導體晶片與 珂述彳丨腳之一部分之工序； (C)準備含上模與下模之模具，以樹㈣片包覆前述下 杲之表面後，將削述引腳框載置於前述樹脂薄片上，而 成方、刖述引腳之一面之丽述端子與前述樹脂薄片 相接觸之工序； (d)以刖述上杈與前述下模夾定前述樹脂薄片及前述 引腳框’並使前述端子之前端部分嵌人前述樹脂薄片内 之工序； &(、e)將樹脂注入前述上模與前述下模之間隙，藉以密封 則^導體晶片、前述晶塾部、前述引腳及前述金屬線 —同％形成使刖述端子之前端部分突出外侧之多數封裝 體後，由前述模具取出前述引腳框之工序；及 刀。·1如述引腳框而將前述多數封裝體分離成 獨立個體之工序者。 12. γ請專利範圍第11項之半導體裝置之製造方法，其中 月,J述⑷工序係包含以光阻掩罩包覆金屬板之-部分，利 I蝕刻未被刖述光阻掩罩包覆之區域之金屬板，以形成 k >數引腳' w述晶塾部及前述端子之工序者。 1申請專利範圍第12項之半導體裝置之製造方法，其中 〜夕數引腳ίτ、利用將前述金屬板施以半#、刻所形成 者。 571421
    14. 如申請專利範圍第11項之半導體裝置之製造方法，其中 别述多數引腳係形成在前述晶墊部侧之間距小於在位 於與前述晶墊部相反側之端部之間距者。
    15. 如申請專利範圍第n項之半導體裝置之製造方法，其中 刖述（a)工序所形成之前述端子為假端子，且進/资包含 在別述（e)工序後，除去前述假端子之工序；及在除杳前 述2端子之區域之前述引腳之一面，形成前端部分突出 於刚遂封裝體之外側之端子之工序者。 16. 如1請專利範圍第12項之半導體裝置之製造方法，其中 在刚述（a)工序中蝕刻前述金屬板之前述 晶墊部之區域之前述金屬板者。 ’赠 17. 如:請專利範圍第12項之半導體裝置之製法方法，其中 在前述U)工序中姓刻前述金屬板之際，不^刻在前述⑷ 工序中接觸於前述模具之區域之前述金屬板者。 18. 如申請專利範圍第11IM之半導 在前述弓！腳框之外框設有縫隙者。m
    19. =申請專利範圍第11項之半導體裝置之製洁方法，i中 ^端子麵著料封裝體之各邊㈣餘各配置2行 ^明寸利轭圍第19項之半導體裝置之製造方法 前料數引腳中，將前述端子配置在接近於前心 曰方之引腳之見係寬於將前述端子配置在離& 晶墊部之一方之？丨腳之寬者。 + 21.如申請專利範圍第"項之半導體裝置之製造方法 571421 申請蓴_範_繽買 在前述（b)工序中支持前述引腳框之模具係在與前述端 子之前端相對向之處設有溝者。 22.如申請專利範圍第1 1項之半導體裝置之製造方法，其中 在前述（c)工序中使用之前述模具係構成使前述上模接 觸於前述引腳框之外框部分及前述引腳之連接部分，並 將其外之區域利用作為注入前述樹脂之模腔之構造者。 23 .如申請專利範圍第1項之半導體裝置，其中前述多數引 腳之前述一端部側之長度交互有差異者。 24. 如申請專利範圍第23項之半導體裝置，其中形成於前述 半導體晶片之主面之焊接墊係沿著前述半導體晶片之 邊以鋸齒狀各配置2行者。 25. 如申請專利範圍第1或9項之半導體裝置，其中前述多數 引腳之前述一端部侧係向前述封裝體之厚度方向被彎 折者。 26. 如申請專利範圍第1或9項之半導體裝置，其中前述端子 之直徑係大於前述引腳之寬者。 2 7.如申請專利範圍第1或9項之半導體裝置，其中前述端子 之直徑係相同於前述引腳之寬者。 2 8.如申請專利範圍第9項之半導體裝置，其中前述晶片支 持體係加熱塗佈器者。
TW091124700A 2001-12-14 2002-10-24 Semiconductor device and method of manufacturing the same TW571421B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001381427 2001-12-14
JP2002291975A JP4173346B2 (ja) 2001-12-14 2002-10-04 半導体装置

Publications (1)

Publication Number Publication Date
TW571421B true TW571421B (en) 2004-01-11

Family

ID=26625065

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091124700A TW571421B (en) 2001-12-14 2002-10-24 Semiconductor device and method of manufacturing the same

Country Status (5)

Country Link
US (3) US6809405B2 (zh)
JP (1) JP4173346B2 (zh)
KR (1) KR20030051222A (zh)
CN (1) CN1424757A (zh)
TW (1) TW571421B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI382509B (zh) * 2008-07-02 2013-01-11 Powertech Technology Inc 無外接腳式半導體封裝構造
TWI603448B (zh) * 2010-05-27 2017-10-21 星科金朋有限公司 具有多列導線的積體電路封裝系統及其製造方法

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2383874T3 (es) * 2001-07-09 2012-06-27 Sumitomo Metal Mining Company Limited Procedimiento para la fabricación de un soporte de conexión
CN101447438B (zh) * 2001-12-14 2010-12-01 瑞萨电子株式会社 半导体器件的制造方法
JP2004214233A (ja) * 2002-12-26 2004-07-29 Renesas Technology Corp 半導体装置およびその製造方法
JP2004253706A (ja) * 2003-02-21 2004-09-09 Seiko Epson Corp リードフレーム、半導体チップのパッケージング部材、半導体装置の製造方法、及び、半導体装置
TWI233674B (en) * 2003-07-29 2005-06-01 Advanced Semiconductor Eng Multi-chip semiconductor package and manufacturing method thereof
JP4319892B2 (ja) * 2003-11-07 2009-08-26 株式会社巴川製紙所 半導体装置製造用接着シート及び半導体装置の製造方法
JP4241408B2 (ja) * 2004-01-28 2009-03-18 株式会社デンソー 半導体装置およびその製造方法
US20050248041A1 (en) * 2004-05-05 2005-11-10 Atm Technology Singapore Pte Ltd Electronic device with high lead density
US7332817B2 (en) * 2004-07-20 2008-02-19 Intel Corporation Die and die-package interface metallization and bump design and arrangement
WO2006022024A1 (ja) * 2004-08-24 2006-03-02 Renesas Technology Corp. 半導体装置の製造方法
US7256479B2 (en) * 2005-01-13 2007-08-14 Fairchild Semiconductor Corporation Method to manufacture a universal footprint for a package with exposed chip
US7364945B2 (en) 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US7354800B2 (en) 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
US7456088B2 (en) 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7768125B2 (en) 2006-01-04 2010-08-03 Stats Chippac Ltd. Multi-chip package system
US7675157B2 (en) * 2006-01-30 2010-03-09 Marvell World Trade Ltd. Thermal enhanced package
US7947534B2 (en) * 2006-02-04 2011-05-24 Stats Chippac Ltd. Integrated circuit packaging system including a non-leaded package
US7750482B2 (en) 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US8704349B2 (en) 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US7863737B2 (en) * 2006-04-01 2011-01-04 Stats Chippac Ltd. Integrated circuit package system with wire bond pattern
JP4799385B2 (ja) * 2006-05-11 2011-10-26 パナソニック株式会社 樹脂封止型半導体装置の製造方法およびそのための配線基板
MY142210A (en) * 2006-06-05 2010-11-15 Carsem M Sdn Bhd Multiple row exposed leads for mlp high density packages
JP5622347B2 (ja) * 2006-08-09 2014-11-12 セイコーエプソン株式会社 慣性センサ装置
JP2008135719A (ja) * 2006-10-31 2008-06-12 Sanyo Electric Co Ltd 半導体モジュール、半導体モジュールの製造方法および携帯機器
US7608482B1 (en) * 2006-12-21 2009-10-27 National Semiconductor Corporation Integrated circuit package with molded insulation
JP4757790B2 (ja) * 2006-12-22 2011-08-24 富士通コンポーネント株式会社 半導体素子の実装構造及びプリント回路基板
US7777310B2 (en) * 2007-02-02 2010-08-17 Stats Chippac Ltd. Integrated circuit package system with integral inner lead and paddle
JP2008294278A (ja) * 2007-05-25 2008-12-04 Fujitsu Microelectronics Ltd 半導体装置、リードフレーム、及び半導体装置の実装構造
JP2009147032A (ja) * 2007-12-13 2009-07-02 Panasonic Corp 半導体装置および光ピックアップ装置
US20090230524A1 (en) * 2008-03-14 2009-09-17 Pao-Huei Chang Chien Semiconductor chip package having ground and power regions and manufacturing methods thereof
JP4531830B2 (ja) * 2008-08-15 2010-08-25 特新光電科技股▲分▼有限公司 Ｌｅｄリードフレームの製造方法
US20100044850A1 (en) 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
SG172749A1 (en) * 2009-03-06 2011-08-29 Kaixin Inc Leadless integrated circuit package having high density contacts
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US8571229B2 (en) * 2009-06-03 2013-10-29 Mediatek Inc. Semiconductor device
JP2011003764A (ja) * 2009-06-19 2011-01-06 Renesas Electronics Corp 半導体装置及びその製造方法
US8860193B2 (en) * 2010-06-04 2014-10-14 Marvell World Trade Ltd. Pad configurations for an electronic package assembly
JP5479247B2 (ja) 2010-07-06 2014-04-23 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9263374B2 (en) * 2010-09-28 2016-02-16 Dai Nippon Printing Co., Ltd. Semiconductor device and manufacturing method therefor
JP5333402B2 (ja) * 2010-10-06 2013-11-06 三菱電機株式会社 半導体装置の製造方法
KR101119305B1 (ko) 2010-12-21 2012-03-16 삼성전기주식회사 더미영역을 포함하는 반도체 패키지 기판
US9431317B2 (en) * 2013-11-07 2016-08-30 Cisco Technology, Inc. Power doubler amplifier module with improved solder coverage between a heat sink and a thermal pad of a circuit package
WO2015111623A1 (ja) * 2014-01-22 2015-07-30 大日本印刷株式会社 リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法
JP6607429B2 (ja) * 2014-01-22 2019-11-20 大日本印刷株式会社 リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法
DE102014103942B4 (de) 2014-03-21 2024-05-02 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines Gehäuses für ein elektronisches Bauelement und eines elektronischen Bauelements, Gehäuse für ein elektronisches Bauelement und elektronisches Bauelement
JP6428013B2 (ja) * 2014-07-16 2018-11-28 大日本印刷株式会社 リードフレーム部材およびその製造方法、ならびに半導体装置およびその製造方法
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
US9496206B2 (en) 2015-04-10 2016-11-15 Texas Instruments Incorporated Flippable leadframe for packaged electronic system having vertically stacked chips and components
US9847281B2 (en) * 2015-06-30 2017-12-19 Stmicroelectronics, Inc. Leadframe package with stable extended leads
US20170011989A1 (en) * 2015-07-07 2017-01-12 Infineon Technologies Ag Lead frame including u-notch
JP6840466B2 (ja) 2016-03-08 2021-03-10 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージ及び半導体パッケージの製造方法
JP6842649B2 (ja) * 2016-09-02 2021-03-17 大日本印刷株式会社 リードフレームおよび半導体装置
JP7182374B2 (ja) * 2017-05-15 2022-12-02 新光電気工業株式会社 リードフレーム及びその製造方法
US20190221502A1 (en) * 2018-01-17 2019-07-18 Microchip Technology Incorporated Down Bond in Semiconductor Devices
DE102019202716B4 (de) 2019-02-28 2020-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Flex-folien-package mit coplanarer topologie für hochfrequenzsignale und verfahren zum herstellen eines derartigen flex-folien-packages
DE102019202721B4 (de) 2019-02-28 2021-03-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. 3d-flexfolien-package
DE102019202718B4 (de) 2019-02-28 2020-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Dünnes Dual-Folienpackage und Verfahren zum Herstellen desselben
DE102019202717A1 (de) * 2019-02-28 2020-09-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Flex-folien-package mit erweiterter topologie
DE102019202715A1 (de) 2019-02-28 2020-09-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Folienbasiertes package mit distanzausgleich
US11584638B2 (en) * 2020-07-30 2023-02-21 Invensense, Inc. Reducing delamination in sensor package
US11869831B2 (en) * 2020-10-08 2024-01-09 Mediatek Inc. Semiconductor package with improved board level reliability

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04196349A (ja) * 1990-11-28 1992-07-16 Hitachi Ltd 樹脂封止型半導体装置
JPH04152646A (ja) * 1990-10-17 1992-05-26 Mitsubishi Electric Corp 半導体集積回路
JP2962586B2 (ja) * 1991-03-05 1999-10-12 新光電気工業株式会社 半導体装置とその製造方法及びこれに用いる接合体
JPH0595078A (ja) * 1991-10-02 1993-04-16 Nec Corp 樹脂封止型半導体装置
EP0588481A1 (en) * 1992-08-17 1994-03-23 American Microsystems, Incorporated Bond pad layouts for integrated circuit semiconductor dies and forming methods
CN1117395C (zh) * 1994-03-18 2003-08-06 日立化成工业株式会社 半导体组件的制造方法及半导体组件
JPH08139259A (ja) 1994-09-16 1996-05-31 Dainippon Printing Co Ltd リードフレームとリードフレーム部材、およびそれらを用いた表面実装型半導体装置
JPH08330494A (ja) * 1995-05-31 1996-12-13 Hitachi Constr Mach Co Ltd 半導体装置の製造方法及び半導体装置
JPH10200036A (ja) * 1996-12-20 1998-07-31 Texas Instr Inc <Ti> 集積回路用超ファインピッチリードフレーム
JP3093704B2 (ja) 1996-12-24 2000-10-03 松下電子工業株式会社 リードフレーム，リードフレームの製造方法，半導体装置及び半導体装置の製造方法
KR100237051B1 (ko) * 1996-12-28 2000-01-15 김영환 버텀리드 반도체 패키지 및 그 제조 방법
JP2956659B2 (ja) * 1997-06-27 1999-10-04 日本電気株式会社 半導体装置およびそのリードフレーム
JPH1174404A (ja) * 1997-08-28 1999-03-16 Nec Corp ボールグリッドアレイ型半導体装置
JP4030200B2 (ja) 1998-09-17 2008-01-09 株式会社ルネサステクノロジ 半導体パッケージおよびその製造方法
JP3686267B2 (ja) * 1998-10-28 2005-08-24 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2000286372A (ja) 1999-03-30 2000-10-13 Sanyo Electric Co Ltd 半導体装置の製造方法
JP3897478B2 (ja) * 1999-03-31 2007-03-22 松下電器産業株式会社 樹脂封止型半導体装置の製造装置及びその製造方法
JP3578262B2 (ja) * 1999-04-06 2004-10-20 日東電工株式会社 半導体チップの樹脂封止方法及びその方法に使用する離型フィルム
JP3518412B2 (ja) 1999-04-22 2004-04-12 松下電器産業株式会社 トレイフィーダによる電子部品の供給方法
JP2000307221A (ja) 1999-04-26 2000-11-02 Sony Corp 電子部品の電気接続方法
JP3780122B2 (ja) 1999-07-07 2006-05-31 株式会社三井ハイテック 半導体装置の製造方法
WO2001011677A1 (fr) * 1999-08-09 2001-02-15 Rohm Co., Ltd. Procede de fabrication d'un dispositif a semi-conducteur
JP3062192B1 (ja) * 1999-09-01 2000-07-10 松下電子工業株式会社 リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法
JP2001077287A (ja) * 1999-09-06 2001-03-23 Mitsubishi Electric Corp 半導体装置用リードフレーム
KR20010037254A (ko) * 1999-10-15 2001-05-07 마이클 디. 오브라이언 반도체패키지
JP2001185567A (ja) * 1999-12-22 2001-07-06 Hitachi Ltd 半導体装置およびその製造方法
JP3878781B2 (ja) 1999-12-27 2007-02-07 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3732987B2 (ja) * 1999-12-28 2006-01-11 株式会社ルネサステクノロジ 半導体装置
JP3786339B2 (ja) * 2000-03-23 2006-06-14 株式会社三井ハイテック 半導体装置の製造方法
JP2001313363A (ja) * 2000-05-01 2001-11-09 Rohm Co Ltd 樹脂封止型半導体装置
US6611047B2 (en) * 2001-10-12 2003-08-26 Amkor Technology, Inc. Semiconductor package with singulation crease
JP2004214233A (ja) * 2002-12-26 2004-07-29 Renesas Technology Corp 半導体装置およびその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI382509B (zh) * 2008-07-02 2013-01-11 Powertech Technology Inc 無外接腳式半導體封裝構造
TWI603448B (zh) * 2010-05-27 2017-10-21 星科金朋有限公司 具有多列導線的積體電路封裝系統及其製造方法

Also Published As

Publication number Publication date
KR20030051222A (ko) 2003-06-25
US20060240600A1 (en) 2006-10-26
US20040232528A1 (en) 2004-11-25
JP2003243600A (ja) 2003-08-29
US7160759B2 (en) 2007-01-09
US6809405B2 (en) 2004-10-26
US20030111717A1 (en) 2003-06-19
JP4173346B2 (ja) 2008-10-29
CN1424757A (zh) 2003-06-18
US7507606B2 (en) 2009-03-24

Similar Documents

Publication Publication Date Title
TW571421B (en) Semiconductor device and method of manufacturing the same
JP3780122B2 (ja) 半導体装置の製造方法
JP3619773B2 (ja) 半導体装置の製造方法
JP3420057B2 (ja) 樹脂封止型半導体装置
US6638790B2 (en) Leadframe and method for manufacturing resin-molded semiconductor device
JP3207738B2 (ja) 樹脂封止型半導体装置及びその製造方法
JP3704304B2 (ja) リードフレーム及びその製造方法並びに該リードフレームを用いた半導体装置の製造方法
JP2006516812A (ja) 部分的にパターン形成されたリードフレームならびに半導体パッケージングにおけるその製造および使用方法
TW200416969A (en) Taped lead frames and methods of making and using the same in semiconductor packaging
TW201145411A (en) Semiconductor package without carrier and method of fabricating the same
WO2006105733A1 (en) Package structure with flat bumps for electronic device and method of manufacture the same
TWI455213B (zh) 無外引腳封裝結構及其製作方法
TW201030919A (en) Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof
JP3470111B2 (ja) 樹脂封止型半導体装置の製造方法
TW201131673A (en) Quad flat no-lead package and method for forming the same
JP4547086B2 (ja) 半導体装置
JP2007287762A (ja) 半導体集積回路素子とその製造方法および半導体装置
JP2004363365A (ja) 半導体装置及びその製造方法
JP4243270B2 (ja) 半導体装置の製造方法
JP4987041B2 (ja) 半導体装置の製造方法
JPH05218129A (ja) 樹脂封止型半導体装置及びその製造方法
TWI501371B (zh) A wiring member for a semiconductor device, a composite wiring member for a semiconductor device, and a resin-sealed type semiconductor device
TWI387080B (zh) 四方扁平無引腳之半導體封裝結構及封裝方法
JP2001077285A (ja) リードフレームとそれを用いた樹脂封止型半導体装置の製造方法
JP5587464B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees