TW419725B - Method for manufacturing SOI wafer and SOI wafer - Google Patents

Method for manufacturing SOI wafer and SOI wafer Download PDF

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Publication number
TW419725B
TW419725B TW088109014A TW88109014A TW419725B TW 419725 B TW419725 B TW 419725B TW 088109014 A TW088109014 A TW 088109014A TW 88109014 A TW88109014 A TW 88109014A TW 419725 B TW419725 B TW 419725B
Authority
TW
Taiwan
Prior art keywords
soi
wafer
bonding
soi layer
oxide film
Prior art date
Application number
TW088109014A
Other languages
English (en)
Chinese (zh)
Inventor
Katsuo Yoshizawa
Masatake Nakano
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Application granted granted Critical
Publication of TW419725B publication Critical patent/TW419725B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
TW088109014A 1998-06-04 1999-06-01 Method for manufacturing SOI wafer and SOI wafer TW419725B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15608898A JP3635200B2 (ja) 1998-06-04 1998-06-04 Ｓｏｉウェーハの製造方法

Publications (1)

Publication Number Publication Date
TW419725B true TW419725B (en) 2001-01-21

Family

ID=15620052

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088109014A TW419725B (en) 1998-06-04 1999-06-01 Method for manufacturing SOI wafer and SOI wafer

Country Status (5)

Country Link
US (1) US6534384B2 (ko)
EP (1) EP0964436A3 (ko)
JP (1) JP3635200B2 (ko)
KR (1) KR100606228B1 (ko)
TW (1) TW419725B (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102034687A (zh) * 2009-09-28 2011-04-27 S.O.I.Tec绝缘体上硅技术公司 键合和转移层的工艺
CN115799273A (zh) * 2022-12-21 2023-03-14 中环领先半导体材料有限公司 一种绝缘体上硅晶圆及制备方法、半导体装置

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US6984571B1 (en) * 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
JP2003078115A (ja) * 2001-08-30 2003-03-14 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハのレーザーマーク印字方法、及び、ｓｏｉウェーハ
JP2004235478A (ja) * 2003-01-30 2004-08-19 Sumitomo Mitsubishi Silicon Corp 貼り合わせｓｏｉ基板およびその製造方法
JP4066881B2 (ja) * 2003-05-21 2008-03-26 信越半導体株式会社 表面処理方法、シリコンエピタキシャルウェーハの製造方法及びシリコンエピタキシャルウェーハ
JP4677707B2 (ja) * 2003-05-30 2011-04-27 セイコーエプソン株式会社 電気光学装置用薄膜トランジスタアレイ基板の製造方法
KR101008224B1 (ko) 2003-09-29 2011-01-17 매그나칩 반도체 유한회사 실리콘 온 인슐레이터 웨이퍼를 이용한 고전압 씨모스소자 및 그 제조방법
FR2880184B1 (fr) * 2004-12-28 2007-03-30 Commissariat Energie Atomique Procede de detourage d'une structure obtenue par assemblage de deux plaques
CN101124657B (zh) * 2005-02-28 2010-04-14 信越半导体股份有限公司 贴合晶圆的制造方法及贴合晶圆
JP5122731B2 (ja) * 2005-06-01 2013-01-16 信越半導体株式会社 貼り合わせウェーハの製造方法
JP4839818B2 (ja) * 2005-12-16 2011-12-21 信越半導体株式会社 貼り合わせ基板の製造方法
JP5292810B2 (ja) 2005-12-19 2013-09-18 信越半導体株式会社 Ｓｏｉ基板の製造方法
FR2899594A1 (fr) 2006-04-10 2007-10-12 Commissariat Energie Atomique Procede d'assemblage de substrats avec traitements thermiques a basses temperatures
JP4858692B2 (ja) * 2006-06-22 2012-01-18 日本電気株式会社 チップ積層型半導体装置
US8586512B2 (en) * 2007-05-10 2013-11-19 Halliburton Energy Services, Inc. Cement compositions and methods utilizing nano-clay
US20090004865A1 (en) * 2007-06-29 2009-01-01 Kastenmeier Bernd E E Method for treating a wafer edge
EP2075830A3 (en) * 2007-10-11 2011-01-19 Sumco Corporation Method for producing bonded wafer
FR2935536B1 (fr) * 2008-09-02 2010-09-24 Soitec Silicon On Insulator Procede de detourage progressif
FR2935535B1 (fr) * 2008-09-02 2010-12-10 S O I Tec Silicon On Insulator Tech Procede de detourage mixte.
EP2200077B1 (en) * 2008-12-22 2012-12-05 Soitec Method for bonding two substrates
FR2954585B1 (fr) 2009-12-23 2012-03-02 Soitec Silicon Insulator Technologies Procede de realisation d'une heterostructure avec minimisation de contrainte
FR2955697B1 (fr) * 2010-01-25 2012-09-28 Soitec Silicon Insulator Technologies Procede de recuit d'une structure
FR2957189B1 (fr) 2010-03-02 2012-04-27 Soitec Silicon On Insulator Procede de realisation d'une structure multicouche avec detourage post meulage.
FR2961630B1 (fr) 2010-06-22 2013-03-29 Soitec Silicon On Insulator Technologies Appareil de fabrication de dispositifs semi-conducteurs
FR2962141A1 (fr) * 2010-06-30 2012-01-06 Soitec Silicon On Insulator Technologies Procédé de désoxydation d'une structure multicouche a l'acide fluorhydrique
US8310031B2 (en) 2010-07-30 2012-11-13 Memc Electronic Materials, Inc. Semiconductor and solar wafers
US20120028555A1 (en) 2010-07-30 2012-02-02 Memc Electronic Materials, Inc. Grinding Tool For Trapezoid Grinding Of A Wafer
US20120028439A1 (en) 2010-07-30 2012-02-02 Memc Electronic Materials, Inc. Semiconductor And Solar Wafers And Method For Processing Same
US8338266B2 (en) 2010-08-11 2012-12-25 Soitec Method for molecular adhesion bonding at low pressure
FR2964193A1 (fr) 2010-08-24 2012-03-02 Soitec Silicon On Insulator Procede de mesure d'une energie d'adhesion, et substrats associes
US20120129318A1 (en) * 2010-11-24 2012-05-24 Semiconductor Energy Laboratory Co., Ltd. Atmospheric pressure plasma etching apparatus and method for manufacturing soi substrate
FR2969373B1 (fr) * 2010-12-20 2013-07-19 St Microelectronics Crolles 2 Procede d'assemblage de deux plaques et dispositif correspondant
US9393669B2 (en) * 2011-10-21 2016-07-19 Strasbaugh Systems and methods of processing substrates
US9610669B2 (en) 2012-10-01 2017-04-04 Strasbaugh Methods and systems for use in grind spindle alignment
US9457446B2 (en) 2012-10-01 2016-10-04 Strasbaugh Methods and systems for use in grind shape control adaptation
CN104733300B (zh) * 2013-12-23 2018-09-25 中芯国际集成电路制造(上海)有限公司 一种键合晶片的减薄方法
KR20180090494A (ko) * 2017-02-03 2018-08-13 삼성전자주식회사 기판 구조체 제조 방법
CN114883186B (zh) * 2022-07-11 2022-10-18 成都功成半导体有限公司 基于临时键合的晶圆背面加工方法及晶圆

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JPH04302160A (ja) * 1991-03-29 1992-10-26 Fujitsu Ltd 半導体装置の製造方法
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JPH06163341A (ja) * 1992-11-18 1994-06-10 Fujitsu Ltd 半導体基板の製造方法
JP3352129B2 (ja) 1992-12-04 2002-12-03 株式会社東芝 半導体基板の製造方法
JP3542376B2 (ja) 1994-04-08 2004-07-14 キヤノン株式会社 半導体基板の製造方法
US5494849A (en) * 1995-03-23 1996-02-27 Si Bond L.L.C. Single-etch stop process for the manufacture of silicon-on-insulator substrates
JPH08274285A (ja) * 1995-03-29 1996-10-18 Komatsu Electron Metals Co Ltd Ｓｏｉ基板及びその製造方法
KR0168348B1 (ko) * 1995-05-11 1999-02-01 김광호 Soi 기판의 제조방법
JPH08330553A (ja) 1995-05-29 1996-12-13 Hitachi Ltd Ｓｏｉウエハおよびそれを用いた半導体集積回路装置の製造方法
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JP3480480B2 (ja) 1996-03-06 2003-12-22 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102034687A (zh) * 2009-09-28 2011-04-27 S.O.I.Tec绝缘体上硅技术公司 键合和转移层的工艺
CN115799273A (zh) * 2022-12-21 2023-03-14 中环领先半导体材料有限公司 一种绝缘体上硅晶圆及制备方法、半导体装置

Also Published As

Publication number Publication date
EP0964436A2 (en) 1999-12-15
JPH11354760A (ja) 1999-12-24
US20010055863A1 (en) 2001-12-27
JP3635200B2 (ja) 2005-04-06
EP0964436A3 (en) 2000-10-18
KR20000005859A (ko) 2000-01-25
US6534384B2 (en) 2003-03-18
KR100606228B1 (ko) 2006-07-28

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