TW202034468A - 內埋元件封裝結構、內埋式面封裝基板及其製造方法 - Google Patents
內埋元件封裝結構、內埋式面封裝基板及其製造方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000010410 layer Substances 0.000 claims abstract description 239
- 239000012792 core layer Substances 0.000 claims abstract description 79
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 59
- 229910052802 copper Inorganic materials 0.000 claims description 50
- 239000010949 copper Substances 0.000 claims description 50
- 238000004806 packaging method and process Methods 0.000 claims description 29
- 239000003989 dielectric material Substances 0.000 claims description 24
- 239000003365 glass fiber Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 5
- 239000011889 copper foil Substances 0.000 description 9
- 239000003292 glue Substances 0.000 description 9
- 238000009826 distribution Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000013461 design Methods 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 5
- 238000005452 bending Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005094 computer simulation Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
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Abstract
一種內埋元件封裝結構,包括一線路基板、一內埋元件以及一應力抵消層。線路基板具有一核心層以及一非對稱線路結構,核心層具有一第一厚度。內埋元件設置於核心層中。應力抵消層設置於核心層的一側,應力抵消層具有一第二厚度,第二厚度介於4~351微米之間。
Description
本發明是有關於一種元件封裝結構及其製造方法,且特別是有關於一種內埋元件封裝結構、內埋式面封裝基板及其製造方法。
在系統級封裝結構中,將半導體晶片埋入封裝基板中的內埋元件技術(Semiconductor Embedded in SUBstrate,簡稱SESUB),因為具有降低封裝基板產品受到雜訊干擾及產品尺寸減小的優點,近年來已成為本領域製造商的研發重點。為了提高生產的良率,內埋元件必須固定在線路基板的核心層內,以利於後續製作的圖案化導電層能與內埋元件電性連接。
另外,為了減少線路基板的翹曲量,線路基板於內埋元件的上方及下方設置相同數量的導電層,因而線路基板的用銅量增加而導致生產成本增加。
本發明係有關於一種內埋元件封裝結構、內埋式面封裝基板及其製造方法,可減少生產成本並可減少條狀基板的翹曲量。
根據本發明之一方面,提出一種內埋元件封裝結構,包括一線路基板、一內埋元件以及一應力抵消層。線路基板具有一核心層以及一非對稱線路結構,核心層具有一第一厚度。內埋元件設置於核心層中。應力抵消層設置於核心層的一側,應力抵消層具有一第二厚度,第二厚度介於4~351微米之間。
根據本發明之一方面,提出一種內埋式面封裝基板,包括複數個線路基板單元、複數個內埋元件以及一應力抵消層。各線路基板單元具有一核心層以及一非對稱線路結構,核心層具有一第一厚度。此些內埋元件設置於此些線路基板單元的核心層中。應力抵消層設置於此些線路基板單元的一側,其中應力抵消層具有一第二厚度,內埋式面封裝基板的翹曲量小於5mm。
根據本發明之一方面,提出一種內埋元件封裝結構的製造方法,包括設置一應力抵消層於一核心層的一側,核心層具有一第一厚度,應力抵消層具有一第二厚度。將一電子元件設置於核心層中。形成一非對稱的線路結構於電子元件的上方及下方。
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式詳細說明如下:
以下係提出實施例進行詳細說明,實施例僅用以作為範例說明,並非用以限縮本發明欲保護之範圍。以下是以相同/類似的符號表示相同/類似的元件做說明。以下實施例中所提到的方向用語,例如:上、下、左、右、前或後等,僅是參考所附圖式的方向。因此,使用的方向用語是用來說明並非用來限制本發明。
依照本發明之一實施例,提出一種內埋元件封裝結構,用以改善非對稱線路結構於內埋元件的上方及下方產生一非對稱的應力分布,因而可解決面封裝基板(panel substrate)翹曲的問題。
非對稱線路結構為在內埋元件的上方及下方的導電層的數量不同,例如上方導電層為2層或2層以上/下方導電層為1層(以2L+1L表示)、上方導電層為1層/下方導電層為2層或2層以上(以1L+2L表示)、上方導電層為2層或2層以上/沒有下方導電層(以2L表示)、上方導電層為1層/沒有下方導電層(以1L表示)或是其他種組合。
上述內容只是示意性舉例一二,本發明對此不加以限制。請參照第1圖及第2圖所列的組合態樣,非對稱線路結構的上方導電層及下方導電層的數量可為2L+1L、1L+2L、2L、1L等至少四組非對稱組合之一,且不同態樣的非對稱線路結構對於面封裝基板造成的翹曲量也不同,因此,本實施例根據不同組合的非對稱線路結構來量身訂製不同厚度的應力抵消層,以有效抑制面封裝基板的翹曲量,使其小於5mm。面封裝基板例如是長條狀基板或二維陣列基板,其包括多個線路基板單元和多個設置於線路基板單元內的內埋元件。
請參照第1及2圖,在原始設計的封裝結構(a)中,上方導電層及下方導電層的數量為2L+1L組合時,基板的翹曲量為19-25mm,遠大於可容許的翹曲量5-10mm,然而在改善的封裝結構(b)中加入應力抵消層之後,可使基板的翹曲量減少至2-4mm,小於可容許的翹曲量5-10mm。
此外,在原始設計的封裝結構(a)中,上方導電層及下方導電層的數量為1L+2L組合時,基板的翹曲量為21-26mm,遠大於可容許的翹曲量5-10mm,然而在改善的封裝結構(b)中加入應力抵消層之後,可使基板的翹曲量減少至3-4mm,小於可容許的翹曲量5-10mm。
另外,在原設計的封裝結構(a)中,上方導電層及下方導電層的數量為2L組合時(無下方導電層),基板的翹曲量為15-21mm,遠大於可容許的翹曲量5-10mm,然而在改善的封裝結構(b)中加入應力抵消層之後,可使基板的翹曲量減少至0-2mm,小於可容許的翹曲量5-10mm。
再者,在原設計的封裝結構(a)中,上方導電層及下方導電層的數量為1L組合時(無下方導電層),基板的翹曲量為21-28mm,遠大於可容許的翹曲量5-10mm,然而在改善的封裝結構(b)中加入應力抵消層之後,可使基板的翹曲量為2-5mm,小於可容許的翹曲量10mm。
由上述的圖表可知,本實施例可根據不同的非對稱組合來訂製不同厚度的應力抵消層,以有效抑制基板的翹曲量小於5mm。請參照第2圖,在原設計的結構(a)中,由於銅箔基板(Copper clad laminate,簡稱CCL)的厚度為固定值,介於30+/-5微米或40+/-5微米之間,且未考量各導電層的殘銅率及銅箔厚度對翹曲量的影響,因而翹曲量均遠大於可容許的翹曲量5-10mm,無法降低。反觀,在改善後的封裝結構(b)中,由於銅箔基板(CCL)的厚度為非固定值,可介於4-351微米之間,且本實施例中進一步考量各導電層的殘銅率及銅箔厚度對翹曲量的影響,因此改善後的翹曲量可小於5mm。
如第2圖所示,當上方導電層及下方導電層的數量為2L+1L、1L+2L、2L、1L等四組組合時,銅箔基板(CCL)的厚度分別介於34-171(+/-12)微米、81-339(+/-12)微米、51-300(+/-12)微米以及16-129(+/-12)微米之間,其中+/-12微米為公差值。此外,當上方導電層及下方導電層的數量為2L+1L、1L+2L、2L、1L等四組組合時,銅箔基板的厚度(T1)與核心層的厚度(T2)的比值分別介於0.18~1.152、0.57~2.90、0.42~2.58以及0.03~1.17之間。核心層的厚度為固定值,例如為121+/-10微米,其厚度可根據實際需求調整。
在本實施例中,銅箔基板(或以下所稱呼的應力抵消層)的厚度主要取決於該非對稱的線路結構各導電層的殘銅率與厚度,因此,當導電層的數量、殘銅率以及厚度等多個參數中至少之一改變時,銅箔基板的厚度也會跟著改變,藉以平衡非對稱線路結構對線路基板產生的非對稱應力分布。
在一實施例中,各導電層的殘銅率例如介於10%至95%之間,殘銅率指銅層製成線路後的面積和整個未圖案化銅層面積之比。沒有加工製作線路的原始銅層的殘銅率就是100%。此外,各導電層的厚度例如介於10至30微米之間。一般而言,殘銅率增加或厚度增加,對線路基板的應力的影響程度也會增加,但仍需進一步比較核心層上方及下方的導電層的數量的差值,請參照如下說明。
請參照第3A圖,其繪示一種內埋元件封裝結構100,包括一線路基板110、一內埋元件120以及一應力抵消層130。線路基板110具有一核心層111以及一上導電層112,且核心層111具有一第一厚度(以T2表示於第2圖中)。內埋元件120設置於核心層111中。核心層111具有相對的一第一表面S1(或第一側)以及一第二表面S2(或第二側),上導電層112設置於第一表面S1,且上導電層112與內埋元件120電性連接。也就是說,上導電層112的電性接點112a與相對應的內埋元件120的電性接墊121相互接觸而導通。此外,本實施例更可設置多個銲球140於線路基板110上,並與上導電層112電性連接,以製作球格陣列型態的內埋元件封裝結構100。
第3A圖中的非對稱線路結構只有單一上導電層112,位於內埋元件120的上方,因此,本實施例中設置一應力抵消層130於內埋元件120的下方,也就是設置於核心層111的第二表面S2,用以平衡內埋元件120的上方及下方的應力分布。
應力抵消層130例如為包含玻纖的介電材料層,且沒有銅層覆蓋在此應力抵消層130上。由於應力抵消層130的介電材料固化之後具有較強的剛性,可抑制線路基板110向上彎曲,故可有效減少線路基板110的翹曲。在另一實施例中,應力抵消層130亦可採用具有預定強度的複合材料、奈米材料或金屬材料製成,本發明對此不加以限制。
根據第2圖中的數值可知,第3A圖中應力抵消層130具有一第二厚度(以T1表示於第2圖中)例如介於16-129(+/-12)微米之間,且應力抵消層130的厚度與核心層111的厚度的比值(T1/T2)例如介於0.03-1.17之間。
舉例而言,應力抵消層130的膠材與玻纖密度分別為1.1g/cm3
與2.5g/cm3
,膠含量50%,玻纖含量50%,上導電層112的銅密度為8.9 g/cm3
,殘銅率為65%,銅厚度為13.6微米。應力抵消層130的厚度可以算式表示為:(上導電層銅厚度x殘銅率x銅密度 )/((膠含量x 膠密度)+(玻纖含量x玻纖密度)),即(13.6微米 x 65% x 8.9) / (50%x1.1+50%x2.5) =43.7微米。在另一實施例中,當殘銅率變為95%時,應力抵消層130的厚度相對增加至63.88微米。在另一實施例中,當殘銅率變為95%,且銅厚度變為30微米時,應力抵消層130的厚度相對增加至141微米。反之,當殘銅率變為10%,且銅厚度變為10微米時,應力抵消層130的厚度相對減少至4微米。
請參照第3B圖,其繪示一種內埋元件封裝結構101,包括一線路基板110、一內埋元件120以及一應力抵消層130。線路基板110具有一核心層111、二層上導電層112、114以及一介電材料層113。核心層111具有一第一厚度。內埋元件120設置於線路基板110的核心層111中。核心層111具有相對的一第一表面S1以及一第二表面S2,上導電層112設置於核心層111的第一表面S1,且上導電層112與內埋元件120電性連接,另一上導電層114設置於介電材料層113上。此二層上導電層112、114之間以貫穿介電材料層113的導電柱C相互導通。介電材料層113設置於此二上導電層112、114之間。此外,本實施例更可設置多個銲球140於線路基板110上,並與上導電層112、114電性連接,以製作球格陣列型態的內埋元件封裝結構101,如上所述。
第3B圖中的非對稱線路結構有兩層上導電層112、114,位於內埋元件120的上方,因此,本實施例中設置一應力抵消層130於內埋元件120的下方,也就是設置於核心層111的第二表面S2,用以平衡內埋元件120的上方及下方的應力分布。上導電層112、114的數量不限定只有兩層,亦可兩層以上。
根據第2圖中的數值可知,第3B圖中應力抵消層130的厚度(以T1表示於第2圖中)例如介於51-300(+/-12)微米之間,且應力抵消層130的厚度與核心層111的厚度的比值(T1/T2)例如介於0.42-2.58之間。第3B圖中應力抵消層130的厚度主要取決於(上導電層銅厚度x殘銅率x銅密度 )/((膠含量x 膠密度)+(玻纖含量x玻纖密度))以及介電材料層113的厚度,其算式如上所述,在此不再贅述。上述介電材料層113的材料可與應力抵消層130的介電材料相同,例如為玻纖含量相同的介電材料,因此,當介電材料層113的厚度增加(例如2層或3層)時,應力抵消層130的厚度也需相對增加,才能達到應力平衡。
請參照第3C圖,其繪示一種內埋元件封裝結構102,包括一線路基板110、一內埋元件120以及一應力抵消層130。線路基板110具有一核心層111、二層上導電層112、114、一介電材料層113以及一下導電層115。介電材料層113設置於此二上導電層112、114之間。本實施例與上述實施例的差異在於更包括一下導電層115,設置於核心層111的第二表面S2,其餘元件以相同的標號表示,在此不再贅述。
第3C圖中的非對稱線路結構有兩層上導電層112、114以及一下導電層115,分別位於內埋元件120的上方及下方,因此,本實施例中設置一應力抵消層130於內埋元件120的下方,也就是設置於核心層111的第二表面S2,與下導電層115位於核心層111的同一側,用以平衡內埋元件120的上方及下方的應力分布。
根據第2圖中的數值可知,第3C圖中應力抵消層130的厚度(以T1表示於第2圖中)例如介於34-171(+/-12)微米之間,且應力抵消層130的厚度與核心層111的厚度的比值(T1/T2)例如介於0.18-1.152之間。第3C圖中應力抵消層130的厚度主要取決於((上導電層銅厚度x殘銅率x銅密度 )-(下導電層銅厚度x殘銅率x銅密度 ))/((膠含量x 膠密度)+(玻纖含量x玻纖密度))以及介電材料層113的厚度,其算式如上所述。在本實施例中,由於二個上導電層112、114中位於下方的第一上導電層112與下導電層115的應力相互抵消,因此只要考慮第二上導電層114及介電材料層113產生的非對稱應力。此外,當介電材料層113的厚度增加(例如2層或3層)時,應力抵消層130的厚度也需相對增加,才能達到應力平衡,如上所述。
請參照第3D圖,其繪示一種內埋元件封裝結構103,包括一線路基板110、一內埋元件120以及一應力抵消層130。線路基板110具有一核心層111、一上導電層112以及二層下導電層115、116。上導電層112設置於核心層111的上方,此二層下導電層115、116位於核心層111的下方。上導電層112與此二層下導電層115、116之間例如以貫穿核心層111的導電柱C1以及貫穿應力抵消層130的導電柱C2相互導通。應力抵消層130設置於此二層下導電層115、116之間,且應力抵消層130與此二層下導電層115、116均位於核心層111的相同側。
第3D圖中的非對稱線路結構有一上導電層112以及兩層下導電層115、116,分別位於內埋元件120的上方及下方。第一下導電層115雖然位於內埋元件120的下方,但其對線路基板110產生向下彎的張應力,而第二下導電層116對線路基板110產生向上彎的張應力,兩者的應力可抵消。因此,本實施例中,應力抵消層130的厚度主要取決於上導電層112的殘銅率與厚度以及核心層111的厚度。此外,下導電層115的數量不限定只有兩層,亦可兩層以上。
根據第2圖中的數值可知,第3D圖中應力抵消層130的厚度(以T1表示於第2圖中)例如介於81-339(+/-12)微米之間,且應力抵消層130的厚度與核心層111的厚度的比值(T1/T2)例如介於0.59-2.90之間。第3D圖中應力抵消層130的厚度主要取決於((上導電層銅厚度x殘銅率x銅密度 )+(第一下導電層銅厚度x殘銅率x銅密度 )- (第二下導電層銅厚度x殘銅率x銅密度 )+(核心層的厚度))/((膠含量x 膠密度)+(玻纖含量x玻纖密度))以及介電材料層113的厚度,其算式如上所述。在本實施例中,由於第一下導電層115與第二下導電層116的應力相互抵消,因此只要考慮上導電層112及核心層111產生的非對稱應力。
請參照第4圖,根據上述內容,本發明提出一種內埋式面封裝基板200,其包括多個線路基板單元210、多個內埋元件220以及一應力抵消層230。多個線路基板單元210可經由切割而分為多個線路基板110,如第3A至3D圖所示。內埋式面封裝基板200可視為上述內埋元件封裝結構100-103的半成品。
各個線路基板單元210具有一核心層211以及一非對稱線路結構212(僅繪示一層)。核心層211具有一第一厚度,非對稱線路結構212如同第3A至3D圖所示,在此不再一一繪示,其中非對稱線路結構212於內埋元件220的上方及下方產生一非對稱應力分布,導致內埋式面封裝基板200翹曲。
此外,內埋元件220設置於各個線路基板單元210的核心層211中。應力抵消層130設置於核心層211的一側,用以平衡非對稱線路結構212的應力分布,其中應力抵消層230具有抑制基板翹曲的一第二厚度,使內埋式面封裝基板200的翹曲量小於5mm以下。
在一實施例中,內埋式面封裝基板200的長度尺寸及寬度尺寸為240.5mmх95mm或更大。當內埋式面封裝基板200的翹曲量大於5mm時,內埋式面封裝基板200的平整度不夠,無法進行錫膏印刷製程或迴焊製程,故無法製作錫球240(參見第5D圖)或無法迴焊銲球240使其固定在線路基板單元210上。此外,當內埋式面封裝基板200的翹曲量大於5mm時,也不利於將內埋式面封裝基板200切割為多個線路基板,因而影響封裝成品的品質。另外,本實施例採用非對稱線路結構212,相對於傳統的對稱線路結構(例如2L+2L或1L+1L組合),還可減少至少一層導電層的數量以及減少圖案化一層導電層的步驟,因此本實施例的封裝結構的生產成本相對減少。
請參照第5A至5E圖,根據上述內容,本發明提出一種內埋元件封裝結構的製造方法如下。在第5A圖中,先以電腦模擬結果確認內埋元件封裝結構的整體結構及其應力分布之後,決定一應力抵消層230的所需厚度。在第5B圖中,將一絕緣材料211’設置於應力抵消層230上。在第5C圖中,設置一電子元件於絕緣材料211’上並以另一絕緣材料211”覆蓋,以形成一內埋元件120於核心層211中,其中核心層211具有一第一厚度,應力抵消層230具有一第二厚度。在第5D圖中,形成一非對稱線路結構212於核心層211上,並與內埋元件220電性連接。非對稱線路結構212不限定只有一層,亦可具有多層上導電層及/或多層下導電層。當非對稱線路結構212具有下導電層時,可先形成下導電層於應力抵消層230上,再形成核心層211於下導電層上。在第5E圖中,當形成銲球240於內埋式面封裝基板200之後,再將各個線路基板單元210切開,以形成多個內埋元件封裝結構201。
在一實施例中,電子元件例如為半導體晶片、驅動晶片、控制晶片等主動元件或電阻、電感、電容之類的被動元件。
在上述的製造方法的一實施例中,可先形成一非對稱線路結構於電子元件的上方及下方之後,再將一應力抵消層230設置於核心層211的一側;或者,可將一應力抵消層230設置於核心層211的一側之後,再形成一非對稱線路結構於電子元件的上方及下方,本發明對此不加以限制。
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100-103:內埋元件封裝結構
110:線路基板
111:核心層
112:上導電層
112a:電性接點
113:介電材料層
115、116:下導電層
120:內埋元件
121:電性接墊
130:應力抵消層
S1:第一表面
S2:第二表面
140:銲球
T1:第二厚度
T2:第一厚度
C、C1、C2:導電柱
200:內埋式面封裝基板
201:內埋元件封裝結構
210:線路基板單元
211:核心層
211’:絕緣材料
211”:絕緣材料
212:非對稱線路結構
220:內埋元件
230:應力抵消層
240:錫球
第1圖繪示原設計與改善後的線路結構的層數與翹曲量的關係比對圖。
第2圖繪示原設計與改善後的線路結構的層數、銅箔基板厚度、核心層厚度、厚度比值、翹曲量以及殘銅率的關係的比對表。
第3A圖繪示依照本發明一實施例的內埋元件封裝結構的剖面示意圖。
第3B圖繪示依照本發明另一實施例的內埋元件封裝結構的剖面示意圖。
第3C圖繪示依照本發明另一實施例的內埋元件封裝結構的剖面示意圖。
第3D圖繪示依照本發明另一實施例的內埋元件封裝結構的剖面示意圖。
第4圖繪示依照本發明一實施例的內埋式面封裝基板的剖面示意圖。
第5A至5E圖繪示依照本發明一實施例的內埋元件封裝結構的製造方法的流程圖。
100:內埋元件封裝結構
110:線路基板
111:核心層
112:上導電層
112a:電性接點
120:內埋元件
121:電性接墊
130:應力抵消層
140:銲球
S1:第一表面
S2:第二表面
T1:第二厚度
T2:第一厚度
Claims (25)
- 一種內埋元件封裝結構,包括: 一線路基板,具有一核心層以及一非對稱線路結構,該核心層具有一第一厚度; 一內埋元件,設置於該核心層中;以及 一應力抵消層,設置於該核心層的一側,該應力抵消層具有一第二厚度,該第二厚度介於4~351微米之間。
- 如申請專利範圍第1項所述之結構,其中該應力抵消層為包含玻纖的介電材料層。
- 如申請專利範圍第1項所述之結構,其中該核心層具有相對的一第一表面以及一第二表面,該非對稱線路結構包含一上導電層,該上導電層設置於該第一表面,且與該內埋元件電性連接。
- 如申請專利範圍第1項所述之結構,其中該核心層具有相對的一第一表面以及一第二表面,該非對稱線路結構包含至少二層的上導電層以及至少一介電材料層,該至少二層的上導電層設置於該第一表面,且與該內埋元件電性連接,該至少一介電材料層設置於該至少二層的上導電層之間。
- 如申請專利範圍第4項所述之結構,其中該非對稱線路結構更包含一下導電層,設置於該第二表面。
- 如申請專利範圍第1項所述之結構,其中該核心層具有相對的一第一表面以及一第二表面,該非對稱線路結構包含一上導電層、至少二層的下導電層以及至少一介電材料層,該上導電層設置於該第一表面,且與該內埋元件電性連接,該至少二層的下導電層設置於該第二表面,且該至少一介電材料層設置於該至少二層的下導電層之間。
- 如申請專利範圍第6項所述之結構,其中以該應力抵消層為該至少一介電材料層。
- 如申請專利範圍第1項所述之結構,其中該第二厚度與該第一厚度的比值介於0.03~2.9之間。
- 如申請專利範圍第3項所述之結構,其中該第二厚度與該第一厚度的比值介於0.03~1.17之間。
- 如申請專利範圍第4項所述之結構,其中該第二厚度與該第一厚度的比值介於0.42~2.58之間。
- 如申請專利範圍第5項所述之結構,其中該第二厚度與該第一厚度的比值介於0.18~1.152之間。
- 如申請專利範圍第6項所述之結構,其中該第二厚度與該第一厚度的比值介於0.57~2.9之間。
- 一種內埋式面封裝基板,包括: 複數個線路基板單元,各該線路基板單元具有一核心層以及一非對稱線路結構,該核心層具有一第一厚度; 複數個內埋元件,設置於該些線路基板單元的該核心層中;以及 一應力抵消層,設置於該些線路基板單元的一側,其中該應力抵消層具有一第二厚度,該內埋式面封裝基板的翹曲量小於5mm。
- 如申請專利範圍第13項所述之結構,其中該非對稱線路結構包含一上導電層,設置於該核心層的一側並與該內埋元件電性連接,其中該應力抵消層的該第二厚度取決於該上導電層的殘銅率及厚度。
- 如申請專利範圍第13項所述之結構,其中該非對稱線路結構包含至少二層上導電層以及至少一介電材料層,該至少二層上導電層設置於該核心層的另一側並與該內埋元件電性連接,該至少一介電材料層設置於該至少二層上導電層之間,其中該應力抵消層的該第二厚度取決於該至少二層上導電層的殘銅率及厚度與該至少一介電材料層的厚度。
- 如申請專利範圍第15項所述之結構,其中該非對稱線路結構更包含一下導電層,與該應力抵消層同側設置於該核心層上,該應力抵消層的該第二厚度更進一步取決於該下導電層的殘銅率及厚度。
- 如申請專利範圍第13項所述之結構,其中該非對稱線路結構包含一上導電層以及至少二層下導電層,該應力抵消層設置於該至少二層的下導電層之間,其中該應力抵消層的該第二厚度取決於該上導電層及該至少二層下導電層的殘銅率及厚度與該核心層的該第一厚度。
- 如申請專利範圍第13項所述之結構,其中該第二厚度與該第一厚度的比值介於0.03~2.9之間。
- 如申請專利範圍第14項所述之結構,其中該第二厚度與該第一厚度的比值介於0.03~1.17之間。
- 如申請專利範圍第15項所述之結構,其中該第二厚度與該第一厚度的比值介於0.42~2.58之間。
- 如申請專利範圍第16項所述之結構,其中該第一厚度與該第二厚度的比值介於0.18~1.152之間。
- 如申請專利範圍第17項所述之結構,其中該第一厚度與該第二厚度的比值介於0.57~2.9之間。
- 一種內埋元件封裝結構的製造方法,包括: 設置一應力抵消層於一核心層的一側,該核心層具有一第一厚度,該應力抵消層具有一第二厚度; 將一電子元件設置於該核心層中;以及 形成一非對稱的線路結構於該電子元件的上方及下方。
- 如申請專利範圍第23項所述之方法,其中該第一厚度與該第二厚度的比值介於0.03~2.9之間。
- 如申請專利範圍第23項所述之方法,其中該第二厚度取決於該非對稱的線路結構各導電層的殘銅率與厚度。
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Family Cites Families (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001345212A (ja) | 2000-05-31 | 2001-12-14 | Tdk Corp | 積層電子部品 |
JP2002324729A (ja) | 2001-02-22 | 2002-11-08 | Tdk Corp | 電子部品とその製造方法 |
JP3612031B2 (ja) | 2001-03-29 | 2005-01-19 | Tdk株式会社 | 高周波モジュール |
TW550717B (en) * | 2002-04-30 | 2003-09-01 | United Test Ct Inc | Improvement of flip-chip package |
JP4301401B2 (ja) | 2002-11-08 | 2009-07-22 | Tdk株式会社 | フロントエンドモジュール及び通信端末 |
JP3734807B2 (ja) | 2003-05-19 | 2006-01-11 | Tdk株式会社 | 電子部品モジュール |
JP2004342948A (ja) | 2003-05-19 | 2004-12-02 | Tdk Corp | 電子部品モジュール |
US7547975B2 (en) | 2003-07-30 | 2009-06-16 | Tdk Corporation | Module with embedded semiconductor IC and method of fabricating the module |
US20050068757A1 (en) * | 2003-09-30 | 2005-03-31 | Saikumar Jayaraman | Stress compensation layer systems for improved second level solder joint reliability |
TW200618705A (en) | 2004-09-16 | 2006-06-01 | Tdk Corp | Multilayer substrate and manufacturing method thereof |
JP2006339354A (ja) | 2005-06-01 | 2006-12-14 | Tdk Corp | 半導体ic及びその製造方法、並びに、半導体ic内蔵モジュール及びその製造方法 |
JP4701942B2 (ja) | 2005-09-14 | 2011-06-15 | Tdk株式会社 | 半導体ic内蔵モジュール |
JP4535002B2 (ja) | 2005-09-28 | 2010-09-01 | Tdk株式会社 | 半導体ic内蔵基板及びその製造方法 |
US7733600B2 (en) | 2005-09-30 | 2010-06-08 | Tdk Corporation | Hard disk drive and wireless data terminal using the same |
US8188375B2 (en) | 2005-11-29 | 2012-05-29 | Tok Corporation | Multilayer circuit board and method for manufacturing the same |
JP4826248B2 (ja) | 2005-12-19 | 2011-11-30 | Tdk株式会社 | Ic内蔵基板の製造方法 |
US8064211B2 (en) | 2006-08-31 | 2011-11-22 | Tdk Corporation | Passive component and electronic component module |
JP4303282B2 (ja) | 2006-12-22 | 2009-07-29 | Tdk株式会社 | プリント配線板の配線構造及びその形成方法 |
JP2008159820A (ja) | 2006-12-22 | 2008-07-10 | Tdk Corp | 電子部品の一括実装方法、及び電子部品内蔵基板の製造方法 |
JP2008159819A (ja) | 2006-12-22 | 2008-07-10 | Tdk Corp | 電子部品の実装方法、電子部品内蔵基板の製造方法、及び電子部品内蔵基板 |
JP4331769B2 (ja) | 2007-02-28 | 2009-09-16 | Tdk株式会社 | 配線構造及びその形成方法並びにプリント配線板 |
JP4518113B2 (ja) | 2007-07-25 | 2010-08-04 | Tdk株式会社 | 電子部品内蔵基板及びその製造方法 |
JP4487271B2 (ja) | 2007-07-25 | 2010-06-23 | Tdk株式会社 | 集合基板及びその製造方法 |
JP4434268B2 (ja) | 2007-11-28 | 2010-03-17 | Tdk株式会社 | 電子部品モジュール |
JP2009200356A (ja) | 2008-02-22 | 2009-09-03 | Tdk Corp | プリント配線板及びその製造方法 |
JP4438879B2 (ja) | 2008-03-19 | 2010-03-24 | Tdk株式会社 | 同期整流型dc/dcコンバータ |
JP4787296B2 (ja) | 2008-07-18 | 2011-10-05 | Tdk株式会社 | 半導体内蔵モジュール及びその製造方法 |
JP4888736B2 (ja) | 2008-08-29 | 2012-02-29 | Tdk株式会社 | 配線基板の製造方法 |
JP5471605B2 (ja) | 2009-03-04 | 2014-04-16 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP2010232314A (ja) | 2009-03-26 | 2010-10-14 | Tdk Corp | 電子部品モジュール |
JP5434714B2 (ja) | 2009-04-15 | 2014-03-05 | Tdk株式会社 | 薄膜コンデンサ及び電子回路基板 |
TWI418272B (zh) * | 2009-08-25 | 2013-12-01 | Samsung Electro Mech | 處理核心基板之空腔的方法 |
JP5692217B2 (ja) * | 2010-03-16 | 2015-04-01 | 日本電気株式会社 | 機能素子内蔵基板 |
JP4953034B2 (ja) | 2010-03-26 | 2012-06-13 | Tdk株式会社 | 電圧変換器 |
JP5552958B2 (ja) | 2010-08-17 | 2014-07-16 | Tdk株式会社 | 端子構造、プリント配線板、モジュール基板及び電子デバイス |
US8642897B2 (en) | 2010-10-12 | 2014-02-04 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
JP5540276B2 (ja) | 2011-03-31 | 2014-07-02 | Tdk株式会社 | 電子部品内蔵基板及びその製造方法 |
TW201308548A (zh) * | 2011-08-15 | 2013-02-16 | Powertech Technology Inc | 小基板多晶片記憶體封裝構造 |
JP5617866B2 (ja) | 2012-04-06 | 2014-11-05 | Tdk株式会社 | シールドケース及び電子機器 |
JP6152254B2 (ja) | 2012-09-12 | 2017-06-21 | 新光電気工業株式会社 | 半導体パッケージ、半導体装置及び半導体パッケージの製造方法 |
JP5998792B2 (ja) | 2012-09-21 | 2016-09-28 | Tdk株式会社 | 半導体ic内蔵基板及びその製造方法 |
JP5605414B2 (ja) | 2012-10-17 | 2014-10-15 | Tdk株式会社 | 電子部品内蔵基板及びその製造方法 |
JP6478309B2 (ja) | 2012-12-31 | 2019-03-06 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | 多層基板及び多層基板の製造方法 |
JP6102486B2 (ja) | 2013-05-10 | 2017-03-29 | Tdk株式会社 | 複合電源管理装置及び通信装置 |
JP6303443B2 (ja) | 2013-11-27 | 2018-04-04 | Tdk株式会社 | Ic内蔵基板の製造方法 |
CN103874347B (zh) * | 2014-03-28 | 2016-09-07 | 江阴芯智联电子科技有限公司 | 高密度多层基板表面对称结构及制作方法 |
US9837484B2 (en) * | 2015-05-27 | 2017-12-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming substrate including embedded component with symmetrical structure |
JP6582669B2 (ja) | 2015-07-22 | 2019-10-02 | Tdk株式会社 | 薄膜キャパシタ及び半導体装置 |
JP6269626B2 (ja) | 2015-09-11 | 2018-01-31 | Tdk株式会社 | 半導体装置、電子部品内蔵基板、及びこれらの製造方法 |
JP6607087B2 (ja) | 2016-03-02 | 2019-11-20 | Tdk株式会社 | 電子部品内蔵基板の製造方法 |
JP6728917B2 (ja) | 2016-04-12 | 2020-07-22 | Tdk株式会社 | 電子回路モジュールの製造方法 |
US10278290B2 (en) | 2016-07-19 | 2019-04-30 | Tdk Corporation | Electronic component embedded substrate |
JP6750462B2 (ja) | 2016-11-04 | 2020-09-02 | Tdk株式会社 | 薄膜コンデンサ及び電子部品内蔵基板 |
KR101983188B1 (ko) * | 2016-12-22 | 2019-05-28 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
JP6862886B2 (ja) | 2017-02-13 | 2021-04-21 | Tdk株式会社 | 電子部品内蔵基板 |
JP6822192B2 (ja) | 2017-02-13 | 2021-01-27 | Tdk株式会社 | 電子部品内蔵基板 |
JP6897139B2 (ja) | 2017-02-13 | 2021-06-30 | Tdk株式会社 | 電子部品内蔵基板及び基板実装構造体 |
US11367626B2 (en) | 2017-03-31 | 2022-06-21 | Tdk Corporation | Electronic component-incorporating substrate |
US10515898B2 (en) | 2018-05-14 | 2019-12-24 | Tdk Corporation | Circuit board incorporating semiconductor IC and manufacturing method thereof |
CN208691627U (zh) * | 2018-08-03 | 2019-04-02 | 奥特斯科技(重庆)有限公司 | 具有嵌入腔中的部件且前侧上具有双介电层的部件承载件 |
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2019
- 2019-03-12 US US16/351,026 patent/US11277917B2/en active Active
- 2019-05-30 TW TW108118722A patent/TWI770388B/zh active
- 2019-06-06 CN CN201910491301.1A patent/CN111696930A/zh active Pending
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Also Published As
Publication number | Publication date |
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US20200296836A1 (en) | 2020-09-17 |
US11277917B2 (en) | 2022-03-15 |
JP2020150246A (ja) | 2020-09-17 |
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CN111696930A (zh) | 2020-09-22 |
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