TW201944544A - 記憶體元件及其製造方法 - Google Patents

記憶體元件及其製造方法 Download PDF

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TW201944544A
TW201944544A TW108109254A TW108109254A TW201944544A TW 201944544 A TW201944544 A TW 201944544A TW 108109254 A TW108109254 A TW 108109254A TW 108109254 A TW108109254 A TW 108109254A TW 201944544 A TW201944544 A TW 201944544A
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gate structure
nitride layer
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陳彥廷
羅明山
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力旺電子股份有限公司
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Abstract

一種記憶體元件及其製造方法。所述記憶體元件包括第一閘極結構、第二閘極結構、氧化物層以及氮化物層。所述第一閘極結構與所述第二閘極結構配置於基底上。所述氧化物層覆蓋所述第一閘極結構。所述氮化物層配置於所述基底上，且覆蓋所述氧化物層與所述第二閘極結構。所述氮化物層的鄰近所述氮化物層與所述第一閘極結構以及所述第二閘極結構的界面處的部分的折射率相較於所述氮化物層的其餘部分的折射率小5%至10%。

Description

記憶體元件及其製造方法
本發明是有關於一種記憶體元件及其製造方法，且特別是有關於一能夠改善資料保持（data retention）特性的記憶體元件及其製造方法。
記憶體元件具有可多次進行資料之存入、讀取、抹除等動作，且存入之資料在斷電後也不會消失之優點，因此已被個人電腦和電子設備所廣泛採用。
一般來說，在形成記憶體元件的過程中，在形成浮置閘極結構之後，會於其上形成一層氮化物層，以在後續形成接觸窗的製程中作為蝕刻中止層。上述氮化物層即所謂的接觸窗蝕刻中止層（contact etching stop layer，CESL）。然而，上述的接觸窗蝕刻中止層中往往會存在缺陷而導致電荷累積，因而在記憶體元件的操作過程中對元件效能造成影響。
舉例來說，記憶體元件在進行程式化之後，在高溫環境下（例如在150℃至300℃的溫度下），儲存於浮置閘極中的電荷會因接觸窗蝕刻中止層中所累積的電荷而朝向接觸窗蝕刻中止層移動，並累積在浮置閘極中靠近接觸窗蝕刻中止層的區域，因而產生極化現象。如此一來，導致流經下方通道區域的電流量降低，因而降低了元件效能。
本發明提供一種記憶體元件，其中作為接觸窗蝕刻中止層的氮化物層中鄰近閘極結構的部分相較於其餘部分具有較小的折射率。
本發明提供一種記憶體元件的製造方法，其用以製造上述的記憶體元件。
本發明的記憶體元件包括第一閘極結構、第二閘極結構、氧化物層以及氮化物層。所述第一閘極結構與所述第二閘極結構配置於所述基底上。所述氧化物層覆蓋所述第一閘極結構。所述氮化物層配置於所述基底上，且覆蓋所述氧化物層與所述第二閘極結構。所述氮化物層的鄰近所述氮化物層與所述第一閘極結構以及所述第二閘極結構的界面處的部分的折射率相較於所述氮化物層的其餘部分的折射率小5%至10%。
在本發明的記憶體元件的一實施例中，所述氮化物層的鄰近所述氮化物層與所述第一閘極結構以及所述第二閘極結構的界面處的部分的厚度例如為所述氮化物層的厚度的1%至10%。
本發明的記憶體元件包括第一閘極結構、第二閘極結構、氧化物層、第一氮化物層、以及第二氮化物層。所述第一閘極結構與所述第二閘極結構配置於所述基底上。所述氧化物層覆蓋所述第一閘極結構。所述第一氮化物層配置於所述基底上，且覆蓋所述氧化物層與所述第二閘極結構。所述第二氮化物層配置於所述第一氮化物層上。所述第一氮化物層的折射率相較於所述第二氮化物層的折射率小5%至10%。
在本發明的記憶體元件的一實施例中，所述第一氮化物層的厚度為所述第一氮化物層與所述第二氮化物層的總厚度的1%至10%。
在本發明的記憶體元件的一實施例中，所述第一閘極結構例如為浮置閘極結構，且所述第二閘極結構例如為選擇閘極結構。
本發明的記憶體元件的製造方法包括以下步驟。首先，於基底上形成第一閘極結構與第二閘極結構。接著，於所述第一閘極結構的表面上形成氧化物層。之後，進行化學氣相沉積製程，於所述基底上形成覆蓋所述氧化物層與所述第二閘極結構的氮化物層。在所述化學氣相沉積製程中，射頻電源將功率自0增加到預定最終功率，使得所述氮化物層的鄰近所述氮化物層與所述第一閘極結構以及所述第二閘極結構的界面處的部分的折射率相較於其餘部分的折射率小5%至10%。
在本發明的記憶體元件的製造方法的一實施例中，所述第一閘極結構例如為浮置閘極結構，且所述第二閘極結構例如為選擇閘極結構。
在本發明的記憶體元件的製造方法的一實施例中，所述氮化物層的鄰近所述氮化物層與所述第一閘極結構以及所述第二閘極結構的界面處的部分的厚度例如為所述氮化物層的厚度的1%至10%。
在本發明的記憶體元件的製造方法的一實施例中，所述氧化物層的形成方法以下步驟。首先，於所述基底上共形地形成氧化物材料層。然後，進行圖案化製程，移除部分氧化物材料層，保留位於所述第一閘極結構的表面上的氧化物材料層。
在本發明的記憶體元件的製造方法的一實施例中，所述預定最終功率例如介於300 W至500 W之間。
在本發明的記憶體元件的製造方法的一實施例中，所述射頻電源例如在3000 W/sec至10000 W/sec的速率下將功率自0增加到所述預定最終功率。
在本發明的記憶體元件的製造方法的一實施例中，所述射頻電源例如在約0.01秒至1秒的範圍內將功率自0增加到所述預定最終功率。
基於上述，在本發明中，使鄰近閘極結構的氮化物層（作為接觸窗蝕刻中止層）形成為具有較小折射率，意即含有較少的Si-H鍵結，使得作為接觸窗蝕刻中止層的氮化物層具有較佳的品質（具有較少缺陷）。因此，當後續所形成的記憶體元件在進行程式化之後，在高溫環境下，本發明的氮化物層可避免儲存於浮置閘極中的電荷累積在浮置閘極中靠近接觸窗蝕刻中止層的區域，進而可避免流經通道區域的電流量降低而降低元件效能。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
在下文中，將參照附圖來說明本發明實施例。在附圖中，為清楚說明，可能誇大或縮小各元件的形狀、尺寸、比例等。
圖1A至圖1C為依照本發明第一實施例的記憶體元件的製造流程剖面示意圖。
首先，請參照圖1A，提供基底100。基底100例如是矽基底。基底100具有記憶元件區100a與周邊電路區100b。在後續製程中，記憶元件區100a中可形成有各種記憶體元件，而周邊電路區100b中可形成有各種邏輯元件。接著，於記憶元件區100a中的基底100上形成閘極結構102與閘極結構104，且於周邊電路區100b中的基底100上形成閘極結構106。
在本實施例中，閘極結構102、閘極結構104與閘極結構106可在相同的製程步驟中形成。舉例來說，首先，於基底100上形成一層閘介電材料層（例如氧化物層，其形成方法例如是進行熱氧化製程）。接著，於閘介電材料層上形成一層閘極材料層（例如多晶矽層，其形成方法例如是進行化學氣相沉積製程）。然後，進行圖案化製程，移除部分閘極材料層與閘介電材料層，以於記憶元件區100a中的基底100上形成閘介電層102a與位於閘介電層102a上的閘極102b、閘介電層104a與位於閘介電層104a上的閘極104b，以及於周邊電路區100b中的基底100上形成閘介電層106a與位於閘介電層106a上的閘極106b。接著，分別於閘極102b、閘極104b與閘極106b的側壁上形成間隙壁102c、間隙壁104c與間隙壁106c。之後，分別於閘極102b、閘極104b與閘極106b兩側的基底100中形成摻雜區102d、摻雜區104d與摻雜區106d。
在本實施例中，閘極結構102包括閘介電層102a、閘極102b、間隙壁102c與摻雜區102d，其作為記憶體元件的浮置閘極結構。此外，閘極結構104包括閘介電層104a、閘極104b、間隙壁104c與摻雜區104d，其作為記憶體元件的選擇閘極結構。在本實施例中，閘極結構102與閘極結構104共用位於兩者之間的摻雜區，但本發明不限於此。另外，閘極結構106包括閘介電層106a、閘極106b、間隙壁106c與摻雜區106d，其作為控制電路的開關元件。
接著，請參照圖1B，於閘極結構102的表面上形成氧化物層108。氧化物層108作為金屬矽化物罩幕層（salicide block，SAB），避免金屬矽化物形成於閘極102b的暴露表面上。在一些實施例中，為了進一步降低閘極104b與閘極106b的電阻值，可選擇性地於閘極104b與閘極106b的暴露表面上形成金屬矽化物。此時，由於氧化物層108覆蓋閘極結構102的表面，因此可避免金屬矽化物形成於閘極102b的暴露表面上。在一些實施例中，氧化物層108的形成方法包括先於基底100上共形地形成氧化物材料層，然後進行圖案化製程，移除部分氧化物材料層，保留位於閘極結構102的表面上的氧化物材料層。
然後，請參照圖1C，進行化學氣相沉積製程，於基底100上形成氮化物層110。在一些實施例中，氮化物層110覆蓋氧化物層108、閘極結構104與閘極結構106，且作為接觸窗蝕刻中止層。氮化物層110的材料通常為氮化矽，且進行上述化學氣相沉積製程時，無可避免地會因外界環境中存在的含氫物質而使得氮化物層110中產生Si-H鍵結而導致缺陷產生。因此，在本實施例中，在進行化學氣相沉積製程時，使射頻電源在0.01秒至1秒的範圍內將功率自0增加到預定最終功率。在一些實施例中，預定最終功率例如介於300 W至500 W之間，且射頻電源可在3,000 W/sec至10,000 W/sec的速率下將功率自0增加到預定最終功率。如此一來，可快速地成長氮化物層，且所成長的氮化物層會含有較少的Si-H鍵結而具有較佳的品質（具有較少缺陷）。當功率自0增加到預定最終功率之後，維持最終功率直到形成所需厚度的氮化物層110。也就是說，在最終所形成的氮化物層110中，氮化物層110的鄰近氮化物層110與閘極結構102、閘極結構104以及閘極結構106的界面處的部分110a的折射率會小於其餘部分的折射率。此外，因射頻電源在0.01秒至1秒的範圍內將功率自0增加到預定最終功率，部分110a的折射率相較於其餘部分的折射率會小5%至10%。
因此，當後續所形成的記憶體元件在進行程式化之後，在高溫環境下，本發明的氮化物層110可避免儲存於浮置閘極（閘極102b）中的電荷累積在浮置閘極中靠近接觸窗蝕刻中止層（氮化物層110）的區域，進而可避免流經通道區域的電流量降低而降低元件效能。
特別一提的是，由於射頻電源在0.01秒至1秒的範圍內將功率自0增加到預定最終功率，因此在此種短時間範圍內形成的具備低折射率的氮化物層（即部分110a）具有非常小的厚度，因此不會對閘極結構104以及閘極結構106的電特性造成嚴重影響。此外，在以上述方式所形成的氮化物層110中，部分110a的厚度例如為氮化物層110的厚度的1%至10%。舉例來說，當氮化物層110的厚度例如為約800 Å時，部分110a的厚度可為約10 Å。
圖2A至圖2B為依照本發明第二實施例的記憶體元件的製造流程剖面示意圖。在下文中，於前文相同的元件將以相同的元件符號標示，且將不對其另行說明。
首先，請參照圖2A，接續在圖1B所述的步驟之後，於基底100上形成氮化物層200，其覆蓋氧化物層108、閘極結構104與閘極結構106。氮化物層200的材料通常為氮化矽。在本實施例中，氮化物層200的折射率相較於後續形成於其上的另一層氮化物層的折射率小5%至10%。氮化物層200可採用任何熟知的方式來形成。舉例來說，可藉由調整化學氣相沉積製程的各種製程參數（例如降低矽烷的流量、提高射頻電源所提供的功率、增加射頻電源提高功率的速率等）來形成氮化物層200。或者，可採用如圖1C所述的方式（在進行化學氣相沉積製程時，使射頻電源在0.01秒至1秒的範圍內將功率自0增加到預定最終功率）來形成氮化物層200。
然後，請參照圖2B，於氮化物層200上形成氮化物層202。氮化物層202的材料通常為氮化矽。氮化物層202可採用任何熟知的方式來形成。在本實施例中，氮化物層200與氮化物層202構成所需形成的接觸窗蝕刻中止層，且氮化物層200的厚度例如為氮化物層200與氮化物層202的總厚度的1%至10%。如此一來，由於具有低折射率的氮化物層200具有非常小的厚度，因此不會對閘極結構104以及閘極結構106的電特性造成嚴重影響。
在本實施例中，由於氮化物層200的折射率相較於氮化物層202的折射率小5%至10%，意即氮化物層200含有較少的Si-H鍵結，因此當後續所形成的記憶體元件在進行程式化之後，在高溫環境下，本發明的氮化物層200可避免儲存於浮置閘極（閘極102b）中的電荷累積在浮置閘極中靠近接觸窗蝕刻中止層（氮化物層200）的區域，進而可避免流經通道區域的電流量降低而降低元件效能。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100‧‧‧基底
100a‧‧‧記憶元件區
100b‧‧‧周邊電路區
102、104、106‧‧‧閘極結構
102a、104a、106a‧‧‧閘介電層
102b、104b、106b‧‧‧閘極
102c、104c、106c‧‧‧間隙壁
102d、104d、106d‧‧‧摻雜區
108‧‧‧氧化物層
110、200、202‧‧‧氮化物層
110a‧‧‧部分
圖1A至圖1C為依照本發明第一實施例的記憶體元件的製造流程剖面示意圖。
圖2A至圖2B為依照本發明第二實施例的記憶體元件的製造流程剖面示意圖。

Claims (13)

  1. 一種記憶體元件，包括： 第一閘極結構與第二閘極結構，配置於基底上； 氧化物層，覆蓋所述第一閘極結構；以及 氮化物層，配置於所述基底上，且覆蓋所述氧化物層與所述第二閘極結構， 其中所述氮化物層的鄰近所述氮化物層與所述第一閘極結構以及所述第二閘極結構的界面處的部分相較於所述氮化物層的其餘部分的折射率小5%至10%。
  2. 如申請專利範圍第1項所述的記憶體元件，其中所述第一閘極結構為浮置閘極結構，且所述第二閘極結構為選擇閘極結構。
  3. 如申請專利範圍第1項所述的記憶體元件，其中所述氮化物層的鄰近所述氮化物層與所述第一閘極結構以及所述第二閘極結構的界面處的部分的厚度為所述氮化物層的厚度的1%至10%。
  4. 一種記憶體元件，包括： 第一閘極結構與第二閘極結構，配置於基底上； 氧化物層，覆蓋所述第一閘極結構上； 第一氮化物層，配置於所述基底上，且覆蓋所述氧化物層與所述第二閘極結構；以及 第二氮化物層，配置於所述第一氮化物層上， 其中所述第一氮化物層的折射率相較於所述第二氮化物層的折射率小5%至10%。
  5. 如申請專利範圍第4項所述的記憶體元件，其中所述第一閘極結構為浮置閘極結構，且所述第二閘極結構為選擇閘極結構。
  6. 如申請專利範圍第4項所述的記憶體元件，其中所述第一氮化物層的厚度為所述第一氮化物層與所述第二氮化物層的總厚度的1%至10%。
  7. 一種記憶體元件的製造方法，包括： 於基底上形成第一閘極結構與第二閘極結構； 於所述第一閘極結構的表面上形成氧化物層；以及 進行化學氣相沉積製程，於所述基底上形成覆蓋所述氧化物層與所述第二閘極結構的氮化物層， 其中在所述化學氣相沉積製程中，射頻電源將功率自0增加到預定最終功率，使得所述氮化物層的鄰近所述氮化物層與所述第一閘極結構以及所述第二閘極結構的界面處的部分的折射率相較於其餘部分的折射率小5%至10%。
  8. 如申請專利範圍第7項所述的記憶體元件的製造方法，其中所述第一閘極結構為浮置閘極結構，且所述第二閘極結構為選擇閘極結構。
  9. 如申請專利範圍第7項所述的記憶體元件的製造方法，其中所述氮化物層的鄰近所述氮化物層與所述第一閘極結構以及所述第二閘極結構的界面處的部分的厚度為所述氮化物層的厚度的1%至10%。
  10. 如申請專利範圍第9項所述的記憶體元件的製造方法，其中所述氧化物層的形成方法包括： 於所述基底上共形地形成氧化物材料層；以及 進行圖案化製程，移除部分所述氧化物材料層，保留位於所述第一閘極結構的表面上的所述氧化物材料層。
  11. 如申請專利範圍第7項所述的記憶體元件的製造方法，其中所述預定最終功率介於300 W至500 W之間。
  12. 如申請專利範圍第11項所述的記憶體元件的製造方法，其中所述射頻電源在3,000 W/sec至10,000 W/sec的速率下將功率自0增加到所述預定最終功率。
  13. 如申請專利範圍第7項所述的記憶體元件的製造方法，其中所述射頻電源在約0.01秒至1秒的範圍內將功率自0增加到所述預定最終功率。
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TWI770729B (zh) * 2020-02-04 2022-07-11 美商超捷公司 形成具有薄化隧道氧化物之分離閘記憶體單元的方法
TWI798983B (zh) * 2021-06-25 2023-04-11 台灣積體電路製造股份有限公司 積體晶片及其形成方法

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CN114512489A (zh) * 2020-11-16 2022-05-17 力旺电子股份有限公司 非挥发性存储器的存储单元
US11915752B2 (en) * 2022-03-31 2024-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Resistive memory with enhanced redundancy writing
US20240127868A1 (en) * 2022-10-17 2024-04-18 Globalfoundries U.S. Inc. Single ended sense amplifier with current pulse circuit

Family Cites Families (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4870470A (en) * 1987-10-16 1989-09-26 International Business Machines Corporation Non-volatile memory cell having Si rich silicon nitride charge trapping layer
JPH03288399A (ja) 1990-04-04 1991-12-18 Mitsubishi Electric Corp 半導体記憶装置
JPH05325569A (ja) 1992-05-27 1993-12-10 Toshiba Corp 半導体記憶装置
JP2682403B2 (ja) * 1993-10-29 1997-11-26 日本電気株式会社 半導体装置の製造方法
TW501263B (en) * 2001-07-20 2002-09-01 United Microelectronics Corp MOS structure with improved substrate-triggered effect for on-chip ESD protection
EP1431952A4 (en) 2001-09-28 2009-12-02 Sony Corp DISPLAY MEMORY, DRIVER SWITCHING, DISPLAY AND CELLULAR INFORMATION DEVICE
US6473349B1 (en) 2001-11-29 2002-10-29 Motorola, Inc. Cascode sense AMP and column select circuit and method of operation
CN1316706C (zh) * 2002-11-15 2007-05-16 华邦电子股份有限公司 快速触发的静电保护电路及其方法
US6862208B2 (en) 2003-04-11 2005-03-01 Freescale Semiconductor, Inc. Memory device with sense amplifier and self-timed latch
JP4405174B2 (ja) 2003-05-01 2010-01-27 パナソニック株式会社 画像表示制御方法および画像表示装置
JP4477629B2 (ja) * 2004-03-24 2010-06-09 富士通マイクロエレクトロニクス株式会社 強誘電体メモリ
JP4553620B2 (ja) * 2004-04-06 2010-09-29 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
KR100562654B1 (ko) * 2004-04-20 2006-03-20 주식회사 하이닉스반도체 균등화신호(ｂｌｅｑ) 구동회로 및 이를 사용한 반도체메모리 소자
KR100605592B1 (ko) * 2004-05-06 2006-07-31 주식회사 하이닉스반도체 멀티-포트 메모리 소자의 리드용 버스 연결회로
DE102004045219B4 (de) 2004-09-17 2011-07-28 Qimonda AG, 81739 Anordnung und Verfahren zum Auslesen von Widerstandsspeicherzellen
US7015100B1 (en) 2004-12-23 2006-03-21 United Microelectronics Corp. Method of fabricating one-time programmable read only memory
KR100632640B1 (ko) * 2005-03-10 2006-10-12 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
US7200043B2 (en) * 2005-05-31 2007-04-03 Elite Semiconductor Memory Technology, Inc. Nonvolatile memory using a two-step cell verification process
US20070024325A1 (en) 2005-08-01 2007-02-01 Chung-Kuang Chen Sense amplifier with input offset compensation
KR101171192B1 (ko) * 2005-10-21 2012-08-06 삼성전자주식회사 박막트랜지스터 기판와 그 제조방법
KR100816748B1 (ko) * 2006-03-16 2008-03-27 삼성전자주식회사 프로그램 서스펜드/리줌 모드를 지원하는 상 변화 메모리장치 및 그것의 프로그램 방법
WO2008077243A1 (en) 2006-12-22 2008-07-03 Sidense Corp. A power up detection system for a memory device
US7916556B2 (en) 2007-01-09 2011-03-29 Sony Corporation Semiconductor memory device, sense amplifier circuit and memory cell reading method using a threshold correction circuitry
JP2008218625A (ja) 2007-03-02 2008-09-18 Renesas Technology Corp 半導体装置およびその製造方法
US7755871B2 (en) * 2007-11-28 2010-07-13 Amazing Microelectronic Corp. Power-rail ESD protection circuit with ultra low gate leakage
CN100570747C (zh) * 2008-08-05 2009-12-16 中国科学院上海微系统与信息技术研究所 相变存储器
US7936590B2 (en) 2008-12-08 2011-05-03 Qualcomm Incorporated Digitally-controllable delay for sense amplifier
JP4720912B2 (ja) * 2009-01-22 2011-07-13 ソニー株式会社 抵抗変化型メモリデバイス
TWI489471B (zh) 2009-02-06 2015-06-21 Sidense Corp 高可靠度一次可編程（ｏｔｐ）記憶體
US8817432B2 (en) * 2009-04-09 2014-08-26 Ememory Technology Inc. Power switch embedded in ESD PAD
KR101083302B1 (ko) 2009-05-13 2011-11-15 주식회사 하이닉스반도체 반도체 메모리 장치
TWI425768B (zh) * 2010-05-03 2014-02-01 Ememory Technology Inc 可避免輸出電壓產生壓降之高壓選擇電路
US8536898B2 (en) 2010-06-02 2013-09-17 David James Rennie SRAM sense amplifier
US20120086068A1 (en) 2010-10-06 2012-04-12 Synopsys Inc. Method for depositing a dielectric onto a floating gate for strained semiconductor devices
US8605495B2 (en) * 2011-05-09 2013-12-10 Macronix International Co., Ltd. Isolation device free memory
US8817433B2 (en) * 2011-07-28 2014-08-26 Arm Limited Electrostatic discharge protection device having an intermediate voltage supply for limiting voltage stress on components
CN102664041B (zh) * 2012-05-22 2015-01-21 安徽大学 一种基于bist控制的可编程sram时序控制系统
KR20140009712A (ko) * 2012-07-12 2014-01-23 삼성전자주식회사 전압 레귤레이터, 전압 레귤레이팅 시스템, 메모리 칩, 및 메모리 장치
US8792267B1 (en) 2013-01-23 2014-07-29 Lsi Corporation Memory having sense amplifier for output tracking by controlled feedback latch
US9281074B2 (en) * 2013-05-16 2016-03-08 Ememory Technology Inc. One time programmable memory cell capable of reducing leakage current and preventing slow bit response
US9218877B2 (en) 2013-06-19 2015-12-22 Broadcom Corporation Differential bit cell
KR20150120557A (ko) * 2014-04-17 2015-10-28 에스케이하이닉스 주식회사 반도체 메모리를 포함하는 전자 장치 및 이의 동작 방법
TWI566383B (zh) 2014-10-24 2017-01-11 力旺電子股份有限公司 非揮發性記憶體
US9705307B2 (en) * 2015-01-27 2017-07-11 Qualcomm Incorporated Self-sensing reverse current protection switch
CN106451385B (zh) * 2015-08-06 2019-01-01 天钰科技股份有限公司 静电放电保护电路与集成电路
US9613692B1 (en) 2015-12-16 2017-04-04 Stmicroelectronics International N.V. Sense amplifier for non-volatile memory devices and related methods
US9881687B2 (en) * 2015-12-18 2018-01-30 Texas Instruments Incorporated Self-latch sense timing in a one-time-programmable memory architecture
KR102517711B1 (ko) 2016-06-30 2023-04-04 삼성전자주식회사 메모리 셀 및 이를 포함하는 메모리 장치
US9824749B1 (en) 2016-09-02 2017-11-21 Arm Limited Read assist circuitry
JP2018041518A (ja) 2016-09-06 2018-03-15 東芝メモリ株式会社 メモリデバイス
CN106409338B (zh) 2016-09-26 2019-11-26 西安紫光国芯半导体有限公司 一种用于Flash存储器的差分位线结构及其操作方法
US9859003B1 (en) * 2016-10-26 2018-01-02 Arm Limited Selective writes in a storage element
TWI618220B (zh) * 2016-11-01 2018-03-11 世界先進積體電路股份有限公司 靜電放電保護電路
CN206480626U (zh) * 2017-01-22 2017-09-08 建荣集成电路科技(珠海)有限公司 一种静电放电保护电路、芯片及电子设备

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI770729B (zh) * 2020-02-04 2022-07-11 美商超捷公司 形成具有薄化隧道氧化物之分離閘記憶體單元的方法
TWI798983B (zh) * 2021-06-25 2023-04-11 台灣積體電路製造股份有限公司 積體晶片及其形成方法

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