TW501263B - MOS structure with improved substrate-triggered effect for on-chip ESD protection - Google Patents

Abstract

The present invention provides an electrostatic discharge protection device with a high substrate-triggered effect and its application circuits. The ESD protection device formed on a P-type well comprising at least one NMOS, at least one first P+ diffusion region for electrically connecting to a P-well biased circuit, at least one dummy gate between the NMOS and the first P+ diffusion region, at least one second P+ diffusion region for electrically connecting to a Vss power terminal, and at least one shallow trench isolation (STI) structure for isolating the NMOS and the second P+ diffusion region. A drain of the NMOS, the P-type well and a source of the NMOS form a parasitic lateral n-p-n bipolar junction transistor (BJT), and the drain and the source of the NMOS are electrically connected to an I/O buffering pad and a Vss power terminal respectively. When an ESD voltage pulse is zapping on the I/O buffering pad, the P-well biased circuit induces a substrate trigger current (Itrig), causing the parasitic lateral n-p-n BJT to be triggered on and quickly discharge a current incurred from the ESD voltage pulse.

Description

501263 ..... 丨 丨 ———— ^ one one one, one ^ detailed ~ ♦ one ... • one Peng one one—'sai one .... 5. The invention is clear. (Υ ~ Field of the invention The present invention provides a kind of The structure of an ESD protection element and its application circuit are particularly an ESD protection element structure with a substrate-trigger effect and its application circuit. Background Description As the size of semiconductor integrated circuit devices continues to shrink, the In the 4 ^ m complementary metal-oxide-semiconductor (CMOS) technology, a shallower depth of junction depth and a thinner gate oxide layer (gate 〇 face thickness) are added, and a lightly doped drain is added. (LDD), shallow trench isolation (STI) = and self-aligned metal silicide (self-aligne (1 siHcide))

Has become a standard process. However, the above process makes the integrated circuit H valley easily susceptible to electrostatic discharge (ESD) damage, so the esd protection circuit design must be added to the chip to protect the integrated circuit from ESD damage. The integrated circuit products of No. 7 city, in the human body discharge mode (η_ ^ βο: 1 = Odel, ΗΒΜ), must have at least more than 2000 volts in order to withstand such a large ESD voltage 'ESD The protection circuit must have a large enough component size, which increases the area of the silicon chip. As a typical example, the ESD of input circuits (I〆. Circuits) In the design of the protection circuit, the wide output of i channel of NM0S is often λ at 300 / zm. For such a large-sized component design,

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a Amendment 5. Description of the invention (2) Often drawn as a multi-finger structure with parallel fingers. However, when the ESD voltage is generated, many finger layouts in the ESD protection circuit cannot be turned on at the same time to release the ESD current. Only part of the finger cloth will be turned on, so these finger layouts will be burned out by the ESD pulse. Therefore / Although the NMOS in the ESD protection circuit has taken up a very large size, the ESD voltage it can withstand is very low. In order to improve the non-uniform conduction of these multi-finger layout structures, the design of gate drive (gate_driven) has been adopted to increase the ESD withstand capability of large-sized NMOS in protection circuits. However, the gate-driven NMOS in the ESD protection circuit, when the gate drive voltage is increased above a certain value, the ESD tolerance decreases sharply. Because the gate drive design guides the ESD current to the channel surface, the NMOS is more likely to be burned out due to the ESD current. Please refer to Figure 1, which is a circuit diagram of the ESD protection design in traditional gate drive technology. Since the ESD protection design in all gate drive technologies is designed using the same basic concept, the ESD protection design using the gate drive technology disclosed in Figure 1 is used as an illustration. ESD protection circuit design 10 includes NMOS 12 with an ESD protection circuit, and NMOS 12 includes a source 13, a pole 14 and a gate 1 $. The pole 1 4 is connected to a buffer pad 8 and the gate 1 6, the voltage is applied by a gate-biased circuit 2 0. In the traditional design, the gate deflection circuit 20 is usually equipped with a pair of capacitors and resistors.

501263 5. The invention is particularly clear— (3) The buffer pad and the gate are connected, and the resistor is used to connect the gate and the V ss power pin. In addition, the ESD protection circuit design 10 is electrically connected to an internal circuit 22 and a buffer pad 18 through a wire 23. When a positive-polarity ESD voltage is introduced from the input / output buffer 塾 18, the rapidly rising ESD voltage will be coupled with the gate 16 of the ESD protection circuit NM0S 1 2 so that the NM0S1 2 is turned on to pass the ESD current through the buffer. Pad 18 is discharged to the V ss power supply pin, which is the so-called gate coupling design or gate drive design ESD protection circuit. Although the biased gate can improve the shortcomings of the multi-finger layout in the ESD protection circuit, the excessive gate bias can also cause ESD current to flow through the inversion layer on the surface of the NMOS channel. layer), so the NM0S channel is burnt. • Please refer to Figure 2. Figure 2 is a schematic diagram of the path of the gate driving NM0S in the ESD current flowing through the ESD protection circuit. As shown in FIG. 2, NMOS 30 in the ESD protection circuit includes a p-type substrate 3, a p-type well 32 located in the P-type substrate 31, and an NMOS 34 in the P-type well 32. The NM0S 34 includes a source 35, a drain 36, a doped polysilicon gate 37, and two lightly doped / sum electrodes (LDDs) 38 disposed beside the source 35 and the drain 36, respectively. The source 35 is electrically connected to the V ss power pin, the drain 36 is electrically connected to the buffer pad _, and the gate 37 is electrically connected to a gate bias circuit 42. ESD damage ^ Wei occurred on the surface of the lightly doped drain 38 next to the pole 3 6

501263

When a positive-polarity ESD voltage is introduced from the input / output buffer pad 40, the intermediate bias circuit 42 generates a bias voltage (VG) to be applied to the gate 37 in N M 0 S 3 4 and causes the NMOS 34 The surface channel is turned on. Due to the extremely shallow depth of the junction layer of the surface channel and the small volume, it is not only easy to burn out due to overheating, but also to damage NMOS and 34 by electrostatic discharge, and ESD damage usually occurs near the drain electrode 3 6 Lightly doped surface channels near 38 corners (c ο r η 〇r). Therefore, when a large ESD current, a typical example is 1. 3 3 A mp (f or a 2kV HBM ESD) flowing through a very shallow surface channel in NMOS 34, it will often burn NM 0 S 3 4 even if It is because NM 0 S 3 4 has a large element size, and such a situation cannot be avoided. Please refer to Figure II. Figure II is the experimental relationship diagram of the metal self-aligned silicide process of the gate drive voltage and the human electrostatic discharge value (ΗΒΜ) of N Μ 0 S at CMOS 0.35 " m. As shown in Figure 3, the human body electrostatic discharge value (Η B Μ) of NMOS in the ESD protection circuit 12 will start to increase as the gate drive voltage increases. However, the human body's electrostatic discharge value (ΗBM) of NM0S will decrease sharply when the gate drive voltage increases to a certain threshold value. 8 / z m。 The experimental data obtained by the E S D protection circuit NM0S 1 2 in FIG. 3 is taken from a fixed channel length of 0.8 / z m. When the channel width of NM0S W = 6 0 0 / z m, the human body electrostatic discharge value of NM0S will decrease sharply when the gate drive voltage is about 8. 5 V. Therefore, when the gate drive design is applied to the ESD protection circuit of the deep sub-micron technology, the E S D intensity (ES D r 〇 b u s t n e s s) cannot be continuously and effectively increased. Please refer to Figure 4. Figure 4 shows the ESD protection currently used on integrated circuits.

501263! V. Invention 2 (5) Another conventional technique for protecting circuit diagrams. The basic concept of its design is substrate-triggered technology. As shown in Figure 4, the ESD protection circuit 50 includes an NMOS 52, an internal circuit 62, a buffer pad 58, a base bias circuit 60, and a wire 63 electrically connected to the internal circuit 62 and the buffer pad 58. . NMQS 52 includes a source 53, a drain 54 electrically connected to a buffer pad 58, a gate 55, and a substrate 56 which receives a voltage applied by the substrate driving circuit 60. One

V When a positive ESD voltage is introduced from the input / output buffer pad 58, the substrate of the NMOS 52 in the ESD protection circuit 50 will be biased by a voltage applied by the substrate bias circuit 60. . Because of the production of this substrate bias, one of the parasitic lateral bipolar transistors (3 < 1 D) 64 in "1? 40352" will be triggered to emit ESD current. In the above-mentioned substrate triggering technology, the ESD current flowing through NMOS 5 2 will not flow through the surface channel. Therefore, compared with the gate driving technology, N M 0 S 5 2 can withstand a larger E S D voltage. Please refer to Fig. 5 '. Fig. 5 is an experimental relationship diagram of the metal self-aligned silicide process with substrate bias and NMO S's human body electrostatic discharge value at 0.35 # m. As shown in Figure 5, the human body electrostatic discharge value of the NMOS 52 triggered by the substrate will always increase as the substrate bias increases. This result is very different from the gate drive design. Because the substrate triggering effect will trigger the parasitic lateral bipolar transistor 64 in NM 0 S 5 2, the current can be directed to the substrate of NMOS 52 instead of flowing through the lightly doped drain in the surface channel and drain corner of. Because the NMOS 52 substrate has a relatively large volume to diverge

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ESl- ^ OJjjy ^ T Corrects the thermal energy generated by the fifth and the last G (6) > ESD current, so the substrate triggers nm〇s 52 even if it is set on a silicon wafer with the same area, it can withstand higher Esd voltage.触发 The triggering of the ESW stay-on technology with the substrate applied on the wafer is even more important and effective in the deep sub-micron process of CMOS. Please refer to Fig./, 'Fig. 6 is a schematic cross-sectional view of the base trigger design. The NMOS 70 includes a p-type substrate 7 and a p-type well η provided in the p- honey substrate 71 'and two NMOS 73 provided in the P-type well 72. The NMOS 73 includes a source 75, a drain 76, a doped polycrystalline gate 74, two lightly doped drains 79 located next to the source 75 and the drain 76, and two to isolate the NMOS 7 3 and Other electronic components are designed with shallow trench isolation (STI) 77, 78, a P diffusion region 8 1 is located next to the shallow trench isolation 7 7 for circuit connection to the power pin V sA, and another P diffusion region 80 is located The shallow trench isolation 78 is used as a circuit connection with a substrate trigger circuit 82. Among them, the parasitic lateral bipolar transistor 84 formed under the NMOS 73 can be triggered by a trigger current (I trig) conducted by the P diffusion region 80. In the typical 0.18 // 111 process, the depth of the shallow trench isolation 77, 78 is mostly between 0 · 4 ~ 0.5 / im (counted from the surface of the Shixi wafer), and the source 7 and the drain 7 6. The depth of the junction of the diffusion layer is only 0 · 1 5 / zm. Therefore, although increasing the depth of the shallow trench isolation 77, 78 can provide better isolation effects for the adjacent diffusion regions of rain, deepening the depth of the shallow trench isolation 7 8 will also reduce the triggering effect of the NMOS 73 substrate. This is because when the depth of the shallow trench isolation 78 increases, the trigger current conducted by the p-diffusion region 80 will be

Page 11 2002. 07. 09.011 501263 V. Explain that m '…. It will be difficult to reversely bias the base of the parasitic lateral bipolar transistor 8 4 located in the substrate, which will cause the The speed at which the parasitic lateral bipolar transistor 84 is triggered is slowed, and the ESD protection effect of the NMOS 73 on the internal circuit (not shown) is greatly reduced. Therefore, how to develop an ESD protection circuit that prevents the above-mentioned currents from flowing through the surface channel and slows down the triggering period of the parasitic lateral double-transistor transistor due to shallow trench isolation has become important in the present invention. aims. SUMMARY OF THE INVENTION Therefore, the main purpose of the present invention is to provide an ESD protection element structure with high substrate-triggered effect and its application circuit to improve the driving speed of the ESD protection circuit and simultaneously solve the conventional heat dissipation problem. 'In the most preferred embodiment of the present invention,' the ESW stay-care element is formed on a well, which includes a first NMOS and a second NMOS, and three domains are set in the P-well, and the first The third P-signal field is used to connect to the & Vss power terminal, and the second p-doped region is set in the middle of = one and the second NMOS, and is used to connect a P-type well bias + brother. Trigger current is a first biased circuit) to induce—the substrate touches a Wel 1 (substrate-trigger current, I trig) between diffusion regions—NMOS; ^ (dummy gate) is set at the first NMOS And the second j; a second dummy gate is disposed in the second P diffusion region and the first

501263 V. Description of the invention (8), a first shallow trench isolation (ST I) is used to isolate the first NMOS and the first P region, and at least one second shallow trench isolation is used to isolate the second isolation. S and the third P 1 region, wherein each of the NM 0 S non-pole and the source will form a parasitic lateral npn BJT with the P-well, and make the substrate A trigger current (1 trig) can flow through the P-wells under each of the dummy gates to turn on the adjacent parasitic lateral bipolar transistors, thereby enabling the ESD protection element structure to discharge the electrostatic current quickly. To V ss power supply pin. Because the present invention uses a dummy gate to block the drain diffusion region located in the metal-oxide-semiconductor transistor and the shallow trench isolation connected to the diffusion region of the substrate driving circuit, and uses the substrate to drive the circuit. The substrate driving current technology accelerates the release of ESD current, thereby solving the problem of difficult heat dissipation caused by ESD current flowing to the surface channel. Therefore, the present invention can not only effectively increase the strength of ESD, but also increase the effect of M0S on ESD protection, and such a M0S junction More in general completely compatible with CMOS process. Refer to the detailed description of the invention Figure VII, Figure VII of the present invention has a high substrate priming effect

A cross-sectional view of a substrate-triggered effect ESD protection device structure. As shown in FIG. 7, the ESD protection element 90 structure is formed on a p-type well g 2 of a p-substrate 9 1. The ESD protection element 9 0 structure includes two n Μ 0 S elements 9 3 and is located in the P-type well 9. In 2, two electrical connections are connected to the ρ diffusion region of the Vss power pin 9 9. One electrical connection is

ill ill page 13 501263 | III, Weiming Ming (9). ———— ^ ———— P diffusion area 100 of a base trigger circuit 102, two dummy gates 98 are provided at each NM0S9 3, and Between the p-diffusion regions 100 and two shallow trench isolations are provided between each NMOS 93 and each p-diffusion region 99. Among them, each nm〇s 93 also includes a source electrode 95 electrically connected to the Vss power pin, an electrical source connected to a ~ 96 input / output (I / O) buffer pad (not shown), a drain electrode 96, a doping Polycrystalline silicon gate 9 4 and two lightly doped drain electrodes 9 7. Since the drain 96, the source 95, and the P-well 92 of each NMOS 93 constitute a parasitic lateral η-pn BJT 104, Chu can be quickly triggered by the substrate trigger circuit 102. The substrate-triggered effect of the 90 structure of the ε SD protection element is improved. Therefore, when the parasitic pseudo-ambient transistor 1 〇 4 is triggered by the substrate trigger circuit 1 〇 2 ', that is, the parasitic lateral bi-electron transistor 1 〇 4 will be conducted by the current located in the diffusion region j 1 0 0 When triggered, the electrostatic current in the ESD protection element 90 structure introduced by the input / output (I / O) buffer pad can be quickly released through the V ss power pin. It is worth noting that each NMOS93 in the above-mentioned structure of the ESD protection element 90 of the present invention is a standard NMOg structure. However, the NMOS9 3 combined with the dummy gate 98 can also be directly regarded as a high-level trigger. Effect of N-channel metal oxide semiconductor (NMOS) device structure. Because there is no shallow trench isolation region between each of the NMOS93 and P diffusion regions and 100 in the structure of the ESD protection element 90, the substrate trigger current generated by the substrate trigger circuit 1 02 can be conducted to the faster Parasitic transverse diploid

501263 V. Invention No. 205 base of transistor 104. Therefore, the parasitic lateral bipolar transistor 104 in the NMOS element 93 proposed by the present invention can be triggered quickly and the current of £ 80 can be quickly discharged. The use of 003 element 93 structure will make the turn-on speed of NMOS 93 in the £ 80 protection circuit not slow down due to shallow trench isolation in deep sub-micron processes of CMOS. In addition, the substrate triggering effect can trigger the parasitic lateral bipolar transistor 104 in the NMOS device 93 and cause the current to flow through the substrate of NMOS 93 instead of the surface channel of NMOS93. It is also… because the base of NMOS93 has a large volume, it is relatively easy to dissipate the heat generated by ESD electricity and current. Therefore, when the NiMOS 9 3 mentioned in the present application is compared with the N M 0 S in the gate drive E S D protection circuit design 10 ′, it can withstand a larger E S D when occupying the same area of the wafer chip. And compared with the traditional substrate trigger with shallow (B trench isolation area) [Compared to 0373, the parasitic lateral bipolar transistor in the present invention? ^ 0393 when the ESD current is released, the start-up speed is also faster. Just borrow The mask pattern can be changed without changing other processes. The structure of the NMOS device with high substrate triggering effect combining the dummy gate 98 and NMOS93 can be seen in the present invention. Please refer to FIG. The layout of the NM0S element 9 3 is shown in FIG. 7, and the sectional view along the dotted line 7-7 ′ is shown in FIG. 7. As shown in FIG. 8, the dummy gate G 2 9 8 is a doped polycrystalline silicon material, but the dummy gate 9 8 The left half is close to the N diffusion region 9 6 and the right half is close to the P + diffusion region 1 0 0. The impurity substitution is not the same. The dummy gate 9 8 is designed to replace the P diffusion region 1 0 0 and the drain 9 6

Page 15 501263 V. Description of the invention Π!) The formation of shallow trench isolation (STI) between NMs does not have any function in NMOS device 93. Therefore, the doping concentration and doping form of the dummy gate 98 will not have any effect on the NMOS device 93. In order to be completely compatible with the existing CMOS deep sub-micron process, the dummy gate 98 is designed as shown in Figure 7 and As shown in Figure 8. The channel length of the dummy gate 98 may not be equal to the channel length of each NMOS93. Because the drain 96 and the source 95 in NMOS 9 3 are N diffusion regions, for the convenience of the process and the increase of positioning tolerance, the gate region of the dummy gate 9 8 near the drain 9 6 can be implanted the same N ions, and other gate regions close to the P diffusion region 100 can implant the same P ions as the drain and source in PMOS. Therefore, on the polycrystalline silicon material constituting the dummy gate 98, there will be N dopants and P dopants. The layout of this component structure is shown in Figure 8. Therefore, with proper layout design, the NMOS component 9 3 triggered by this substrate can be widely used in general C M 0 S integrated circuit products. 0

The concept of the present invention can also be applied in the shallow trench isolation process of CMOS deep sub-micron to increase the turn-on speed of the PMOS device in the ESD protection circuit. Please refer to FIG. 9, which is a cross-sectional view of an ESD protection ion device structure with a high substrate-triggered effect of the present invention. As shown in FIG. 9, the ESD protection element 1 The 10 structure is formed on an n-type well 11 2 of a p substrate 1 1 1. The ESD protection element 110 structure includes two PM0S elements Π3 located at N.

501263

In the well 1 12, the 'two electrically connected to the n diffusion region 1 of the VDD power pin 1 1 9, _ is electrically connected to the N diffusion region 1 2 2 of the substrate bias circuit 1 2 2 and two dummy idler poles 1 1 8 is provided between each PMOS 1 1 3 and the N diffusion region 120, and two shallow trench isolations are provided between each PMOS 1 13 and the N diffusion region 1 19. Among them, each P Μ 0 S 1 1 3 also includes a source 1 15 electrically connected to the v DD power pin, and an electrical pole connected to an input / output (1 / 〇) buffer pad (not shown). 1 1 6. A doped polysilicon gate 1 丨 4 and two lightly doped drain electrodes 117 °. Since the drain 1 1 6 of each PM0S 1 1 3 and the source 1 1 5 and the N-type well 1 1 2 constitute a Parasitic lateral pnp BJT i 2 4 ′ can be quickly triggered by the substrate bias circuit 1 2 2 to improve the substrate-triggered effect of the ESD protection element 1 1 〇 structure ). Therefore, when the parasitic lateral bipolar transistor 1 2 4 is triggered by the substrate bias circuit 1 2 2, that is, the parasitic lateral bipolar transistor 1 2 4 will be conducted by the current conducted in the diffusion region 1 2 0 When triggered, the electrostatic current in the ESD protection element 1 10 structure introduced by the input / output (I / 〇) buffer pad can be quickly released through the V DD power pin. Similarly, compared with the conventional substrate-triggered ESD protection element, the parasitic lateral bipolar transistor 124 in the ESD protection element 110 of the present invention has a faster opening and starting speed when the ESD current is released, and the ESD current system is Flow through the base of? 1 ^ 103113, not through? 108113 surface channel, so more capacity

Ml 111

501263 _, I. Sound · Ι_Μ-· * " · I Μ I l_M_lj 麻 一 ... V. Description of the invention U3) — — 1 Easily dissipates heat generated by ESD current. Please refer to FIG. 10. FIG. 10 is a schematic diagram of an electrostatic discharge protection circuit of the input stage according to the present invention. As shown in Fig. 10, the ESDK protection circuit 2 of the input stage can be explained by the base trigger technique of the PM0S element and the NMOS element in the present invention. When a positive ESD voltage pulse is applied to the input buffer 2 丨 0, and vs is grounded and v⑽ ^ is floating, a sudden increase in ESD pulse will pass through a capacitor, 2 2 to a NMOS 0 2 The gate 2 of 4 generates a coupling voltage (C0Upied vo 11age), and the coupling voltage can be maintained for a longer time on the gate 2 of NM0S 2 0 4 due to the presence of the resistor 208. It is scared that when the coupling voltage is greater than the initial voltage (vth) of NMOS, the transistor 204 will be turned on and the part of the current of the positive ESD voltage pulse is conducted through the p-diffusion region 100 (see Figure 7) to be introduced as ESD protection NMOS 212 in the P-well (or P-type substrate). When a trigger current is generated by the transistor 204, N M 0 S 2 1 2 as ESD protection will be turned on faster, so that the e SD current is quickly released from the buffer pad 2 1 0 to the V ss power pin Without flowing to an internal circuit 211. The substrate trigger current generated by transistor 2 0 4 can trigger the parasitic lateral bipolar transistor 2 1 4 in N M 0 S 2 1 2 to direct the current to the substrate of NMOS 2 1 2 instead of to NMOS 2 1 2 surface channels, plus the base of NM 0 S 2 1 2 has a large volume that can dissipate the thermal energy generated by the current of £ 80, so 008212 can withstand a larger voltage of £ 81).

Page 18 501263 Invented π Ming (u) pressure pulse is applied to the input buffer 2H, and the Vss pole 215 and the P-type, (P-type substrate) :. J = S 12 of > and biased Junctlon) and was released to the v-page white partial fort junction (forward junction operation voltage (~ .. 8 — connected to two. Because ... withstands large ESD voltage. V) car乂 Low ', therefore, M0S 2 丨 2 can be equal to,' and when ΓΛ polarity ΛΛδΙ) 士 电 | Pulse is applied to the input buffer 2 Mi ,; 5/9 q ς S and \ 丨 S sweat, positive voltage The pulse will be released to the V⑽ power pin through the forward bias interface # jUnCtl0n) formed by the drain 35 of PMOS and Lijing (N-type substrate). The operating voltage from the H to the fortress interface (~ 0 "-100) is lower, so pM0s 2 3 2 can withstand a larger e SD voltage. When a negative ESD voltage pulse is applied to the input buffer Pad 2 丨 〇, and when VD is grounded and V s is floating, the sudden increase of ESD pulse will generate a coupling voltage through a capacitor 2 2 2 to a gate 2 2 6 of PM0S 2 24 (coupled

voltage), and the coupling voltage can be maintained on the gate 2 2 6 of PM0S 2 24 for a long time due to the presence of the resistor 2 28. When the | Mach voltage is less than the start voltage (Vth) of PM0S 2 24, the transistor 224 will be turned on, and the current of the negative ESD voltage pulse that conducts part will be introduced into the N diffusion region 120 (see Figure 9) as an ESD. Protected pMOS 2 32 in N-type wells (or N-type substrates). So ’when a trigger current is generated by transistor 2 24,

Page 19 501263 V. Description of the invention (: 15) The protected PM0S 2 3 2 will be turned on quickly, so that the ESD current is quickly released from the buffer pad 210 to the V DD power pin. The substrate trigger current generated by transistor 2 2 4 can trigger the parasitic lateral bipolar transistor 2 34 in PM0S 2 3 2 to direct the current to the substrate of PMOS 2 3 2 instead of the surface channel of PMOS 2 3 2 , Plus the base of PM0S 23 2 has a larger volume that can dissipate the thermal energy generated by the ESD current, so? ^ 108 2 3 2 can withstand a large voltage of £ 81). In the second embodiment of the present invention, the same concept can also be applied to the output stage

E S D protective circuit. FIG. 11 is a schematic diagram of an electrostatic discharge protection circuit 300½ of an output stage according to the present invention. As shown in FIG. 11, the output stage ESD protection circuit 300 can be explained by the substrate triggering technology of the PM0S element and the NM0S element in the present invention. Among them, the circuit design of the ESD protection circuit 300 is similar to the input stage ESD protection circuit 2000. The ESD protection circuit 300 also includes a pre-driver circuit (321), which is not included in the internal circuit (311). versus

E S 2 protection circuit between 3 0 0. As shown in Figure ^-, when a positive E S D

When a voltage pulse is applied to the wheel-out cushion pad 3 丨 〇, and vs is grounded and vd is tickled, f 1 〇a 11 ng), the sudden increase of E s D pulse will pass through a capacitor 3 02 to a NMOS. 3 0 4's gate 3 0 6 generates a coupled voltage 'and the coupling voltage can be maintained for a longer time on the gate 3 0 6 of NM〇s 3 04 due to the presence of the resistor 30 . When the engaging voltage is greater than the initial voltage (Vth) of NMOS, the transistor 3 0 4 will be

Page 20 501263 V. Invention (16) Turns on and conducts part of the current of positive ESD voltage pulses through p-diffusion area 100 (see Figure 7) into a P-type well of NMOS 312 as ESD protection (or P-type substrate). When a trigger current is generated by the transistor 304, ^ 312, which is the protection of £ 80, will be turned on quickly, so that the £ 80 current is quickly released from the buffer pad 3 10 to the 'vss power pin. The substrate trigger current generated by transistor 3 0 4 can trigger the parasitic lateral bipolar transistor 314 in NMOS 31 2 to direct the current to the substrate of 008312, rather than to the surface channel of Li 08 3 12 'plus NMOS The base of 3 12 has a larger volume that can dissipate the thermal energy generated by the ESD current, so N M 0 S 3 1 2 can withstand a larger ESD voltage. When a negative E + SD voltage pulse is applied to the input buffer pad 3 1 〇, and when Vs is grounded and VD floats, the 'negative ESD voltage pulse will pass through the forward bias junction (f 〇) formed by the drain 3 1 5 of NMOS 31 2 and the P-type well (P-type substrate). rwar 廿 biased junction) and is released to the Vss power supply pin. Because the operating voltage (~ 〇 · 8-〇v) of the forward biased junction is lower, nm〇S 312 can withstand a larger ESD voltage.

Ϊ Two positive ESD voltage pulses are applied to the input buffer 塾 310, and when V ^ ⑽ is connected, the positive voltage pulse will pass through the four ^^ poles. (N-type substrate,) forward direction The bias interface (forward is released to the Vdd power pin. Because the operating voltage of the forward bias interface (~ ns, larger ESD voltage. · 8 — L0V) is low, PM0S 3 3 2 can withstand

Page 21 501263 Five 'invention description (17) When a negative ESD voltage pulse is applied to the input buffer 塾 3 1 〇, and v DD is connected to ground and V s is connected, the sudden increase of ESD pulse will pass through a capacitor 3 2 2 A coupled voltage is generated for a gate 32 6 of a PM0S 32 4, and the coupled voltage can be maintained on the gate 3 2 6 of P M 0 S 3 2 4 due to the presence of the resistance 32 8 Longer time. When the coupling voltage is less than the start voltage (Vth) of PM0S, PM0S 324 will be turned on, and the current of the negative ESD voltage pulse of the conduction part will be introduced into the PM0S 3 32 as ESD protection through the N diffusion region 120 (see Figure 9). N-well (or N-type base). When a trigger current is generated by PM0S 324, PM0S 332 as ESD protection will be turned on faster, so that the ESD current is quickly released from the buffer pad 3 1 0 to the V DD power pin. The substrate trigger current generated by P Μ 0 S 3 2 4 can trigger the parasitic lateral bipolar transistor 3 34 in PMOS 3 3 2 to direct the current to the substrate of P Μ 0 S 3 3 2 rather than to P Μ The surface channel of 0 S 3 3 2 plus the base of PM0S 3 3 2 has a large volume that can dissipate the thermal energy generated by the ESD current, so? ^ 108 3 3 2 can withstand a large £ 80 voltage. Because E S pulses can pass through the ν D and V ss power pins of IC products, the same inventive concept can also be applied to power-rail ESD clamp circuits. The third embodiment of the present invention is an ESD protection circuit design designed for a power line ESD clamping circuit. Please refer to FIG. 12. FIG. 12 shows the ESD clamping voltage of the power line of the present invention. The positive ESD voltage pulse is applied to the V ss power pin and the v DD power pin.

Page 22 501263 Five 'Invention Description Π8) At this time, VS is grounded at this time, and the sudden increase of ESD pulse will generate a coupled voltage through a capacitor 4 0 2 to a gate 4 0 6 of NM0S 4 0 4 , And the coupling voltage can be maintained on the gate 406 of NM0s 4 0 4 for a long time due to the presence of the resistance 408. When the coupling voltage is greater than the initial voltage (Vth) of NM0S 4 04, NM0S 4 04 will be turned on, and the current of the positive ESD voltage pulse that conducts part of it will be introduced as an ESD protection through the p scatter region 100 (see Figure 7) NMOS 412 in the P-well (or P-type substrate). When a trigger current is generated by NM0S 404, N M 0 S 4 1 2 as ESD protection will be turned on faster, so that the e SD current is quickly released from the V DD power pin to the V ss power pin without Flow to an internal circuit (interna 1 circuit) 4 1 1. The substrate trigger current generated by transistor 4 0 4 can trigger the parasitic lateral bipolar transistor 4 1 4 in NMOS 4 12 to direct the current to the substrate of N M 0 S 4 1 2 rather than to n M 0 S The surface channel of 4 1 2 plus the base of NM0S 41 2 has a large volume that can dissipate the thermal energy generated by the current of £ 30, so 008412 can withstand a large voltage of £ 80. When a negative ESD voltage pulse is applied to the Vss power pin and the power pin, Vs is grounded at this time, and the negative ESD voltage pulse will pass through the drain 4 1 5 of NM〇s 412 and the P-type well (P-type substrate ) Constitutes a forward biased junction (forward biased junction) and is released to the Vss power supply to operate as a forward biased junction (~ 0. 8 ~ 1β 〇ν $, 4 1 2 can withstand larger ESD voltage. _

foot. because

NM0S

501263 I five, # 明 说明 Π9,

SS The gate 4 0 6 of the transistor 4 04 is electrically connected to the power supply pin v via the resistor 4 0 8 so that the transistor 4 0 is in a closed state. Therefore, in a normal operating situation, the transistor 4 0 4 is the closed state, so there will be no trigger electricity flowing into the base (? -Type well) of question 03412, and the gate 03412 will remain closed; 1 ". Please refer to FIG. 13. FIG. 13 is a schematic diagram of another embodiment of the power-rail ESD clamp circuits 45 of the present invention. As shown in FIG. 13, the substrate trigger circuit is composed of a bipolar 4 6 6, a resistor 4 6 8 and a P MOS 4 5 4. Ugly by applying the concept of substrate triggering technology, the input / output stage ESj) protection circuit can also design Zener diodes (26116 ± ~ (1 丨 〇 (16) .. See ^ 1 Fourteen and Ten Fifth, FIG. 14 is a schematic diagram of an input-level electrostatic discharge protection circuit 500 according to the present invention, and FIG. 15 is a schematic diagram of a round-out electrostatic discharge protection circuit 600 according to the present invention. As shown in FIG. 14, when a positive When the ESD voltage pulse is applied to the output buffer 塾 510, and Vs is grounded and VD is connected (floatlng), the sudden increase in ESD pulse will cause the collapse of a Zener diode 5 1 6 and cause some positive ESD. The voltage pulse current is introduced into a P-type well (or p-type substrate) of NMOS 512 as ESD protection through a p-diffusion area (see Figure 7), so that the ESD current is quickly released from the buffer pad 5 10 To the v ss electrical & pin without flowing to an internal circuit 511. Since the substrate trigger current turned on by the quina diode 5 1 6 can trigger the parasitic lateral in n μ 〇 5 2 Bipolar transistor 5 1 4 to direct current to the substrate of v M 0 S 5 1 2 08,512 passage surface, together with the substrate off 03,512

501263 V. Description of the invention ¢ 20) .. There is a large volume that can dissipate the thermal energy generated by the ESD current, so the NMOS 5 1 2 can withstand a larger ESD voltage. When a negative ESD voltage pulse is applied to the input buffer 塾 5 1 0, and VD is connected to ground and V s is connected, the sudden increase of the ESD pulse will cause the breakdown of a quina diode 5 3 6, causing some The negative ESD voltage pulse current is introduced into an N-type well (or N-type substrate) of PMOS 5 32 as an ESD protection through an N diffusion region 120 (see FIG. 9), so that the ESD current is quickly released from the buffer pad 510. To VDD power pin. Because the substrate trigger current turned on by the quina diode 5 3 6 can trigger the parasitic lateral bipolar transistor 5 3 4 in PMOS 5 3 2 to direct the current to the substrate of PMOS 5 32 instead of PMOS 5 3 2 surface channels, plus the base of PMOS 53 2 has a large volume that can dissipate the thermal energy generated by the ESD current, so PMOS 5 3 2 can withstand a larger ESD voltage. As shown in Fig. 15, the output stage electrostatic protection circuit 600 is composed of two quina diodes 616, 636, one NMOS 612, one PMOS 632, and one parasitic transverse bipolar transistor 61 4 in NMOS 612 and A parasitic lateral bipolar transistor 6 3 4 in a PMOS 6 3 2 is formed. The output stage ESD protection circuit 600 is located between a buffer unit 610, a pre-driver circuit 621, and an internal circuit 611. Its operating principle is the same as the output stage ESD protection circuit 500 shown in Figure 14.

The same concept can be applied to the power line ESD clamp circuit. Please refer to FIG. 16 and FIG. 17. FIG. 16 and FIG. 17 are power cord ESD of the present invention.

Page 25 501263 V. Description of the invention (21 :) Schematic diagram of power-rail ESD clamp circuit, 7nn, snn. As shown in Figure 16, when a positive ESD voltage = :: V ss power pin and Between the V DD power pins, at this time, v S is grounded. Suddenly increased ESD pulses will cause the Zener diode 7 1 6 to collapse, causing part of the ^ ESD voltage pulse current to pass through a P diffusion region 10 〇 (See Figure 7.1 / N-type P-well (or P-type substrate) as ESD protection, so that the ESD current is quickly released to the V ss power supply pin 'without flowing to an internal circuit. ) 711 ... Because of the Kina Diode? 6 The substrate trigger current conducted by 6 can trigger the parasitic ^ to the carrier crystal 714 in NM0S 71 2 to direct the current to the substrate of NM0S 712, and " Non- / direction N: 2 71 2 surface channel 'plus the base of NM0S 712 has a large volume that can dissipate the thermal energy generated by the ESD current. Therefore, NM0S 2 can be carried as a large ESD voltage. Q 、 々, again into / as shown in Figure 17, the power line ESD clamping circuit 8 0 0 is a base handle two poles f 816, a PM0 S 83 2 and a parasitic transverse bipolar transistor 834 in PM0S 8 3 2 operate on the same principle as the power line esd box circuit 7 0 0 shown in Figure 16. The ESD voltage pulse will cause a base The collapse of the nano-diode 7 816 caused a triggering current and introduced an N-type well (or N-type substrate) of PMOS 8 32 as an ESD protection through an N-diffusion region 120 te (see Fig. 9). ) "And turn on the parasitic lateral bipolar transistor 834 in PM0S 832 to release the ESD current" to protect the internal circuit (in cerna 1 circuit) 81

Page 26 501263 V. Description of the invention (22) In short, the method for manufacturing (ο η-chip) ESD protection circuit on a wafer is between the drain and the doped region connected to the substrate bias circuit. A dummy gate was added to replace the shallow trench isolation area. Since the substrate trigger current I μ is generated by the substrate trigger circuit, the shallow trench isolation area is reduced, so it will be easier to reach the base of the parasitic lateral bipolar transistor in the MOS device and structure. Therefore, the parasitic lateral bipolar transistor in the MOS device structure can be driven faster and more efficiently. Not only does the ESD current flow into the substrate of the M0S structure quickly, it is also not concentrated on the surface channels of the M0S structure, so it can effectively avoid the problem of the M0S component being burned due to the difficulty of heat dissipation. Compared with the conventional 6-force ESD protection circuit manufactured on the wafer (ο η-chi ρ), the substrate-triggered effect of the present invention NM 0 S element structure, ESD protection element, and ESD protection circuit can It can be driven faster and more efficiently to achieve the purpose of accelerating the discharge of ESD current, and solve various problems of conventional ESD protection components. It is very suitable for integrated circuit products in CMOS processes below 0.25 microns. The above are only the preferred embodiments of the present invention. Any equal changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the patent of the present invention.

501263 Simple illustration of the diagram Simple illustration of the diagram Figure 1 is a circuit diagram of the ESD protection design of the conventional gate drive technology. Figure 2 is a schematic diagram of a conventional gate driving NM0S path in an ESD protection circuit. ,

Figure 2 is a schematic diagram showing the relationship between the gate drive voltage of a conventional gate-driven NM 0 S element and the human body's electrostatic discharge value. Figure 4 is a circuit diagram of the E S D protection design of the conventional substrate trigger technology. Figure 5 is a schematic diagram showing the relationship between the substrate trigger voltage of the conventional substrate-triggered NMOS device and the electrostatic discharge value of the human body.

Figure 6 is a cross-sectional view of a NMOS in a conventional substrate-triggered ESD protection circuit. FIG. 7 is a cross-sectional view of a structure of an N-type ESD protection element having a high substrate triggering effect according to the present invention. FIG. 8 is a schematic layout diagram of the NMOS device of the present invention. Fig. 9 is a cross-sectional view of the structure of a P-type ESD protection element having a high substrate triggering effect according to the present invention. FIG. 10 is a schematic diagram of an input stage electrostatic discharge protection circuit according to the present invention.

FIG. 11 is a schematic diagram of an output stage electrostatic discharge protection circuit according to the present invention. FIG. 12 is a schematic diagram of a power line ESD clamping circuit according to the present invention. FIG. 13 is a schematic diagram of the power line ESD clamp circuit of the present invention. FIG. 14 is a 7F schematic diagram of the input stage electrostatic discharge protection circuit of the present invention. FIG. 15 is a schematic diagram of an output stage electrostatic protection circuit according to the present invention.

Page 28 501263 Description of the fixed type Figure 16 is the ESD clamping circuit of the power line of the present invention. Figure 17 is the schematic diagram of the ESD clamping circuit of the power line of the present invention. Detailed description 1 0, 50, 4 0 0 ESD protection circuit 12 '30, 34, 52 > 70' 73 ^ 90 93, 204, 312 412, 4 04, 512, 61 2, 71 2NMOS 13, 35, 53 '75 ^ 95 to 115 source 14, 36, 5 4, 76 ^ 96 > 116, 235 Drain 16 '55 \ 206 > 226 > 3 0 6' 406 Gate 18, 40, 58, 210 ^ 51 0 «6 10 Buffer pads 64, 84, 104, 214, 414, 514 534, 614, 714, 834 Parasitic lateral bipolar transistor (BJT) 110, 113, 232, 332, 224, 420, 426, 454; Figure.丨. Circuit design 212, 6 34, ^ 532 to gate (LDD) Circuit 632 832 PMOS 37 ^ 74 ^ 94, 114 Substitute heteropoly chip 38 '79 ^ 97 ^ 117 Lightly doped drain 6 0' 82 to 102 ,, 122 substrate trigger electric 8 80 80 99> 100 P diffusion area 2 (L · 42 gate bias 22 internal circuit 23 ^ 63 wire 3 71 71 > 9 111 111 P-type substrate

501263 _ simple description 56 '65 ^ 105 32' 72 ～ 92 > 112 77 ～ 78 202 ^ 222 ^ 302 119 '120' 2 0 8 ^ 2 2 8 ^ 3 0 8 ^ 418 98, 118 200 '500 300 ^ 600 4 0 0, 700, 800 466 516, 536, 6i6, 636, base P-type well shallow trench isolation capacitor N diffusion area resistance dummy gate (G 2) input stage ESD protection circuit output stage L · SD protection circuit ESD clamped circuit diodes 7 1 6 and 8 1 6 kina diodes

Page 30

Claims (1)

501263 cavity, patented by Patent No. 501 · A high substrate-triggered ef feet N-channel metal oxide semiconductor (NM0S) element structure, the NMOS element structure is formed on a substrate in a P manhole, The NMOS device structure includes: a gate provided in the P-well; a first N diffusion region provided in the P-well; used as the pole of the NMOS device structure; a second An N-diffusion region is provided in the P-type well and is used as a source of the NMOS device structure, and the first N-diffusion region, the P-type well, and the second N-diffusion region form a parasitic lateral η-ρ collector, base, and emitter of a parasitic lateral η-Pn BJT; a first P-diffusion region is provided in the P-type well for electricity A p-well biased circuit is connected; a dummy gate is provided between the first n-diffusion region and the first p-diffusion region; ', a second P The diffusion area is set in the P-well, and is used to respect a V ss power pin (V ss P o w r r t e r m i n a 1); and a shallow trench isolation (ST I first P diffusion region to isolate the second N diffusion region from the r scatter region; Wherein when the P-type well bias circuit (p — weU bias d =, bottom trigger current (, the base trigger current 1, the first p diffusion region flows through the ^ 1 忒 parasitic transverse direction below the dummy gate) Bipolar transistor for electrical connection: a constant current is quickly conducted to the source via the source Page 501 501 90117747 Date of repair 6. Application for patent scope 2. For example, the NM0S element structure of the application scope item 1 includes a plurality of lightly doped drains (LDDs) located in the P-type wells around the gates. . 3. The NMOS device structure according to item 1 of the application scope, wherein the dummy gate system includes a P-type dopant and a surface dopant. 4. The NMOS device structure according to item 1 of the application scope, wherein the specific current is an electrostatic discharge (ESD) current. 5. A P-channel metal oxide semiconductor (PMOS) device structure with a high substrate triggering effect (subs trate-tr i ggered eff ect). The PMOS device structure is formed on an N-type well of a substrate. The PMOS device structure includes : A gate, provided in the N-type well; a first P diffusion region, provided in the N-type well, and used as a drain of the PM0S element structure; a first P diffusion region, provided It is used as the source of the PMOS device structure in the N-type well, and the first P-diffusion region, the n-type well, and the first P-diffusion region form a parasitic lateral ρ-η-ρ double carrier Transistor The collector, base, and emitter of the parasitic lateral pnp BJT; a first N-diffusion region is provided in the N-type well for electrically connecting a N-type well bias voltage Circuit (Piell biased circuit); a dummy gate is provided in the first P diffusion region to Page 32. 2002. 07. 09. 032 Six Mffd Amended in January 90, 117747, the application volume between iilli and the first N scattered area; a second N diffusion area, which is located in the N-type well, is used to electrically connect a V DD power terminal (VDD power terminal); and a shallow trench isolation (ST I) for isolating the second P diffusion region from the second N diffusion region; wherein when the N-type well bias circuit (P -well biased circuit) when a substrate trigger current (I trig) is induced, the substrate trigger current (I trig) will flow through the N-type well below the dummy gate to the first N scatter region to open the parasitic A lateral bipolar transistor, so that a specific current electrically connected to the drain is quickly conducted to the V DD power pin via the source. 6. If the PM0S element structure 2 of item 5 of the application scope includes a plurality of lightly doped drain electrodes (LDDs) provided in the N-type wells around each of the gate electrodes. 7. The PMOS device structure of item 5 of the application, wherein the dummy gate system includes a P-type dopant and an N-type dopant. 8. The PM0S device structure according to item 5 of the application, wherein the specific current is an electrostatic discharge (ESD) current. 9. An ESD protection element structure, the ESD protection element structure is formed on a P-type well of a substrate, and the ESD protection element structure includes: at least one NMOS, provided in the P-type well, and The drain of the NM0S, the P 2002. 07. 09. 033 Page 33 501263 VI. + Please specialize in range wells and the source of the NMOS to form a parasitic lateral npn bipolar transistor (parasitic lateral η-pn BJT). The pole and the source of the NM0S are electrically connected to an input / output buffering pad (I / O buffering pad) and a V ss power terminal, respectively; at least one first P diffusion region, where In the P-well, it is used to electrically connect a P-well biased circuit; at least one dummy gate is provided in the NM 0 S and the first P diffusion region Between; at least a second P diffusion region disposed in the P-type well for electrically connecting the V ss power pin; and at least one shallow trench isolation (STI) for isolating the N M 0 S from the second P 1 diffusion region; wherein when an ESD voltage pulse is applied to the input / output (I / 0) buffer, the P-well biased circuit will induce a substrate trigger current '( I trig) and flows directly from the first P diffusion region through the P-type well below the dummy gate to the The base lateral bipolar transistor of the trigger electrode green parasitic lateral bipolar transistor, the current of the ESD voltage pulse to the quick-release to the V ss power supply pin. 10. If the ESD protection element structure of item 9 of the application scope, wherein the parasitic biased bipolar transistor that is triggered will release most of the current of the ESD voltage pulse to the P-type well below the NMOS Vss power pin instead of flowing through the surface channel of the NMOS. 501263 6 'application for patent scope, 1 1 · If the ESD protection element structure of item 9 of the application scope, the dummy idler system includes P-type dopants and N-type dopants. 1 2 · An ESD protection element structure (ESD pr otecti n device structure), the ESD protection element structure is formed on an N-type well on a substrate. The ESD protection element structure includes: at least one PMOS, provided in In the N-type well, the drain of the PM0S, the: and the source of the PM0S form a parasitic lateral ρ-η-p bipolar transistor (parasitic lateral ρ-np BJT), and The sum electrode and the source of the PM0S are respectively electrically connected to an input / output buffer pad, an I / O buffering pad, and a VD D power pin (VDD ρ 〇 wer terminal); at least one first N diffusion region, It is arranged in the N-type well, and is used for electrically connecting an N-well biased circuit; at least one dummy gate is arranged in the P M 0 S and the first N diffusion region Between; at least a second N-thickness region provided in the N-type well for electrically connecting the V DD power pin; and at least a shallow trench isolation (STI) to isolate the PMOS and the second N f Diffusion region, where when an ESD voltage pulse is applied To the input / output (1/0) the buffer Sook, the N-well bias circuit (P-well biased circuit) Preparation of a substrate to induce trigger current (I trig), by the parasitic lateral bipolar ^ Page 35 501263 | 一 * ^ '........ ··· μ 一一 广 n I ^ ........ μ 一一 知 ⑼ ~. ** " *** »^ Catch you. ___ Mountain, 6 'Application Dedicated to: Yuanwei "' — The base of the crystal flows directly through the N-type well below the dummy gate to The first N diffusion region turns on the parasitic lateral bipolar transistor to quickly release the current of the ESD voltage pulse to the ν DD power pin. 13. The ESD protection element structure according to item 12 of the application scope, wherein the triggered parasitic bias to the bipolar transistor will release most of the Esj) voltage pulse current to the N-type well below the PM0S to The Vd |) power pin, instead of flowing through the surface channel of the P MH 0 S. 14. The ESD protection element structure according to item 12 of the application scope, wherein the dummy gate system includes a P-type dopant and an N-type dopant. , X 15 · —A kind of static discharge protection circuit (eiectr〇 static discharge protection circuit), the ESD protection circuit is electrically connected to an input / output buffer (I / O buffering pad), an internal circuit, an vss power pin (Vss power 61'111 丨 1 ^ 1) and a 71) 1) power pin, the £ 80 protection circuit includes: a first ESD protection element structure, electrically connected to the v% The power pin, the input / output buffer pad and the internal circuit. The first ESD protection element structure includes: a P-type well; At least one first NMOS is disposed in the P-well, and the drain of the first nmOS, the P-well, and the source of the first NMOS form a parasitic lateral η-ρ -η double-carrier electricity Crystal (parasitic lateral η-pn BJT), and 501263 A Patent scope: Ϊ and Modi-the source of the coffee is connected to the J / output buffer and the Vss power supply connected to at least a first P diffusion region, respectively, provided here: xi m to ΪΓ A dummy gate is located between the / NMMOS and the brother-P diffusion zone; the human connection and domain are set in the P-type well, and (STI) is used to isolate The at least one second P diffusion region is connected to the V ss power pin; and at least one first shallow trench isolates the second P diffusion region; an input / output 1 ^ direction # bottom bias circuit is electrically connected to the ^ Power pin, the I / O buffer pad, the -P diffusion area of the internal circuit tank element junction, the forward direction and the J-factory: ESD to protect a second NMOS, the second NMOS7 pressure- The circuit contains ~ Mingyang "-PW) and the vss power pin power supply; via -Sakai II: Connected to the wheel input / output buffer 亥, 1H is connected to the second electronic element of the ff NM0S drain And the gate of a second electric early one NM0S is electrically connected to the V ss power supply through one and the input / output buffer pads. A second ESD protection element structure, belt, fish ^ the input / output buffer pad and the internal power == the V DD power pin, the structure includes: | 1 & way, the second ESD protection element is an N-type well And the first PM0S forms a parasitic lateral 1 Pnp BJT), and at least one first PM0S is provided in the n-type well, and the drain, the N-type well, and the source of the first PM0s are Pnp double 1. carrier transistor 501263 6. Scope of patent application The drain of the PM0S and the source of the first PM0S are electrically connected to the input / output buffer 塾 and the V⑽ power pin (V DD ρ 〇wertermina 1); at least one first N A diffusion region is provided in the N-type well; at least one dummy gate is provided between the first PMOS and the first N diffusion region; at least a second N diffusion region is provided in the N-type well A well is used to electrically connect the V Dp power pin and at least a second shallow trench isolation (STI) to isolate the first PMOS and the second N diffusion region; a negative substrate driving circuit is electrically connected to the The V DD power pin, the input / output buffer pad, the internal circuit, and the first N diffusion region of the second ESD protection element structure and the negative substrate driving circuit include: a second PM0S, the second PM0S The source of the second PM0S is electrically connected to the input / output buffer pad through an N-well resistance (R_NW), and the drain of the second PM0S is electrically connected to the input / output buffer pad. A third electronic component and a fourth electronic element Respectively buffer the V DD supply pin and input / output pads are electrically connected. 16. The ESD protection circuit according to item 15 of the application scope, wherein when a positive ESD voltage pulse is applied to the input / output buffer pad and V ss is grounded and VD is floating, the positive ESD voltage pulse is transmitted by The second electronic component and the first electronic component apply a coupled voltage to the gate of the second NMOS. Page 38 501263 6. Application for patent scope_ 1 7. As the esd protection circuit of item 6 in the application scope, wherein when the coupling voltage is greater than the starting voltage (vth) of the second NMOS, the second NMOS A part of the current of the positive ESD voltage pulse is turned on and conducted to the P-type well through the first P # hetero region to trigger the parasitic lateral η-p-η double-carrier transistor, so that the ESD voltage is high. The impulsive current can be quickly released to the V s source pin through the P-well below the first NMOS. 18. The esd protection circuit according to item 15 of the application scope, wherein when a negative ESD voltage pulse is applied to the input / output buffer and V ss is grounded and VD is ticked (f 1 0 ating), the negative ESD voltage pulse The current will be released to the Vss power pin 19 through the forward biased jUncti0n formed by the first pole of the NMOS and the P-well. 9 · As the scope of application! The esd protection circuit of 5 items, wherein when a negative ESD voltage pulse is applied to the input / output buffer pad and V DD is grounded and vs is stored (f 1 〇ating), the negative e SD voltage will be provided by the The third electronic component and the fourth electronic component apply a coupled voltage to the gate of the second PMOS. 20. The esd protection circuit according to item 19 of the application scope, wherein when the coupling voltage is less than the starting voltage (vth) of the second PM0S, the second PM0S will be turned on and conduct part of the current of the negative ESD voltage pulse. Is introduced into the N-type well through the first N-doped region to trigger the parasitic lateral p-n_p bipolar transistor 'to allow the current of the negative ESD voltage pulse to pass through the first PMOS 501263 — ^ — η 9011IHL——t-- L-5T ^ W ^ lii The N-type well is quickly released to the V DD power pin. 21 · The ESD protection circuit of item 15 of the application scope, wherein when a positive ESD voltage pulse is applied to the input / output buffer, and V DD is grounded and VS is connected (f 1 oat i ng), the positive ESD voltage The pulsed current will be released to the V dd power pin through the forward biased junction formed by the drain of the first PMOS and the well. 22. The ESD protection circuit according to item 15 of the application, wherein the first electronic component includes a resistor or diodes. 2 3. The ESD protection circuit according to item 15 of the application, wherein the second electronic component includes a resistor, a capacitor, or a zener diode. 2 4. The ESD protection circuit according to item 15 of the application, wherein the third electronic component includes a resistor, a capacitor, or a kina diode. 25. The ESD protection circuit according to item 15 of the application, wherein the fourth electronic component includes a resistor or a diode. 26. If the ESD protection circuit of item 5 of the application scope includes a pre-driver circuit, it is electrically connected to the VDD power pin, the V ss power pin, the internal circuit, and the first n The gate of M 0 S and the gate of the first PMOS. Page 40 2002. 07. 09. 040 501263 6. Application: ^ Scope 2 7. — An ESD protection circuit that is electrically connected to an input / output buffer, an internal circuit, and a V% power supply Pin and a V DD power pin, the ESD protection circuit includes: a first ESD protection element structure, electrically connected to the V ss power pin, the input / output buffer pad and the internal circuit, the first The structure of the ESD protection element includes: a P-well; at least one NMOS, located in the P-well, and the drain of the NMOS, the P-well, and the source of the NMOS forming a parasitic lateral npn double A carrier transistor (parasitic lateral npn BJT), and the non-polar terminal of the NMOS and the green pole of the N M 0 5 are respectively electrically connected to the input / output tb buffer and the V ss power pin; at least one first A P-diffusion region is provided in the P-type well; at least one dummy gate is provided between the N M 0 S and the first P-diffusion region; at least one second P-diffusion region is provided in the P-well. In the P-well, it is used to electrically connect the V ss power pin; And at least one first shallow trench isolation (STI) for isolating the NMOS and the second P diffusion region; a forward substrate bias circuit electrically connected to the Vss power pin and the input / output buffer pad , The internal circuit and the first P diffusion region of the first ESD protection element structure f, the forward base bias circuit includes: a first electronic component electrically connected to the input / output buffer pad, the P.41 501263 I ------------------ I ----------- ~ "« ^ VI. Application for Specialized Scope '-the internal circuit and the first A first p-diffusion region of an ESD protection element structure; and a second electronic component, which is connected to the vs power supply pin and the first p-diffusion region of the first ESD protection element structure; a second ESD protection A component structure electrically connected to the v dd power supply pin, the input / output buffer pad and the internal circuit, the second ESD protection component structure includes: an N-type well; at least one PM0S disposed in the N-type well, The drain of the PM0S, the n-type well, and the source of the PM0S form a parasitic lateral ρ-η-p bipolar transistor (parasitic lateral pnp BJT), and the pole of the PM0S and the source of the PM0S The poles are electrically connected to the input / output buffer pad and the V DD power pin (V DD Ρ 〇wertermina 1); at least the first N diffusion region 'set in the well' and at least one dummy gate (dummy gate) 'is disposed between the P M 0 S and the first N diffusion region; at least one second N diffusion region, In the N-well, it is used to electrically connect the V DD power pin; and at least a second shallow trench isolation (STI) is used to isolate the PMOS from the -N diffusion region, a negative substrate driving circuit, and the electrical connection. In the V DD power pin, the input / output buffer pad, the internal circuit and the first N diffusion region of the second ESD protection element structure, the negative substrate driving circuit includes a third electronic component, Electrically connected to the input / output buffer pad, and the. Page 42 501263 VI. The internal circuit of the top view and the first n diffusion area of the second ESD protection element structure; and a fourth electronic component electrically connected to the V DD power pin and the second ESD The first N diffusion region of the device structure is protected. 28. The ESD protection circuit of item 27 in the application scope, wherein when a positive ESI < voltage pulse is applied to the input / output buffer pad and V ss is connected to ground and VD is connected to _ (f 1 〇ating), the positive The ESD voltage pulse generates a coupled voltage through the second electronic component and the first electronic component and is applied to the P-type well through the first P-doped region to trigger the parasitic lateral η- The p-η double-carrier transistor enables the current of the ESD voltage pulse to be quickly released to the ν s, s power pin through the P-type 下方 below the NMOS. 29. The ESD protection circuit according to item 27 of the application, wherein when a negative ESD voltage pulse is applied to the input / output buffer pad and V ss is grounded and VD floats (float ing), The current will be released to the V ss power pin through the forward biased juncti (n) formed by the pole of the NMOS and the P-well. 30. The ESD protection circuit of item 27 of the application scope, wherein when a negative ESD electric dust pulse is applied to the input / output buffer pad and v dd is grounded and vs is selected (f 1 o ^ t 1 ng), the A negative ESD voltage pulse will be generated by the third electronic component, = the pen component generates a coupled voltage and is applied to the N-type well from the 4th N-th hybrid region to trigger the parasitic cross Page 43 To the ρ-η-P bipolar transistor, the current of the negative ESD voltage pulse can be quickly released to the V⑽ power pin through the N-type well below the PMOS. 31. The ESD protection circuit of item 27 of the application scope, wherein when a positive ESI voltage pulse is applied to the input / output buffer pad and V⑽ is grounded and V s 谇 is floating, the positive ESD voltage pulse The current will be released to the VDD power pin through the forward biased junction formed by the drain of P㈣S and the N-well. 32. The ESD protection circuit according to item 27 of the application, wherein the first electronic component includes a resistor or diodes. 33. The ESD protection circuit of claim 27, wherein the second electronic component includes a resistor, a capacitor, or a zener diode. 34. The ESD protection circuit according to item 27 of the application, wherein the third electronic component includes a resistor, a capacitor, or a kina diode. 35. The ESD protection circuit of claim 27, wherein the fourth electronic component includes a resistor or a diode. 3 6 · If the ESD protection circuit of item 27 of the application scope includes a pre-driver circuit, which is electrically connected to the vD1) power pin, the Vss power pin, the internal circuit, and the nmOS Gate of the PM0S 2002. 07. 09. 044, page 44, 501263 6. Application scope is covered. 3 7. — A kind of power-rail ESD clamp circuits, which are electrically connected to A V ss power pin and a V DD power pin, the power line ESD clamping circuit includes: an ESD protection element structure, the first ESD protection element structure includes: a P-type well; a N M 0 S, Is set in the P-type well, and the drain of the N M 0 S, the P-well and the source of the NMOS forms a parasitic lateral η-ρ-η double carrier transistor (parasitic lateral npn BJT), and The drain of the NMOS and the source of the NMOb are respectively connected to the V DD power pin and the Y SS ^ source pin; a first P diffusion region is set in the P-type well; a dummy A dummy gate is disposed between the NMO S and the first P diffusion region; a second P diffusion region is disposed in the P-type well for electrically connecting the V ss power pin; and a first Shallow trench isolation (STI) for isolating the NMOS and the second P + diffusion region; a substrate bias And is electrically connected to the V ss power pin, the V DD power pin, and the first P diffusion region of the ESD protection element structure. The forward substrate bias circuit includes: a M0S, a source of the M0S. It is via a P-well resistance (R_PW) and Page 45 501263 VI. Apply for the scope of shame The V ss power pin is electrically connected. The drain of the M0S is electrically connected to the V DD power pin. The gate of the M0S is connected through a first electronic component and a first The two electronic components are electrically connected to the V ss power pin and the V DD power pin, respectively. 3 8. The power line ESD clamping circuit of item 37 in the above range, wherein the M0S is an NM0S, and the first electronic component and the second electronic component are a resistor and a capacitor, respectively. 39. The power line ESD clamping circuit according to item 37 of the application, wherein the M0S is a PM0S, and the first electronic component and the second electronic component are a diode and a resistor, respectively. 4 0. A power-rail ESD clamp circuit, which is electrically connected to a V ss power pin and a V DD power pin. The power line ESD clamp circuit includes There are: an ESD protection element structure, the first ESD protection element structure includes: a P-type well; an N M 0 S, which is set in the P-type well, and the drain of the N M 0 S, the P-type well And the source of the NM0S forms a parasitic lateral η-ρ-η double carrier transistor (parasitic lateral npn BJT), and the pole of the NM0S and the source of the NM0S are electrically connected to the V DD power supply respectively. Pin and the V ss power pin; Page 46 501263 VI. A patent claim: a first P diffusion region is provided in the P-type well; a dummy gate is provided between the NMOS and the first P diffusion region; a first Two P diffusion regions are provided in the P-type well for electrically connecting the V ss power pin; and, a first shallow trench isolation (STI) is used to isolate the NMOS and the second P + diffusion region; a substrate The bias circuit is electrically connected to the V ss power pin, the V DD power pin, and the first P diffusion region of the ESD protection element structure. The forward substrate bias circuit includes: a resistor, electrically connected A V-ss power supply pin and the first P diffusion region of the ESD protection element structure; and a kina diode, which is electrically connected to the V DD power supply pin, the resistor, and the first ESD protection element structure The first P diffusion region. Page 47