TWI678042B - 靜電放電保護系統 - Google Patents

靜電放電保護系統 Download PDF

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TWI678042B
TWI678042B TW108109238A TW108109238A TWI678042B TW I678042 B TWI678042 B TW I678042B TW 108109238 A TW108109238 A TW 108109238A TW 108109238 A TW108109238 A TW 108109238A TW I678042 B TWI678042 B TW I678042B
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electrostatic
current
electrostatic discharge
pad
terminal
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TW201944678A (zh
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丁韻仁
Yun-Jen Ting
賴致瑋
Chih-Wei Lai
吳易翰
Yi-han WU
林坤信
Kun-Hsin Lin
許信坤
Hsin-Kun Hsu
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力旺電子股份有限公司
Ememory Technology Inc.
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Abstract

靜電放電保護系統包含焊墊、主靜電放電保護電路及靜電放電截斷電路。焊墊於接觸時傳導靜電電流。主靜電放電保護電路耦接於焊墊，用以將靜電電流之第一部分電流導入共電壓端。靜電放電截斷電路耦接於焊墊與負載電路之間，用以防止靜電電流之第二部分電流進入負載電路。靜電放電截斷電路包含電容及電晶體。電容耦接於焊墊。電晶體耦接於電容。

Description

靜電放電保護系統
本發明描述一種靜電放電保護系統，尤指一種強化靜電放電保護功能的靜電放電保護系統。
靜電放電(Electrostatic Discharge， ESD)為具有不同靜電電位的物體相互靠近或直接接觸引起的電荷轉移之物理現象。不同物質的接觸、相對運動或相互摩擦即可產生靜電。兩個帶有電荷的物體也就成了靜電源。依據電荷中和原理，靜電源與其他物體接觸時，會存在著電荷流動，以傳送足夠的電量以抵消電壓。電荷流動的過程中，將產生潛在的破壞電壓、電流以及電磁場，嚴重時可將脆弱物體或電子元件擊毀，此為靜電放電的特性。
隨著電子設備功能的增加，輸入輸出(I/O)的端點或是連接元件也隨之增多。無論是I/O端點、或是用以接收外部驅動或控制電壓的連接元件，都可視為提供靜電放電之能量進入內部電路的媒介。因此，與靜電放電保護的相關設計變得不容忽視。特別是在濕度較小的環境中，靜電放電的電壓尺度動輒上百甚至上千伏特。如此超高的瞬間電壓可能立刻會將電子設備內的電路擊毀、或是讓電子設備內的電路發生誤動作。因此，現有的電子設備常會包含靜電放電保護元件，目的為避免靜電放電的能量直接破壞其內部的電路。
目前靜電放電保護元件的通用做法為提供一條靜電放電的漏電路徑，以將靜電放電的能量導出電子設備之外，進而避免直接讓電子設備中其他的電路元件直接承受如此高的能量。然而，電子設備中所有的電路元件通常互為直接或是間接的電性連接模式。因此，若靜電放電保護元件僅提供一條靜電放電的漏電路徑，靜電放電的能量仍可透過漏電路徑之外的其他路徑流竄。換句話說，電子設備中其他的電路元件仍會被一部分靜電放電的能量影響。對於較為精密或是能量耐受力較低的電路元件(例如鰭式場效電晶體，Fin Field-effect Transistor)，一部分靜電放電的能量就足以造成永久性的損壞。因此，發展一種保護能力更強的靜電放電保護系統實為必然趨勢。
本發明一實施例提出一種靜電放電保護系統，包含第一焊墊、第一主靜電放電保護電路及第一靜電放電截斷電路。第一焊墊於接觸時傳導第一靜電電流。第一主靜電放電保護電路耦接於第一焊墊，用以將第一靜電電流之第一部分電流導入共電壓端。第一靜電放電截斷電路耦接於第一焊墊與負載電路之間。第一靜電放電截斷電路包含第一電容及第一電晶體。第一電容包含耦接於第一焊墊的第一端、以及第二端。第一電晶體包含耦接於第一電容之第一端的第一端、耦接於第一電容之第二端的控制端、以及第二端。第一電容經第一靜電電流之第二部分電流充電後，使得第一電晶體進入截止狀態，藉以防止第一靜電電流之第二部分電流傳送至負載電路。
第1圖係為本發明之靜電放電保護系統100之實施例的電路圖。靜電放電保護系統100可應用於任何具有不同靜電電位的電路中，以防止靜電放電(Electrostatic Discharge， ESD)的能量將電路損壞。靜電放電保護系統100包含第一焊墊PAD1、第一主靜電放電保護電路MESD1及第一靜電放電截斷電路ESDH1。第一焊墊PAD1可為任何種類的接觸型導體，例如類比輸入輸出板(I/O Pad)或編程電源板(VPP Pad)。因此，當第一焊墊PAD1被有靜電能量的物體接觸時，會傳導其靜電能量而使第一焊墊PAD1的電壓升高至第一靜電電壓V ESD1。第一靜電電壓V ESD1的尺度約為數百至數千伏特，例如+2000伏特的靜電電壓。當第一焊墊PAD1的電壓升高至第一靜電電壓V ESD1後，即產生第一靜電電流。第一主靜電放電保護電路MESD1耦接於第一焊墊PAD1，用以將第一靜電電流之第一部分電流導入共電壓端。第一主靜電放電保護電路MESD1可包含複數個二極體串(Diode String)。第一主靜電放電保護電路MESD1也可由雙載子(Bipolar)電晶體、金屬氧化物半導體元件及矽控制整流器(Silicon-Controlled Rectifier，SCR)等元件組成。共電壓端具有共電壓V SS。在第一焊墊PAD1的電壓升高至第一靜電電壓V ESD1後，共電壓V SS小於第一靜電電壓V ESD1。因此第一靜電電流之第一部分電流的電流方向為由第一焊墊PAD1，透過第一主靜電放電保護電路MESD1而流入共電壓端。第一靜電放電截斷電路(ESD Inhibit Circuit)ESDH1耦接於第一焊墊PAD1，用以將第一靜電電流之第二部分電流截斷。第一靜電放電截斷電路ESDH1包含第一電容C1以及第一電晶體T1。第一電容C1包含耦接於第一電源板PAD1端的第一端、以及第二端。第一電容C1的電容值後文稱為第一電容值，其範圍可為10~50微微(pico，10 -12)法拉(farad)之間。第一電晶體T1包含耦接於第一電容C1之第一端的第一端、耦接於第一電容C1之第二端的控制端、以及第二端。在靜電放電保護系統100中，靜電放電保護的對象可為負載電路L。負載電路L可耦接於第一電晶體T1之第二端及共電壓端。第一靜電電流之第二部分電流可視為靜電放電之漏電流。並且，第一靜電放電截斷電路ESDH1可將第一靜電電流之第二部分電流在短時間內快速地降低，以使第二部分電流趨近於零。因此，負載電路L幾乎不會受到靜電放電之漏電流的影響。
在靜電放電保護系統100中，第一電晶體T1可為P型金屬氧化物半導體場效電晶體(P-Type Metal-Oxide-Semiconductor)，具有通導閘極電晶體(Passing Gate Transistor)的功能。第一電晶體T1之控制端與共電壓端間產生第一寄生電容CP1，且第一寄生電容CP1的第一寄生電容值小於第一電容C1的第一電容值。第一寄生電容CP1可產生在負載電路L的內部。舉例而言，如上述提及，第一電容值之範圍可為10~50微微法拉之間。第一寄生電容值約為2微微法拉。負載電路L的定義可為任何的受電元件，例如具有讀取、寫入與抹除能力的記憶單元(Memory Cell)、或是以鰭式場效電晶體(Fin Field-effect Transistor，FinFET)組成的邏輯電路。本發明的靜電放電保護系統100可有效避免記憶單元發生誤動作，或是鰭式場效電晶體之邏輯電路受到靜電放電之高能量影響而發生氧化層損壞的情況。以下將描述靜電放電保護系統100的運作原理。
第2圖係為靜電放電保護系統100中，產生第一靜電電流F1時，各元件狀態以及電流方向的示意圖。如前述提及，當第一焊墊PAD1被有靜電能量的物體接觸時，會傳導其靜電能量而使第一焊墊PAD1的電壓升高至第一靜電電壓V ESD1，進而產生第一靜電電流F1。第一靜電電流F1的第一部分電流F2會經由第一主靜電放電保護電路MESD1被導入共電壓端。因此，第一靜電電流F1的第一部分電流F2可視為對負載電路L沒有影響的電流。然而，依據克希荷夫電流定律(Kirchhoff’s Current Law)，第一靜電電流F1的第二部分電流F3會存在，且符合F1=F2+F3的關係。在一般情況下，第一靜電電流F1之第一部分電流F2幾乎等於第一靜電電流F1，亦即第一靜電電流F1之第一部分電流F2會遠大於第一靜電電流F1之第二部分電流F3。然而，若是第一主靜電放電保護電路MESD1的反應速度較慢，第一靜電電流F1的第二部分電流F3會升高。若是沒有引入第一靜電放電截斷電路ESDH1，第一靜電電流F1的第二部分電流F3將會造成負載電路L誤動作或是損壞。因此，在靜電放電保護系統100中，第一靜電放電截斷電路ESDH1的功能為阻隔第一靜電電流F1的第二部分電流F3輸入至負載電路L中，說明如下。當第一焊墊PAD1的電壓升高至第一靜電電壓V ESD1時，第一電容C1可透過第一靜電電流F1之第二部分電流F3充電。在第一電容C1透過第一靜電電流F1之第二部分電流F3充電一段時間後(非常短的時間，例如數十至數百個奈秒(nanosecond))，第一電容C1的第二端會符合分壓定律。換句話說，節點A的電壓會由低轉為高。節點A之電壓與第一靜電電壓V ESD1之電壓差的絕對值若小於第一電晶體T1的第一門檻電壓之絕對值，則第一電晶體T1將變為截止狀態。換句話說，節點A與第一靜電電壓V ESD1之電壓差的絕對值可視為第一電晶體T1之閘極與源極之跨壓(V GS1)的絕對值。當V GS1的絕對值小於第一電晶體T1的第一門檻電壓(V TH1)之絕對值時，即|V GS1|＜|V TH1|，則第一電晶體T1將變為截止狀態(Cutoff)。截止狀態的第一電晶體T1可截斷第一靜電電流F1之第二部分電流F3傳送至負載電路L。具體而言，第一電晶體T1的第一門檻電壓V TH1、共電壓端的共電壓V SS、第一焊墊PAD1的第一靜電電壓V ESD1、第一寄生電容CP1的第一寄生電容值α CP1、及第一電容C1的第一電容值α C1符合以下關係：
換言之，第一電晶體T1的第一門檻電壓V TH1可經由上述公式適當地設計，以使第一焊墊PAD1的電壓升高至第一靜電電壓V ESD1時，可以“關閉”第一電晶體T1而使之成為截止狀態。因此，由於第一電晶體T1變為截止狀態，流到負載電路L的電流也會在短時間內快速地降低，以避免負載電路L的電路受到損壞。在實際情況中，第一靜電放電截斷電路ESDH1將第二部分電流F3在短時間內快速地降低後，由第一靜電放電截斷電路ESDH1所輸出的電流F4會趨近於零。因此，負載電路L幾乎不會受到靜電放電之電壓波動的影響。並且，設計者可以依據負載電路L之電路的能量耐受力，選擇合適的第一電晶體T1。例如，當負載電路L包含能量耐受力較低的鰭式場效電晶體(FinFET)時，設計者可以選擇閘極氧化層較薄的電晶體為第一電晶體T1，以加快第一電晶體T1的截止速度。任何合理的技術變更或是元件置換都屬於本發明所揭露的範疇。
因此，在靜電放電保護系統100中，即使第一焊墊PAD1產生第一靜電電流F1，第一靜電電流F1的所有傳導路徑會與負載電路L隔離。換句話說，第一靜電電流F1之第一部分電流F2會被導入共電壓端，而第一靜電電流F1之第二部分電流F3會被第一電晶體T1截斷其傳輸。因此，對於負載電路L而言，僅會在極短的時間內接收到微量之靜電放電電流。因此，靜電放電保護系統100可以有效地提供負載電路L完整的靜電放電保護功能。
第3圖係為本發明之靜電放電保護系統200之另一實施例的電路圖。靜電放電保護系統200之部分元件相同於靜電放電保護系統100，但提供了雙向的靜電放電保護功能。在靜電放電保護系統200中，第一焊墊PAD1、第一主靜電放電保護電路MESD1、第一靜電放電截斷電路ESDH1及負載電路L的元件將同於靜電放電保護系統100，因此元件代號將沿用靜電放電保護系統100的元件代號，且上述之重複元件的功能將不再贅述。靜電放電保護系統200除了上述元件外，還包含第二焊墊PAD2、第二主靜電放電保護電路MESD2以及第二靜電放電截斷電路ESDH2。第二焊墊PAD2可為任何種類的接觸型導體，例如類比輸入輸出板或編程電源板。因此，當第二焊墊PAD2被有靜電能量的物體接觸時，會傳導其靜電能量而使第二焊墊PAD2的電壓升高至第二靜電電壓V ESD2。第二靜電電壓V ESD2的尺度約為數百至數千伏特。當第二焊墊PAD2的電壓升高至第二靜電電壓V ESD2後，即產生第二靜電電流。第二主靜電放電保護電路MESD2耦接於第二焊墊PAD2，用以將第二靜電電流之第一部分電流導入共電壓端。第二主靜電放電保護電路MESD2可包含複數個二極體串。第二主靜電放電保護電路MESD2也可由雙載子電晶體、金屬氧化物半導體元件及矽控制整流器等元件組成。第二主靜電放電保護電路MESD2可利用上述元件之一次崩潰區來導出第二靜電電流之第一部分電流。共電壓端具有共電壓V SS。在第二焊墊PAD2的電壓升高至第二靜電電壓V ESD2後，共電壓V SS小於第二靜電電壓V ESD2。因此第二靜電電流之第一部分電流的電流方向為由第二焊墊PAD2，透過第二主靜電放電保護電路MESD2而流入共電壓端。換句話說，第一靜電電流與第二靜電電流互為反向。第二靜電放電截斷電路ESDH2耦接於第二焊墊PAD2，用以將第二靜電電流之第二部分電流截斷。第二靜電放電截斷電路ESDH2包含第二電容C2以及第二電晶體T2。第二電容C2包含耦接於第二電源板PAD2端的第一端、以及第二端。第二電容C2的電容值後文稱為第二電容值，其範圍可為10~50微微法拉之間。第二電晶體T2包含耦接於第二電容C2之第一端的第一端、耦接於第二電容C2之第二端的控制端、以及第二端。負載電路L可耦接於第二電晶體T2之第二端及共電壓端。第二靜電電流之第二部分電流可視為靜電放電之漏電流。並且，第二靜電放電截斷電路ESDH2可將第二靜電電流之第二部分電流在短時間內快速地降低，以使第二部分電流趨近於零。因此，負載電路L幾乎不會受到靜電放電之漏電流的影響。
在靜電放電保護系統200中，第二電晶體T2可為P型金屬氧化物半導體場效電晶體，具有通導閘極電晶體的功能。第二電晶體T2之控制端與共電壓端間產生第二寄生電容CP2，且第二寄生電容CP2的第二寄生電容值小於第二電容C2的第二電容值。第二寄生電容CP2可產生在負載電路L的內部。舉例而言，如上述提及，第二電容值之範圍可為10~50微微法拉之間。第二寄生電容值約為2微微法拉。以下將描述靜電放電保護系統200的運作原理。
第4圖係為靜電放電保護系統200中，產生第二靜電電流F5時，各元件狀態以及電流方向的示意圖。應當理解的是，在靜電放電保護系統200中，第一焊墊PAD1、第一主靜電放電保護電路MESD1以及第一靜電放電截斷電路ESDH1所組成的電路，用於保護負載電路L的原理同於前述之靜電放電保護系統100。因此，第一靜電電流F1與其分路的電流F2至F3被導出、截斷、阻隔的方式也相同於前述之靜電放電保護系統100，故於此將不再贅述。類似地，與第一靜電電流F1反向的第二靜電電流F5的運作方式也類似於靜電放電保護系統100之運作方式。然而，為了描述之明確性，於此將說明第二靜電電流F5的處理方式。第二靜電電流F5的第一部分電流F6會經由第二主靜電放電保護電路MESD2被導入共電壓端。因此，第二靜電電流F5的第一部分電流F6可視為對負載電路L沒有影響的電流。然而，依據克希荷夫電流定律，第二靜電電流F5的第二部分電流F7會存在，且符合F5=F6+F7的關係。在一般情況下，第二靜電電流F5之第一部分電流F6會遠大於第二靜電電流F5之第二部分電流F7。然而，若是第二主靜電放電保護電路MESD2的反應速度較慢，第二靜電電流F5的第二部分電流F7會升高。若是沒有引入第二靜電放電截斷電路ESDH2，第二靜電電流F5的第二部分電流F7將會造成負載電路L誤動作或是損壞。因此，在靜電放電保護系統200中，第二靜電放電截斷電路ESDH2的功能為截斷甚至阻隔第二靜電電流F5的第二部分電流F7輸入至負載電路L中，說明如下。當第二焊墊PAD2的電壓升高至第二靜電電壓V ESD2時，第二電容C2可透過第二靜電電流F5之第二部分電流F7充電。在第二電容C2透過第二靜電電流F5之第二部分電流F7充電一段時間後(非常短的時間，例如數十至數百個奈秒)，第二電容C2的第二端會符合分壓定律。換句話說，節點B的電壓會由低轉為高。節點B之電壓與第二靜電電壓V ESD2之電壓差的絕對值若小於第二電晶體T2的第二門檻電壓之絕對值，則第二電晶體T2將變為截止狀態。換句話說，節點B與第二靜電電壓V ESD2之電壓差的絕對值可視為第二電晶體T2之閘極與源極之跨壓(V GS2)的絕對值。當V GS2的絕對值小於第二電晶體T2的第二門檻電壓(V TH2)之絕對值時，即|V GS2|＜|V TH2|，則第二電晶體T2將變為截止狀態(Cutoff)。截止狀態的第二電晶體T2可截斷第二靜電電流F5之第二部分電流F7傳送至負載電路L。具體而言，第二電晶體T2的第二門檻電壓V TH2、共電壓端的共電壓V SS、第二焊墊PAD2的第二靜電電壓V ESD2、第二寄生電容CP2的第二寄生電容值α CP2、及第二電容C2的第二電容值α C2符合以下關係：
換言之，第二電晶體T2的第二門檻電壓V TH2可經由上述公式適當地設計，以使第二焊墊PAD2的電壓升高至第二靜電電壓V ESD2時，可以“關閉”第二電晶體T2而使之成為截止狀態。因此，由於第二電晶體T2變為截止狀態，流到負載電路L的電流F8也會在短時間內快速地降低，以避免負載電路L的電路受到損壞。在實際情況中，第二靜電放電截斷電路ESDH2將第二部分電流F7在短時間內快速地降低後，由第二靜電放電截斷電路ESDH2所輸出的電流F8會趨近於零。因此，負載電路L幾乎不會受到靜電放電之電壓波動的影響。並且，設計者可以依據負載電路L之電路的能量耐受力，選擇合適的第二電晶體T2。例如，當負載電路L包含能量耐受力較低的鰭式場效電晶體(FinFET)時，設計者可以選擇閘極氧化層較薄的電晶體為第二電晶體T2，以加快第二電晶體T2的截止速度。任何合理的技術變更或是元件置換都屬於本發明所揭露的範疇。
因此，在靜電放電保護系統200中，即使第二焊墊PAD2產生第二靜電電流F5，第二靜電電流F5的所有傳導路徑會與負載電路L隔離。意即，第二靜電電流F5之第一部分電流F6會被導入共電壓端，而第二靜電電流F5之第二部分電流F7會被第二電晶體T2截斷其傳輸。因此，對於負載電路L而言，僅會在極短的時間內接收到微量之靜電放電電流。換句話說，在靜電放電保護系統200中，無論是第一焊墊PAD1或是第二焊墊PAD1所產生的靜電電流，都能有效地截斷以及阻隔，以防止負載電路L受到損壞。因此，靜電放電保護系統200可以有效地提供負載電路L完整且雙向的靜電放電保護功能。
綜上所述，本發明揭露了一種靜電放電保護系統，具有單向甚至雙向的靜電放電保護功能。靜電放電保護系統除了利用主靜電放電保護電路將大部分的靜電能量導出之外，還引入了靜電放電截斷電路以使剩餘的靜電能量被阻隔。此外，靜電放電截斷電路的電晶體以及電容之規格也可以依據負載電路的需求而設計。因此，本發明之靜電放電保護系統可以有效地提供負載電路完整的靜電放電保護功能，且也具備設計彈性。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100及200 靜電放電保護系統
PAD1 第一焊墊
MESD1 第一主靜電放電保護電路
ESDH1 第一靜電放電截斷電路
L 負載電路
C1 第一電容
T1 第一電晶體
CP1 第一寄生電容
A 節點
V SS 共電壓
V ESD1 第一靜電電壓
F1至F8 電流
PAD2 第二焊墊
MESD2 第二主靜電放電保護電路
ESDH2 第二靜電放電截斷電路
C2 第二電容
T2 第二電晶體
CP2 第二寄生電容
B 節點
V ESD2 第二靜電電壓
第1圖係為本發明之靜電放電保護系統之實施例的電路圖。
第2圖係為第1圖之靜電放電保護系統中，產生第一靜電電流時，各元件狀態以及電流方向的示意圖。
第3圖係為本發明之靜電放電保護系統之另一實施例的電路圖。
第4圖係為第3圖之靜電放電保護系統中，產生第二靜電電流時，各元件狀態以及電流方向的示意圖。

Claims (13)

  1. 一種靜電放電保護系統，包含：
    一第一焊墊，於靜電放電(electrostatic discharge)發生時傳導一第一靜電電流；
    一第一主靜電放電保護電路，耦接於該第一焊墊，用以將該第一靜電電流之一第一部分電流導入一共電壓端；及
    一第一靜電放電截斷電路，耦接於該第一焊墊及一負載電路之間，該第一靜電放電截斷電路包含：
    一第一電容，包含：
    一第一端，耦接於該第一焊墊；及
    一第二端；及
    一第一電晶體，包含：
    一第一端，耦接於該第一電容之該第一端；
    一控制端，耦接於該第一電容之該第二端；及
    一第二端；
    其中該第一電容經該第一靜電電流之一第二部分電流充電後，使得該第一電晶體進入一截止狀態，藉以防止該第一靜電電流之該第二部分電流傳送至該負載電路。
  2. 如請求項1所述之系統，其中該第一電晶體係為一P型金屬氧化物半導體場效電晶體(P-Type Metal-Oxide-Semiconductor)，且該第一主靜電放電保護電路包含複數個二極體串(Diode String)。
  3. 如請求項1所述之系統，其中該第一靜電電流之該第一部分電流大於該第一靜電電流之該第二部分電流。
  4. 如請求項1所述之系統，其中在該第一電晶體之該控制端與該共電壓端間產生一第一寄生電容，且該第一寄生電容的一第一寄生電容值小於該第一電容的一第一電容值。
  5. 如請求項4所述之系統，其中該第一電晶體的一第一門檻電壓、該共電壓端的一共電壓、該第一焊墊的一第一靜電電壓、該第一寄生電容的該第一寄生電容值、及該第一電容的該第一電容值符合以下關係：
    Figure TWI678042B_C0001

    其中V TH1係為該第一門檻電壓、α C1係為該第一電容值、α CP1係為該第一寄生電容值、V ESD1係為該第一靜電電壓且V SS係為該共電壓。
  6. 如請求項5所述之系統，其中該第一電容值在10~50微微(pico，10 -12)法拉(farad)之間，且該第一寄生電容值約為2微微法拉。
  7. 如請求項1所述之系統，另包含：
    一第二焊墊，於靜電放電(electrostatic discharge)發生時傳導一第二靜電電流；
    一第二主靜電放電保護電路，耦接於該第二焊墊，用以將該第二靜電電流之一第一部分電流導入該共電壓端；及
    一第二靜電放電截斷電路，耦接於該第二焊墊與該負載電路之間，該第二靜電放電截斷電路包含：
    一第二電容，包含：
    一第一端，耦接於該第二焊墊；及
    一第二端；及
    一第二電晶體，包含：
    一第一端，耦接於該第二電容之該第一端；
    一控制端，耦接於該第二電容之該第二端；及
    一第二端；其中該第二電容經該第二靜電電流之一第二部分電流充電後，使得該第二電晶體進入一截止狀態，藉以截斷該第二靜電電流之該第二部分電流傳送至該負載電路。
  8. 如請求項7所述之系統，其中該第二電晶體係為一P型金屬氧化物半導體場效電晶體(P-Type Metal-Oxide-Semiconductor)，且該第二主靜電放電保護電路包含複數個二極體串(Diode String)。
  9. 如請求項7所述之系統，其中該第二靜電電流之該第一部分電流大於該第二靜電電流之該第二部分電流。
  10. 如請求項7所述之系統，其中在該第二電晶體之該控制端與該共電壓端間產生一第二寄生電容，且該第二寄生電容的一第二寄生電容值小於該第二電容的一第二電容值。
  11. 如請求項10所述之系統，其中該第二電晶體的一第二門檻電壓、該共電壓端的一共電壓、該第二焊墊的一第二靜電電壓、該第二寄生電容的該第二寄生電容值、及該第二電容的該第二電容值符合以下關係：
    Figure TWI678042B_C0002

    其中V TH2係為該第二門檻電壓、α C2係為該第二電容值、α CP2係為該第二寄生電容值、V ESD2係為該第二靜電電壓且V SS係為該共電壓。
  12. 如請求項11所述之系統，其中該第二電容值在10~50微微(pico，10 -12)法拉(farad)之間，且該第二寄生電容值約為2微微法拉。
  13. 如請求項7所述之系統，其中該第一靜電電流與該第二靜電電流互為反向，該第一焊墊或該第二焊墊係為一類比輸入輸出板(I/O Pad)或一編程電源板(VPP Pad)。
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