TW201515187A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW201515187A
TW201515187A TW103121357A TW103121357A TW201515187A TW 201515187 A TW201515187 A TW 201515187A TW 103121357 A TW103121357 A TW 103121357A TW 103121357 A TW103121357 A TW 103121357A TW 201515187 A TW201515187 A TW 201515187A
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Taiwan
Prior art keywords
semiconductor wafer
semiconductor
bump
main surface
wafer
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Application number
TW103121357A
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English (en)
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TWI636545B (zh
Inventor
Daisuke Tsuji
Original Assignee
Ps4 Luxco Sarl
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Publication of TW201515187A publication Critical patent/TW201515187A/zh
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Publication of TWI636545B publication Critical patent/TWI636545B/zh

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    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Abstract

本發明之半導體裝置，係將分別具備有複數之凸塊電極的複數之半導體晶片作層積，前述複數之半導體晶片，係具備有被形成於各別之側面處的辨識部，在前述半導體晶片之各者處，前述複數之凸塊電極係被同樣地作配置，前述辨識部，係以使其與前述複數之凸塊電極中的被設置在既定之場所處之作為基準的凸塊電極之間的位置關係會成為相等的方式來形成，前述複數之半導體晶片，係將被設置於各半導體晶片處之凸塊電極以半導體晶片之層積順序來作電性連接，並且以使被形成有前述辨識部之側面會朝向相同方向的方式而被層積。

Description

半導體裝置
本發明，係有關於半導體裝置。
近年來，伴隨著電子機器之小型化和高功能化，係對於半導體晶片之高密度安裝有所要求。針對此種要求，係對於積載有具備貫通電極之複數之半導體晶片的CoC(Chip on Chip)型之半導體裝置有所檢討。
在專利文獻1(日本特開2010-251347號公報)中，係揭示有一種技術，其係將具備有被與貫通電極作連接並且從基板面而突出了的凸塊電極之複數之半導體晶片，以使上下之半導體晶片之凸塊電極會被作連接的方式來進行積載(反晶層積)，並在半導體晶片間填充身為密封樹脂之底部填充材，而形成晶片層積體，之後，將晶片層積體固定在配線基板上。
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開2010-251347號公報
通常，凸塊電極，其直徑係為20μm程度而為微小，並以40μm程度之窄節距而被形成。因此，在將複數之半導體晶片進行反晶安裝時，依存於安裝精確度，會有在各個半導體晶片之相對應的凸塊電極間而發生位置偏差的情形。
於此，凸塊電極，由於係被形成於半導體晶片之中央區域處，因此要對於作了層積的半導體晶片之凸塊電極間的位置偏差之發生及其程度作檢測一事，係為困難。
另外，在對於被形成有複數之半導體晶片之半導體晶圓進行切割並將各半導體晶片個片化時，依存於切割之精確度，會有在每一半導體晶片處之從半導體晶片之端部起直到凸塊電極為止的距離變得互為相異之情形。因此，要基於作了層積的半導體晶片之各別的端部之位置來檢測出凸塊電極間之位置偏差的發生及其程度一事，亦為困難。
本發明之其中一種形態之半導體裝置，係將分別具備有複數之凸塊電極的複數之半導體晶片作層積， 前述複數之半導體晶片，係具備有被形成於各別之側面處的辨識部，在前述半導體晶片之各者處，前述複數之凸塊電極係被同樣地作配置，前述辨識部，係以使其與前述複數之凸塊電極中的被設置在既定之場所處之作為基準的凸塊電極之間的位置關係會成為相等的方式來形成，前述複數之半導體晶片，係將被設置於各半導體晶片處之凸塊電極以半導體晶片之層積順序來作電性連接，並且以使被形成有前述辨識部之側面會朝向相同方向的方式而被做層積。
本發明之其他形態之半導體裝置，係具備有：第1半導體晶片，係具備第1主面、和與前述第1主面相對向之第2主面、和連結前述第1主面和前述第2主面之第1側面、和被形成於前述第1主面上之第1凸塊電極、和對應於前述第1凸塊電極而被形成於前述第1側面上之第1辨識部；和第2半導體晶片，係具備第3主面、和與前述第3主面相對向之第4主面、和連結前述第3主面和前述第4主面之第2側面、和對應於前述第1凸塊電極而被形成於第3主面上之第2凸塊電極、和與前述第2凸塊電極作電性連接並被形成於前述第4主面上之第3凸塊電極、和相對於前述第2凸塊電極，來以與前述第1凸塊電極和前述第1辨識部間之位置關係相同的位置關係而形成於前述第2側面上之第2辨識部，並使前述第2凸塊電極與前述第1凸塊電極作連接，且以使前述第1側面和前述第2側面朝向相同方向的方式來層積於前述第1半導體晶 片上。
若依據本發明，則能夠容易地對於作了層積的半導體晶片之凸塊電極間的位置偏差之發生及其程度進行檢測。
1‧‧‧半導體裝置
10‧‧‧晶片層積體
11‧‧‧樹脂構件
20‧‧‧配線基板
21‧‧‧絕緣膜
22‧‧‧連接墊片
23‧‧‧焊錫球
24‧‧‧焊墊
25‧‧‧絕緣基材
26‧‧‧螺樁凸塊
27‧‧‧樹脂構件
28‧‧‧密封樹脂
30‧‧‧半導體晶圓
30A‧‧‧半導體晶圓
31‧‧‧切割區域
31A‧‧‧切割線
40‧‧‧接合平台
41‧‧‧第1吸附孔
42‧‧‧接合工具
43‧‧‧第2吸附孔
50‧‧‧塗布平台
51‧‧‧塗布用薄片
52‧‧‧分配器
53‧‧‧底部填充材
60‧‧‧製品形成部
61‧‧‧切割線
100‧‧‧半導體晶片
100A‧‧‧半導體晶片
100B‧‧‧半導體晶片
100C‧‧‧記憶體晶片
100D‧‧‧介面晶片
100a‧‧‧半導體晶片
100b‧‧‧半導體晶片
101‧‧‧電路形成層
102‧‧‧凸塊電極
102a‧‧‧表面凸塊電極
102b‧‧‧背面凸塊電極
103‧‧‧貫通電極
104‧‧‧辨識部
104A‧‧‧辨識部
104B‧‧‧辨識部
105‧‧‧矽基板
105a‧‧‧表面
105b‧‧‧背面
106‧‧‧電極墊片
107‧‧‧絕緣膜
108‧‧‧凸塊(表面凸塊)
109‧‧‧Ni電鍍層
110‧‧‧Au電鍍層
111‧‧‧種晶層
112‧‧‧絕緣環
113‧‧‧凸塊(背面凸塊)
114‧‧‧背面焊錫層
[圖1]對於本發明之第1實施形態的半導體裝置之概略構成的其中一例作展示之剖面圖。
[圖2]係為被形成有圖1中所示之半導體晶片的半導體晶圓之平面圖。
[圖3]圖2中所示之A-A’間的剖面圖。
[圖4A]圖1中所示之半導體晶片的平面圖以及側面圖。
[圖4B]圖4A中所示之B-B’間的剖面圖。
[圖5A]對於圖1中所示之半導體晶片的層積工程作展示之剖面圖。
[圖5B]對於圖1中所示之半導體晶片的層積工程作展示之剖面圖。
[圖5C]對於圖1中所示之半導體晶片的層積工程作展示之剖面圖。
[圖5D]對於圖1中所示之半導體晶片的層積工程作展 示之剖面圖。
[圖6A]圖5D中所示之作了層積的半導體晶片之上面圖以及側面圖。
[圖6B]圖5D中所示之作了層積的半導體晶片之側面圖。
[圖6C]圖5D中所示之作了層積的半導體晶片之側面圖。
[圖7A]圖5D中所示之作了層積的半導體晶片之側面圖。
[圖7B]圖5D中所示之作了層積的半導體晶片之側面圖。
[圖8A]對於圖1中所示之晶片層積體的樹脂構件之填充工程作展示之剖面圖。
[圖8B]對於圖1中所示之晶片層積體的樹脂構件之填充工程作展示之剖面圖。
[圖8C]對於圖1中所示之晶片層積體的樹脂構件之填充工程作展示之剖面圖。
[圖8D]對於圖1中所示之晶片層積體的樹脂構件之填充工程作展示之剖面圖。
[圖9A]對於圖1中所示之半導體裝置的組裝工程作展示之剖面圖。
[圖9B]對於圖1中所示之半導體裝置的組裝工程作展示之剖面圖。
[圖9C]對於圖1中所示之半導體裝置的組裝工程作展 示之剖面圖。
[圖9D]對於圖1中所示之半導體裝置的組裝工程作展示之剖面圖。
[圖9E]對於圖1中所示之半導體裝置的組裝工程作展示之剖面圖。
[圖10]係為被形成有本發明之第2實施形態之半導體晶片的半導體晶圓之平面圖。
[圖11A]圖10中所示之半導體晶片的上面圖以及側面圖。
[圖11B]圖11A中所示之C-C’間的剖面圖。
[圖12A]本發明之第3實施形態之半導體晶片的上面圖以及側面圖。
[圖12B]圖12A中所示之D-D’間的剖面圖。
[圖13]對於本發明之半導體裝置的概略構成之另外一例作展示之圖。
以下，參考圖面，針對用以實施本發明之形態作說明。
(第1實施形態)
圖1，係為對於本發明之第1實施形態的半導體裝置1之概略構成作展示的剖面圖。本發明之半導體裝置，係為在配線基板上被安裝有半導體晶片之層積體(晶片層積 體)的所謂CoC型之半導體裝置。以下，在各圖中，針對相同之構成，係附加相同之元件符號，並省略其說明。
圖1中所示之半導體裝置1，係為將層積有複數之半導體晶片100的晶片層積體10與配線基板20作了連接的構成。晶片層積體10，例如，係為將被形成有記憶體之4個的記憶體晶片作了層積的構成。
半導體晶片100，係在被形成有電路形成層101之面(表面)以及與表面相對向之面(背面)處，分別被形成有複數之凸塊電極102。以下，係有將被形成於表面上之凸塊電極102稱作表面凸塊電極102a，並將被形成於背面上之凸塊電極102稱作背面凸塊電極102b的情形。半導體晶片100之表面凸塊電極102a和背面凸塊電極102b，係藉由貫通電極103而被作連接。各半導體晶片100，係在使表面與其他之半導體晶片100之背面相對向的狀態下，以使表面凸塊電極102a和其他之半導體晶片100之背面凸塊電極102b作電性連接的方式來作層積。藉由此，各半導體晶片100，係經由凸塊電極102來藉由各個的貫通電極103而相互作連接。
又，半導體晶片100，係以會使至少一部分從連結表面和背面之側面而露出的方式，來形成有辨識部104。辨識部104，係藉由將絕緣構件埋入至被設置在半導體晶片100之基板上之溝中，而形成之。各半導體晶片100，係以使被形成有辨識部104之側面會朝向相同之方向的方式而被作層積。
另外，距離配線基板20最遠之半導體晶片100，係並未具備有背面凸塊電極102b以及貫通電極103。以下，係會有將構成晶片層積體10之半導體晶片100中的於兩面上均具備有凸塊電極102之半導體晶片100稱作半導體晶片100a，並將僅在表面上具備有凸塊電極之半導體晶片100稱作半導體晶片100b的情況。半導體晶片100b，由於係並不具備有貫通電極103，因此，相較於半導體晶片100a，晶片厚度係為厚。
晶片層積體10，係具備有將各半導體晶片100間之空隙作填埋並且從側面所觀察時之剖面會成為略梯形狀之樹脂構件11。樹脂構件11，例如係使用底部填充材而形成。
在被配置於略梯形狀之樹脂構件11的短邊(上底)側之半導體晶片100處，係連接固定有被形成有既定之配線的配線基板20。在配線基板20處，例如係使用於兩面上被形成有既定之配線的玻璃環氧基板。各配線，除了後述之連接墊片和焊墊以外，係藉由抗蝕阻膜等之絕緣膜21而被作覆蓋。
在配線基板20之其中一面上，係被形成有用以與晶片層積體10作連接之複數的連接墊片22，在另外一面上，係被形成有用以與成為外部電極之焊錫球23作連接的複數之焊墊24。連接墊片22和焊墊24，係藉由被形成於絕緣基材25中之配線而被作連接。焊墊24，係在配線基板20之另外一面上，以既定之間隔而例如形成為 格子狀。
在連接墊片22之晶片層積體10側之面上，係被形成有例如由Au或Cu等所構成之螺樁凸塊26。螺樁凸塊26，係被與半導體晶片100之凸塊電極102作連接。晶片層積體10和配線基板20，係藉由NCP(Non Conductive Paste)等之樹脂構件27而被作接著固定。藉由樹脂構件27，螺樁凸塊26和凸塊電極102之間的連接部位係被保護。
配線基板20上之晶片層積體10，係藉由密封樹脂28而被密封。在並未被搭載有晶片層積體10之配線基板20之另外一面的複數之焊墊24處，係被連接有焊錫球23。
接著，針對半導體晶片100(於兩面上具備有凸塊電極102之半導體晶片100a)的構成作說明。
圖2，係為被形成有半導體晶片100之半導體晶圓30的上面圖。
在半導體晶圓30上，係被形成有藉由切割區域31所區劃出之複數的半導體晶片100。藉由沿著切割區域31來切割半導體晶圓30，各半導體晶片100係被個片化。
在各半導體晶片100處，係於既定之方向上而被配置有複數之以既定之節距間隔所形成的凸塊電極102之列。以下，係將凸塊電極102之列方向稱作Y方向，並將與Y方向相正交而被配置有凸塊電極102之列的 方向稱作X方向。
又，在各半導體晶片100處，係以會使其與複數之凸塊電極102中之與被設置在特定之場所處的作為基準之凸塊電極102之間的位置關係成為相等的方式，而被形成有辨識部104。在本實施形態中，作為辨識部104，係以使由雙重之絕緣環所成的構造體橫跨藉由切割區域所區劃出之相鄰接之2個的半導體晶片100的方式來構成之。另外，辨識部104，係僅需要形成於半導體晶片100之相正交之2邊處即可。但是，如同上述一般，由於辨識部104係以橫跨相鄰接之2個的半導體晶片100的方式而被形成，因此，若是注目於某一半導體晶片100，則在該半導體晶片100之4邊處係被形成有由雙重之絕緣環所成的構造體。
圖3，係為圖2中所示之A-A’間的剖面圖。
在矽基板105之表面105a上，係被形成有電路形成層101。
在電路形成層101處，係被形成有既定之電路、例如被形成有記憶體電路。又，在電路形成層101上，係形成有被作了層積的複數之絕緣層以及被設置於該複數之絕緣層處的配線還有接觸插塞等。
在電路形成層101之上，複數之電極墊片106係以既定之配置而被設置。在電極墊片106所被設置之位置處，被設置於電路形成層101之最上層處的配線，係從電路形成層101之表面而露出，並被與電極墊片106作電 性連接。電路形成層101，係為了對於電路形成面作保護，而除了被設置有電極墊片106之區域以外，為被絕緣膜107所被覆。
在電極墊片106之上，係被形成有由Cu等所成之柱狀體的凸塊(表面凸塊)108。
在表面凸塊108之上，係為了防止Cu之擴散，而被形成有Ni電鍍層109。又，在Ni電鍍層109之上，係為了防止氧化，而被形成有Au電鍍層110。
電極墊片106、表面凸塊108、Ni電鍍層109以及Au電鍍層110，係構成表面凸塊電極102a。
在矽基板105處，係於與電極墊片106相對應之位置處而被形成有貫通孔。在貫通孔中，係藉由隔著種晶層111而填充有導體層、例如Cu層，而形成貫通電極103。
又，在矽基板105處，係於貫通電極103之周圍，被形成有以將貫通電極103作包圍的方式而以圓筒狀來被埋入之藉由絕緣構件所構成的雙重之絕緣環112。絕緣環112，係為了謀求矽基板105和貫通電極103之間的絕緣而被形成。進而，在矽基板105處，與絕緣環112相同之雙重的絕緣環，係作為辨識部104，而以橫跨藉由切割區域31所區劃出之2個的半導體晶片100的方式而被形成。因此，並不需要追加新的工程，便能夠在形成絕緣環112之工程中而亦形成辨識部104。
在矽基板105之與表面相對向的背面105b 處，係隔著種晶層111而被形成有複數之例如由Cu等所成的柱狀體之凸塊(背面凸塊)113。背面凸塊113，係對應於表面凸塊108地而被形成，並經由貫通電極103而被與所對應之表面凸塊108作電性連接。
在背面凸塊113之上，係被形成有由Sn/Ag所成之半球狀的背面焊錫層114。
背面凸塊113以及背面焊錫層114，係構成背面凸塊電極102b。
圖4A，係為圖2中所示之半導體晶片100的上面圖以及從X方向和Y方向所觀察了的側面圖。又，圖4B，係為圖4A中所示之B-B’間的剖面圖。
藉由沿著圖2中所示之半導體晶圓30之切割區域31來進行切割，半導體晶片係被切斷並分離，而被個片化。如同上述一般，辨識部104，係以橫跨藉由切割區域31所區劃出之相鄰接之2個的半導體晶片100的方式來形成之。又，如同圖3中所示一般，辨識部104，係藉由雙重之絕緣環所構成。
因此，藉由切割，身為辨識部104之絕緣環係被切斷。之後，如圖4A中所示一般，在將半導體晶片100之表面和背面作連結的側面處，絕緣環係露出，並形成由在半導體晶片100之厚度方向上而延伸之4根的線所成之辨識部104。
接著，針對晶片層積體10之形成工程作說明。
圖5A~5D，係為對於半導體晶片100的層積工程作展示之剖面圖。
如圖5A中所示一般，半導體晶片100b係被載置於接合平台40上。在接合平台40處，係以在被載置有半導體晶片100b之載置面上露出的方式，而被設置有複數之第1吸附孔41。第1吸附孔41，係被與未圖示之真空幫浦作連接。半導體晶片100b，係藉由從第1吸附孔41而被真空幫浦所吸附，來固定在接合平台40上。於此，半導體晶片100b，係以將被形成有表面凸塊電極102a之表面朝上、亦即是以使背面和接合平台40相接的方式，而被作固定。在半導體晶片100b之背面，由於係並未被形成有凸塊電極102，因此係能夠將半導體晶片100b以良好的狀態來固定在接合平台40上。
接著，如圖5B中所示一般，將半導體晶片100a，使被形成有表面凸塊電極102a之表面朝向上方，而藉由接合工具42來作固定。在接合工具42處，係以在半導體晶片100a所被作固定之面上露出的方式，而被設置有複數之第2吸附孔43。第2吸附孔43，係被與未圖示之真空幫浦作連接。半導體晶片100a，係藉由從第2吸附孔43而被真空幫浦所吸附，來固定在接合工具42上。在藉由接合工具42而作了固定的狀態下，以使半導體晶片100a之背面凸塊電極102b和半導體晶片100b之表面凸塊電極102a相接的方式，而將半導體晶片100a層積於半導體晶片100b之上。之後，藉由使半導體晶片 100a之背面凸塊電極102b和半導體晶片100b之表面凸塊電極102a相接合，而將半導體晶片100彼此作接合。於此，係以使上下之半導體晶片100的被形成有辨識部104之側面會朝向相同之方向的方式，而層積半導體晶片100。
在凸塊電極102彼此之接合中，例如，係只要使用藉由設定為高溫(例如，300℃程度)之接合工具42來對於半導體晶片100施加既定之荷重的熱壓著法即可。另外，在接合中，不僅是熱壓著法，係亦可使用一面施加超音波一面進行壓著之超音波壓著法、或者是使用將此些作了併用的熱超音波壓著法。
藉由與參考圖5B所作了說明者相同的處理，來在第2段之半導體晶片100a上連接固定第3段之半導體晶片100a，並在第3段之半導體晶片100a上連接固定第4段之半導體晶片100a(圖5C)。
經過上述之工程，如同圖5D中所示一般，4個的半導體晶片100係被作層積。
圖6A，係為對於圖5D中所示之被作了層積的半導體晶片100而從第4段之半導體晶片100a側來作了觀察的上面圖，以及從X方向和Y方向而作了觀察的側面圖。
另外，在圖6A中，假設4個的半導體晶片100係為並不存在有凸塊電極間之位置偏差地來作了層積者。於此情況，各半導體晶片100之辨識部104，由於係 以會使其與被設置在特定之場所處的作為基準之凸塊電極102之間的位置關係成為相等的方式，而被形成，因此，各半導體晶片100之辨識部104的位置係相互對齊。辨識部104，由於係在半導體晶片100之4邊處而以從半導體晶片100之側面來露出的方式而被形成，因此，不論是從X方向來作觀察或者是從Y方向來作觀察，均能夠以視覺而辨認到各半導體晶片100之辨識部104的位置為相互對齊。
接著，針對當在作了層積的半導體晶片100中而發生有凸塊電極102間之位置偏差的情況時，而在圖6B中展示從Y方向而作了觀察時之側面圖，並於圖6C中展示從X方向而作了觀察時之側面圖。
當發生有凸塊電極102間之位置偏差的情況時，半導體晶片100之辨識部104，由於係以會使其與被設置在特定之場所處的作為基準之凸塊電極102之間的位置關係成為相等的方式，而被形成，因此，在各半導體晶片100之間，會發生辨識部104的位置偏差。辨識部104，由於係在半導體晶片100之4邊處而以從半導體晶片100之側面來露出的方式而被形成，因此，不論是從X方向來作觀察或者是從Y方向來作觀察，均能夠以視覺而辨認到係發生有辨識部104的位置偏差。
如此這般，在本實施形態中，係以會使其與被設置在特定之場所處的作為基準之凸塊電極102之間的位置關係成為相等的方式，而在各半導體晶片100之側面 處設置有辨識部104。因此，當將複數之半導體晶片100作了層積的情況時，藉由對於各半導體晶片100之辨識部104的整列狀態作確認，係能夠容易地檢測出凸塊電極間之位置偏差的發生和位置偏差的程度。
另外，在圖6A~6C中，係使用所層積了的半導體晶片100之端部為相互一致的例子來作了說明。於此，依存於切割之精確度，係會有在每一半導體晶片處的從半導體晶片100之端部起直到凸塊電極102為止的距離互為相異的情形。
針對當將從端部起直到凸塊電極102為止的距離為互為相異之複數之半導體晶片100作了層積的情況時，而在圖7A中展示從Y方向而對於所層積了的半導體晶片100作了觀察時之側面圖，並於圖7B中展示從X方向而作了觀察時之側面圖。另外，在圖7A、7B中，假設係為並未發生凸塊電極間之位置偏差者。
由於在每一半導體晶片之各者處的從半導體晶片100之端部起直到凸塊電極102為止的距離為互為相異，因此，如同圖7A、7B中所示一般，不論是從X方向作觀察或是從Y方向作觀察，均係發生有各半導體晶片100之端部的位置偏差。但是，由於係並未發生有各半導體晶片100之凸塊電極102間的位置偏差，因此各半導體晶片100之辨識部104係相互整列。辨識部104，由於係在半導體晶片100之4邊處而以從半導體晶片100之側面來露出的方式而被形成，因此，不論是對於作了層積的半 導體晶片100而從X方向來作觀察或者是從Y方向來作觀察，均能夠以視覺而辨認到各半導體晶片100之辨識部104的位置為相互對齊。
如同上述一般，依存於切割之精確度，由於會有導致在每一半導體晶片之各者處的從半導體晶片100之端部起直到凸塊電極102為止的距離互為相異的情形，因此，想要基於作了層積的半導體晶片100之各別的端部來檢測出凸塊電極102之位置偏差的發生及其程度一事，係為困難。但是，在本實施形態中，係以會使其與被設置在特定之場所處的作為基準之凸塊電極102之間的位置關係成為相等的方式，而在各半導體晶片100之側面處設置有辨識部104。因此，就算是發生有作了層積的半導體晶片100之端部的位置偏差，藉由對於各半導體晶片100之辨識部104的整列狀態作確認，係能夠容易地檢測出是否發生有凸塊電極間之位置偏差。
接著，針對圖5D中所示之對於作了層積的半導體晶片100之樹脂構件11的填充工程作說明。另外，樹脂構件11之填充工程，係對於在圖5D所示之工程之後藉由依據辨識部104之位置所進行的外觀檢查而判定為並不存在有凸塊電極102間之位置偏差者，而進行之。
圖8A~8D，係為對於樹脂構件11之填充工程作展示的剖面圖。
被作了層積的半導體晶片100，例如係如圖8A中所示一般，被載置在張貼於塗布平台50處之塗布用 薄片51之上。在塗布用薄片51處，係使用有像是氟系薄片或者是塗布有矽系接著材之薄片等一般之相對於樹脂構件11(例如，底部填充材)而浸濕性為差的材料。另外，塗布用薄片51，係並不需要直接張貼在塗布平台50上，只要是在平坦之面上，則不論是張貼於何處均可，例如，係亦可張貼在載置於塗布平台50上之既定的治具等處。
接著，如圖8B中所示一般，藉由分配器52，來從被載置在塗布用薄片51上之被作了層積的半導體晶片100之端部近旁而供給底部填充材53。被作了供給的底部填充材53，係一面在被作了層積的半導體晶片100之周圍形成裾(fillet)，一面藉由毛細管現象而進入半導體晶片100間之空隙中，並將半導體晶片100間之空隙填埋。
在本實施形態中，由於在塗布用薄片51處係使用有由相對於底部填充材53而浸濕性為差之材料所成的薄片，因此底部填充材53之擴廣係被抑制，而不會有使裾之寬幅變大的情況。
在供給了底部填充材53之後，在將被作了層積的半導體晶片100載置於塗布用薄片51上的狀態下，而以既定之溫度、例如以150℃程度來進行硬化(熱處理)，藉由此來使底部填充材53熱硬化。其結果，如圖8C中所示一般，係形成有藉由樹脂構件11而將被作了層積的半導體晶片100之周圍覆蓋並且將半導體晶片100間 之空隙作了填埋的晶片層積體10。
在本實施形態中，由於在塗布用薄片51處係使用有由相對於底部填充材53而浸濕性為差之材料所成的薄片，因此係能夠防止在熱硬化時而底部填充材53附著於塗布用薄片51上。
在樹脂構件11之熱硬化後，晶片層積體10，係如同圖8D中所示一般，被從塗布用薄片51而拾起。在本實施形態中，由於在塗布用薄片51處係使用有由相對於底部填充材53而浸濕性為差之材料所成的薄片，因此係能夠容易地將晶片層積體10從塗布用薄片51而拾起。
另外，在供給底部填充材53時，當被作了層積的半導體晶片100會有發生位置偏移之虞的情況時，係亦可先使用樹脂接著材來將被作了層積的半導體晶片100暫時固定接著在塗布用薄片51上，之後再供給底部填充材53。
接著，針對半導體裝置1之組裝工程作說明。
圖9A~圖9E，係為對於半導體裝置1的組裝工程作展示之剖面圖。另外，在圖9A~9E中，係對於將複數之半導體裝置1整批地形成之組裝工程的其中一例作展示。
在半導體裝置1的組裝時，如同圖9A中所示一般，首先準備具備有被配置為矩陣狀之複數之製品形成部60的配線基板20。製品形成部60，係分別為成為半導 體裝置1之配線基板20的部位。在製品形成部60處，係被形成有既定之圖案的配線。各配線，除了連接墊片22和焊墊24以外，係藉由抗蝕阻膜等之絕緣膜21而被作覆蓋。製品形成部60間，係成為在將各半導體裝置1個別地作切離時之切割線61。
在配線基板20之其中一面上，係被形成有用以與晶片層積體10作連接之複數的連接墊片22。在配線基板20之另外一面上，係被形成有用以與成為外部端子之導電性之焊錫球23作連接的複數之焊墊24。連接墊片21，係藉由配線而被與既定之焊墊24作連接。在連接墊片22上，係被形成有螺樁凸塊26。
若是結束了配線基板20之準備，則係如圖9A中所示一般，在各製品形成部60上，藉由分配器而塗布絕緣性之樹脂構件27、例如塗布NCP(Non Conductive Paste)。
接著，藉由接合工具等來將晶片層積體10之半導體晶片100b的背面作吸附保持，並如圖9B中所示一般，在製品形成部60上搭載晶片層積體10，而將晶片層積體10之最下端的半導體晶片100a之表面凸塊電極102a和螺樁凸塊26例如使用熱壓著法來作接合。此時，接著構件27係被填充於晶片層積體10和配線基板20之間，配線基板20和晶片層積體10係被作接著固定。於此，在晶片層積體10之周圍由於係以錐狀而被形成有樹脂構件11，因此係能夠防止接著構件27之上爬。藉由此，係能 夠降低起因於接著構件27附著在接合工具上一事所導致的晶片層積體10之破損或接合不良等。
搭載有晶片層積體10之配線基板20，係被安裝在未圖示之轉移模封裝置的由上模和下模所成之成形模具中，並移行至模封工程。
在成形模具之上模處，係被形成有將複數之晶片層積體10整批作覆蓋的未圖示之空腔，被搭載於配線基板20上之晶片層積體10，係被收容於空腔內。
接著，將作了加熱熔融之密封樹脂注入至被設置在成形模具之上模處的空腔內，並以將晶片層積體10全體作覆蓋的方式而將密封樹脂填充至空腔內。在密封樹脂中，例如係使用環氧樹脂等之熱硬化性樹脂。
接著，在藉由密封樹脂而將空腔內作了填充的狀態下，以既定之溫度、例如以180℃程度來進行硬化，藉由此而使密封樹脂熱硬化。藉由此，如圖9C中所示一般，形成將被搭載於複數之製品形成部60上的各晶片層積體10整批地作覆蓋之密封樹脂28。進而，藉由以既定之溫度來進行烘烤，而使密封樹脂28完全硬化。
在本實施形態中，由於係在藉由樹脂構件11來將晶片層積體10之半導體晶片100間作了密封之後，再形成將晶片層積體10全體作覆蓋之密封構件28，因此係能夠對於在半導體晶片100彼此之空隙中而發生空洞的情況作抑制。
若是形成密封樹脂28，則係移行至球安裝工 程，如圖9D中所示一般，在被形成於配線基板20之另外一面上的焊墊24處，係被連接有焊錫球23。
在球安裝工程中，係使用具備有位置為與配線基板20之各焊墊24相互一致的複數之吸附孔的安裝工具，來將複數之焊錫球23作吸附保持，並將助焊劑轉印至各焊錫球23處。之後，將各焊錫球23整批地連接於配線基板20之焊墊24上。
在結束了對於全部的製品形成部60之焊錫球23的連接之後，藉由對於配線基板20進行回焊，而將焊錫球23和焊墊24作連接。
若是焊錫球23之連接結束，則係移行至基板切割工程，並藉由以切割線61來將各個的製品形成部60切斷分離，而形成半導體裝置1。
在基板切割工程中，係藉由於密封樹脂28處貼附未圖示之切割膠帶，來支持製品形成部60。之後，藉由未圖示之切割裝置所具備的切割刃，來如同圖9E中所示一般，藉由以切割線61而進行切斷，來將各個的製品形成部60之每一者作分離。在切斷分離後，藉由將切割膠帶從製品形成部60而拾起，係能夠得到圖1中所示之CoC型之半導體裝置1。
若依據本實施形態，則係先作成將複數之半導體晶片100作了積載的晶片層積體10，之後再將晶片層積體10連接固定在配線基板20上。因此，係能夠降低起因於半導體晶片100和配線基板20間之熱膨脹係數或 剛性的差異而導致在製造時之熱處理中所對於半導體晶片100彼此之連接部或半導體晶片100施加的熱應力。其結果，係能夠抑制半導體晶片100彼此之連接部的破斷和在半導體晶片100處所發生的碎裂。
又，係在由相對於底部填充材而浸濕性為差之材料所成的塗布用薄片51上，對於被作了層積的半導體晶片100供給樹脂構件11(底部填充材53)。因此，藉由底部填充材53所形成之裾的形狀係會安定化，並且係能夠將裾之寬幅縮小。其結果，係能夠抑制封裝尺寸之大型化。進而，在底部填充材53之供給後，係能夠容易地從塗布用薄片51而將晶片層積體10拾起。
如此這般，本實施形態之半導體裝置1，係將分別具備有複數之凸塊電極的複數之半導體晶片100作層積，複數之半導體晶片100，係具備有被形成於各別之側面處的辨識部104，在半導體晶片100各者處，複數之凸塊電極102係被同樣地作配置，辨識部104，係以使其與複數之凸塊電極102中的被設置在既定之場所處之作為基準的凸塊電極102之間的位置關係會成為相等的方式來形成，複數之半導體晶片100，係將被設置於各半導體晶片100處之凸塊電極102以半導體晶片100之層積順序來作電性連接，並且以使被形成有辨識部104之側面會朝向相同方向的方式而被作層積。
又，本實施形態之半導體裝置1，係具備有：第1半導體晶片(例如，半導體晶片100b)，係具備作 為第1主面之表面、和與表面相對向之作為第2主面之背面、和連結表面和背面之作為第1側面的側面、和被形成於表面上之作為第1凸塊電極之表面凸塊電極102a、和對應於表面凸塊電極102a而被形成於側面上之作為第1辨識部之辨識部104；和第2半導體晶片，係具備作為第3主面之背面、和與背面相對向之作為第4主面之表面、和連結背面與表面之作為第2側面之側面、和對應於第1凸塊電極而被形成於背面上之作為第2凸塊電極之背面凸塊電極102b、和與背面凸塊電極102b作電性連接並被形成於表面上之作為第3凸塊電極之表面凸塊電極102a、和相對於背面凸塊電極，來以與第1凸塊電極和第1辨識部間之位置關係相同的位置關係而形成於第2側面上之作為第2辨識部之辨識部104，並使第2凸塊電極與第1凸塊電極作連接，且以使第1側面和第2側面朝向相同方向的方式來層積於第1半導體晶片上。
在各半導體晶片100處，係以與作為基準之凸塊電極102之間之位置關係會成為相等的方式，來在半導體晶片100之側面形成有辨識部104，並且，係以使被形成有辨識部104之側面會朝向相同之方向的方式，來層積半導體晶片100，因此，在將複數之半導體晶片100作了層積的情況時，藉由對於各半導體晶片100之辨識部104的整列狀態作確認，係能夠容易地檢測出凸塊電極102間之位置偏差的發生及其程度。
(第2實施形態)
圖10，係為被形成有本發明之第2實施形態之半導體晶片100A的半導體晶圓30A之上面圖。
在半導體晶圓30處，作為辨識部104，係被形成有由雙重之絕緣環所成的構造體。另一方面，在本實施形態之半導體晶圓30A處，係作為辨識部，而被形成有橫跨藉由切割區域31所區劃出之相鄰接之2個的半導體晶片100A並且與身為藉由切割所被作研削的邊界之切割線31A相正交的直線狀之構造體。
圖11A，係為半導體晶片100A的上面圖以及從X方向和Y方向所對於半導體晶片100A作了觀察的側面圖。又，圖11B，係為圖11A中所示之C-C’間的剖面圖。
如圖11A、11B中所示一般，在半導體晶片100A處，係於半導體晶片100A之4邊處，被形成有與半導體晶片100A之端部相正交的直線狀之辨識部104A。
在本實施形態中，亦係與第1實施形態同樣的，係以會使其與被設置在特定之場所處的作為基準之凸塊電極102之間的位置關係成為相等的方式，而設置有會從各半導體晶片100A之側面處而至少露出一部分之辨識部104A。因此，當將半導體晶片100A作了層積的情況時，藉由對於各半導體晶片100A之辨識部104A的整列狀態作確認，係能夠容易地檢測出凸塊電極102間之位置偏差的發生和位置偏差的程度。
又，在第1實施形態中，辨識部104係被形成為圓形狀，相對於此，在本實施形態中，辨識部104A係被形成為與切割線31相正交之直線狀。當辨識部104係身為圓形狀的情況時，當起因於在切割工程中之切斷誤差等而導致半導體晶片之切斷位置有所偏移的情況時，係會有發生辨識部104之位置偏差的情形。另一方面，藉由如同本實施形態一般地而將辨識部104A形成為與切割線31相正交之直線狀，由於就算是在切割工程中產生有切斷誤差，辨識部104A之位置也不會偏移，因此係能夠以高精確度來形成辨識部。
(第3實施形態)
在第2實施形態之半導體晶片100A中，辨識部104A係被形成於矽基板上。另一方面，在本實施形態之半導體晶片100B中，辨識部係被形成於矽基板上之電路形成層處。
圖12A，係為半導體晶片100B的上面圖以及從X方向和Y方向所對於半導體晶片100B作了觀察的側面圖。又，圖12B，係為圖12A中所示之D-D’間的剖面圖。
如圖12A、12B中所示一般，在半導體晶片100B處，係於半導體晶片100B之4邊處，被形成有與半導體晶片100B之端部相正交的直線狀之辨識部104B。於此，辨識部104B，係利用電路形成層101之配線圖案所 形成。
在本實施形態中，亦係與第1以及第2實施形態同樣的，係在各半導體晶片100B處，以會使其與被設置在特定之場所處的作為基準之凸塊電極102之間的位置關係成為相等的方式，而設置有會從各半導體晶片100B之側面處而至少露出一部分之辨識部104B。因此，當將半導體晶片100B作了層積的情況時，藉由對於各半導體晶片100B之辨識部104B的整列狀態作確認，係能夠容易地檢測出凸塊電極102間之位置偏差的發生和位置偏差的程度。
又，在本實施形態中，辨識部104B，係被形成為與切割線31相正交之直線狀。因此，與第2實施形態相同的，由於就算是在切割工程中產生有切斷誤差，辨識部104A之位置也不會偏移，因此係能夠以高精確度來形成辨識部。
又，在本實施形態中，辨識部104B，係被形成於電路形成層101處。因此，係並不需要在矽基板上形成用以將絕緣構件作埋入之溝，故而，相較於第1以及第2實施形態，係能夠使半導體晶片之強度提昇。又，被形成在矽基板上之溝，係容易成為晶片碎裂之起點，但是，在本實施形態中，由於係並不需要為了形成辨識部104B而在矽基板上形成溝，因此係能夠降低晶片碎裂之發生的可能性。
另外，在第1~第3實施形態中，雖係針對將 相同尺寸之半導體晶片作層積的情況為例來作了說明，但是本發明係並不被限定於此。只要作為基準之凸塊電極的位置為相同，則如同圖13中所示一般，係亦可適用在將尺寸以及電路構成均為相異之半導體晶片作層積的情況中。另外，在圖13中，係針對在4個的記憶體晶片100C之上而層積有尺寸為較記憶體晶片100C而更小之對於記憶體晶片100C作控制的介面(IF)晶片100D的例子來作展示。如圖13中所示一般，就算是在將尺寸相異之半導體晶片作了層積的情況時，藉由從側面來對於辨識部作視覺辨認，係能夠容易地檢測出凸塊電極間之位置偏差的發生和位置偏差的程度。
以上，雖係基於實施形態來對於由本發明者所進行之發明作了說明，但是，本發明係並不被限定於上述實施形態，當然的，在不脫離其要旨的範圍內，係可作各種之變更。例如，在上述之實施形態中，雖係針對將4個的記憶體晶片作了層積的晶片層積體以及將4個的記憶體晶片和1個的IF晶片作了層積的晶片層積體來作了說明，但是本發明不論是對於層積有何種之半導體晶片的情況均可作適用。又，半導體晶片之層積數量亦並不被限定於4、5段，而亦可為3段以下或者是6段以上。
又，在上述之實施形態中，雖係針對將辨識部形成為圓形狀或者是直線狀的情況來作了說明，但是，只要是以使其與作為基準之凸塊間的位置關係會成為相等的方式來形成，則辨識部不論是以何種形狀來構成均可。
又，在上述之實施形態中，雖係針對在將半導體晶片作了層積之後再供給底部填充材的例子來作了說明，但是，例如亦可將張貼有透明之樹脂層(例如，透明之NCF(Non Conductive Film))的半導體晶片作層積，並藉由在進行覆晶安裝的同時使NCF熔融，來使其填充於半導體晶片間。就算是樹脂層從半導體晶片之側面而滲出或者是將半導體晶片之側面作覆蓋，亦由於樹脂層係為透明，因此係能夠對於辨識部作視覺辨認。
本申請案，係以2013年6月21日申請之日本出願2013-130330號作為基礎，並主張優先權，且將其揭示內容全部包含於本案中。
1‧‧‧半導體裝置
10‧‧‧晶片層積體
11‧‧‧樹脂構件
20‧‧‧配線基板
21‧‧‧絕緣膜
22‧‧‧連接墊片
23‧‧‧焊錫球
24‧‧‧焊墊
25‧‧‧絕緣基材
26‧‧‧螺樁凸塊
27‧‧‧樹脂構件
28‧‧‧密封樹脂
100、100a、100b‧‧‧半導體晶片
101‧‧‧電路形成層
102a‧‧‧表面凸塊電極
102b‧‧‧背面凸塊電極
103‧‧‧貫通電極
104‧‧‧辨識部

Claims (7)

  1. 一種半導體裝置，其特徵為：係將分別具備有複數之凸塊電極的複數之半導體晶片作層積，前述複數之半導體晶片，係具備有被形成於各別之側面處的辨識部，在前述半導體晶片之各者處，前述複數之凸塊電極係被同樣地作配置，前述辨識部，係以使其與前述複數之凸塊電極中的被設置在既定之場所處之作為基準的凸塊電極之間的位置關係會成為相等的方式來形成，前述複數之半導體晶片，係將被設置於各半導體晶片處之凸塊電極以半導體晶片之層積順序來作電性連接，並且以使被形成有前述辨識部之側面會朝向相同方向的方式而被做層積。
  2. 一種半導體裝置，其特徵為，係具備有：第1半導體晶片，係具備第1主面、和與前述第1主面相對向之第2主面、和連結前述第1主面和前述第2主面之第1側面、和被形成於前述第1主面上之第1凸塊電極、和對應於前述第1凸塊電極而被形成於前述第1側面上之第1辨識部；和第2半導體晶片，係具備第3主面、和與前述第3主面相對向之第4主面、和連結前述第3主面和前述第4主面之第2側面、和對應於前述第1凸塊電極而被形成於第3主面上之第2凸塊電極、和與前述第2凸塊電極作電性 連接並被形成於前述第4主面上之第3凸塊電極、和相對於前述第2凸塊電極，來以與前述第1凸塊電極和前述第1辨識部間之位置關係相同的位置關係而形成於前述第2側面上之第2辨識部，並使前述第2凸塊電極與前述第1凸塊電極作連接，且以使前述第1側面和前述第2側面朝向相同方向的方式來層積於前述第1半導體晶片上。
  3. 如申請專利範圍第1項或第2項所記載之半導體裝置，其中，在前述半導體晶片所被形成之晶圓上，係被形成有藉由切割區域所區劃出來並橫跨相鄰接之半導體晶片的構造體，前述辨識部，係藉由對於前述切割區域進行切割而形成之。
  4. 如申請專利範圍第1項或第2項所記載之半導體裝置，其中，前述構造體，係被形成為圓狀。
  5. 如申請專利範圍第1項或第2項所記載之半導體裝置，其中，前述構造體，係被形成為與切割線相正交之直線狀。
  6. 如申請專利範圍第1~5項中之任一項所記載之半導體裝置，其中，前述構造體，係藉由將絕緣構件埋入至被形成於前述半導體晶片之基板上的溝部中，而形成之。
  7. 如申請專利範圍第1~5項中之任一項所記載之半導體裝置，其中，前述辨識部，係藉由前述半導體晶片之電路形成層的配線圖案而形成。
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KR20160022862A (ko) 2016-03-02
DE112014002910B4 (de) 2020-08-06
WO2014203807A1 (ja) 2014-12-24
US20200203317A1 (en) 2020-06-25

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