TW201513297A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201513297A
TW201513297A TW103114516A TW103114516A TW201513297A TW 201513297 A TW201513297 A TW 201513297A TW 103114516 A TW103114516 A TW 103114516A TW 103114516 A TW103114516 A TW 103114516A TW 201513297 A TW201513297 A TW 201513297A
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Taiwan
Prior art keywords
semiconductor wafer
semiconductor device
end portions
sealing resin
semiconductor
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TW103114516A
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English (en)
Inventor
Masahiro Yamaguchi
Toru Saga
Koji Hosokawa
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Ps4 Luxco Sarl
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Publication of TW201513297A publication Critical patent/TW201513297A/zh

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

提供一種適於作為具有PoP構造之半導體裝置的上側封裝來利用之半導體裝置。 係具備有被覆晶安裝於配線基板(30)之其中一面(32)上的半導體晶片(10)、和被覆晶安裝於配線基板(30)之另外一面(33)上的半導體晶片(20)，此些之半導體晶片(10、20)之搭載方向係相互差異90°。藉由此，在配線基板(30)上之配線圖案(41、42)的佈局係不會有局部性地密集的情形，而成為能夠提高佈局之自由度。並且，在將半導體晶片(10、20)安裝於配線基板(30)上時，由於係能夠藉由平台來將荷重所集中之位置作保持，因此係成為能夠防止在配線基板處所產生的變形。

Description

半導體裝置及其製造方法
本發明，係有關於半導體裝置及其製造方法，特別是有關於在配線基板之兩面上而將半導體晶片作覆晶安裝所成的半導體裝置及其製造方法。
近年來，係提案有在硬質之配線基板上而將複數之半導體晶片作覆晶安裝所成的半導體裝置。例如，在專利文獻1中，係揭示有在配線基板之兩面上而分別將半導體晶片作了覆晶安裝的形態之半導體裝置。如此這般，若是在配線基板之兩面上而分別將半導體晶片作覆晶安裝，則係成為能夠達成更為高密度之封裝。
〔先前技術文獻〕 〔專利文獻〕
[專利文獻1]日本特開2006-210566號公報
[專利文獻2]日本特開2007-287906號公報
[專利文獻3]日本特開2010-103348號公報
然而，在專利文獻1所記載之半導體裝置中，由於半導體晶片和外部端子係被配置在配線基板之同一平面(背面)處，因此半導體晶片之背面和外部端子之前端之間的高度差、也就是所謂的腳高(standoff)，係變得非常小。因此，係有著難以搭載於存在有凹凸之基板表面上的問題。作為存在有凹凸之基板表面，例如係為具有PoP(Package on Package)構造之半導體裝置的下側封裝之表面等。故而，在專利文獻1中所記載之半導體裝置，係難以作為具有PoP構造之半導體裝置的上側封裝來使用。
為了解決此種問題，係可考慮如同專利文獻2中所記載之半導體裝置一般地而使導體柱從配線基板突出的方法。然而，若是使導體柱從配線基板而突出，則依存於下側封裝之構造，會有使腳高成為過剩並使全體之厚度產生必要以上之增大的情形。又，在專利文獻2中所記載之半導體裝置，由於係並非為在配線基板之兩面上安裝半導體晶片者，亦並非為進行覆晶安裝者，因此關於應該如何將此對於在配線基板之兩面上分別將半導體晶片作覆晶安裝的形態之半導體裝置作適用一事，係仍不明瞭。
又，雖然並非為將半導體晶片作覆晶安裝所成的半導體裝置，但是，在專利文獻3中，係揭示有在配 線基板之兩面上分別安裝半導體晶片並且將此些之半導體晶片藉由密封樹脂來覆蓋，再經由貫通密封樹脂所設置的通孔導體來將配線基板和外部端子作連接的構造。然而，在將半導體晶片覆晶安裝於配線基板上的情況時，係成為需要進行一面施加荷重以及超音波一面將半導體晶片推壓附著於配線基板上等的製程，但是，在專利文獻3中所記載之半導體裝置，由於係採用打線接合，因此係並不會發生在覆晶安裝中所會出現的像是起因於荷重以及超音波之施加所導致的配線基板之變形等的特有之問題。
由本發明所致之半導體裝置，其特徵為，係 包含有：配線基板，係具備被形成於其中一面上之複數的第1連接墊片、和被形成為另外一面上之複數的第2連接墊片、以及被配置於前述另外一面上並被與前述第1或第2連接墊片作了電性連接之複數的焊墊；和第1半導體晶片，係具備藉由相互對向之第1以及第2端部和相互對向之第3以及第4端部所區劃出之其中一面、和沿著前述其中一面之前述第1以及第2端部的各者而被作了配置的複數之第1凸塊電極，並以使前述複數之第1凸塊電極被與前述複數之第1連接墊片作連接的方式，而被搭載於前述配線基板之前述其中一面上；和第1密封樹脂，係以覆蓋前述第1半導體晶片的方式而被形成於前述配線基板之前述其中一面上；和第2半導體晶片，係具備藉由相互對向 之第1以及第2端部和相互對向之第3以及第4端部所區劃出之其中一面、和沿著前述其中一面之前述第1以及第2端部的各者而被作了配置的複數之第2凸塊電極，並以使前述複數之第2凸塊電極被與前述複數之第2連接墊片作連接且使前述第2半導體晶片之前述第1以及第2端部分別與前述第1半導體晶片之前述第3以及第4端部相互平行地來作配置的方式，而被搭載於前述配線基板之前述另外一面上；和第2密封樹脂，係以覆蓋前述第2半導體晶片的方式而被形成於前述配線基板之前述另外一面上；和複數之導體柱，係貫通前述第2密封樹脂地而被設置，並使其中一端與分別所對應之前述複數之焊墊的其中一者作連接，且使另外一端從前述第2密封樹脂而作了露出；和複數之焊錫球，係被搭載於前述複數之導體柱的前述另外一端處。
由本發明所致之半導體裝置之製造方法，其 特徵為，係具備有：在配線基板之其中一面上，形成複數的第1連接墊片，並在前述配線基板之另外一面上，形成複數的第2連接墊片、和被與前述第1或第2連接墊片作了電性連接之複數的焊墊、以及使其中一端分別與相對應之前述複數之墊片的其中一者作了連接的複數之導體柱之工程；和將具備藉由相互對向之第1以及第2端部和相互對向之第3以及第4端部所區劃出之其中一面與沿著前述其中一面之前述第1以及第2端部的各者而被作了配置的複數之第1凸塊電極的第1半導體晶片，以使前述複數之 第1凸塊電極被與前述複數之第1連接墊片作連接的方式，而搭載於前述配線基板之前述其中一面上之工程；和將具備藉由相互對向之第1以及第2端部和相互對向之第3以及第4端部所區劃出之其中一面與沿著前述其中一面之前述第1以及第2端部的各者而被作了配置的複數之第2凸塊電極的第2半導體晶片，以使前述複數之第2凸塊電極被與前述複數之第2連接墊片作連接且使前述第2半導體晶片之前述第1以及第2端部分別與前述第1半導體晶片之前述第3以及第4端部相互平行地來作配置的方式，而搭載於前述配線基板之前述另外一面上之工程；和以覆蓋前述第1以及第2半導體晶片的方式，而於前述配線基板之前述其中一面以及另外一面上分別形成第1以及第2密封樹脂之工程；和以使前述複數之導體柱的另外一端露出的方式，來對於前述第2密封樹脂進行研削之工程；和在前述複數之導體柱的前述另外一端處而搭載複數之焊錫球之工程。
若依據本發明，則由於係在貫通密封樹脂之導體柱的另外一端處搭載有焊錫球，因此係成為能夠充分地確保腳高。並且，由於分別被安裝於配線基板之兩面上之2個的半導體晶片之搭載方向係相互差異90°，因此，在配線基板上之配線圖案的佈局係不會有局部性地密集的情形，而成為能夠提高佈局之自由度。並且，在使用接合 工具而將半導體晶片安裝於配線基板上時，由於係能夠藉由平台來將荷重所集中之位置作保持，因此係成為能夠防止在配線基板處所產生的變形。
10、20‧‧‧半導體晶片
10a‧‧‧半導體晶片之背面
11、21‧‧‧墊片電極
12、22‧‧‧凸塊電極
13、23‧‧‧焊錫層
30‧‧‧配線基板
31‧‧‧絕緣基材
31X‧‧‧母材
32‧‧‧其中一面
33‧‧‧另外一面
41、42‧‧‧配線圖案
41a、42a‧‧‧連接墊片
42b‧‧‧焊墊
43‧‧‧通孔導體
44‧‧‧導體柱
44a‧‧‧導體柱之前端
45‧‧‧焊錫球
51~54‧‧‧絕緣膜
51a、53a‧‧‧開口部
61、62‧‧‧底部填充材
71、72‧‧‧密封樹脂
80‧‧‧封裝
81、87‧‧‧焊墊
82‧‧‧配線基板
83‧‧‧焊錫球
84‧‧‧半導體晶片
84a‧‧‧凸塊電極
85‧‧‧連接墊片
86‧‧‧通孔導體
88‧‧‧底部填充材
89‧‧‧絕緣膜
90‧‧‧平台
91、92‧‧‧空腔
93‧‧‧接合工具
94‧‧‧吸引噴嘴
100、200‧‧‧半導體裝置
L11~L14、L21~L24、L31~L34‧‧‧邊(端部)
[圖1]對於由本發明之第1實施形態所致的半導體裝置100之構成作展示的剖面圖。
[圖2]對於半導體裝置100而從上面方向作了觀察的略平面圖。
[圖3]對於半導體裝置100而從背面方向作了觀察的略平面圖。
[圖4]從半導體裝置100而將配線基板30拔出而作展示的剖面圖。
[圖5]對於配線基板30而從上面方向作了觀察的略平面圖。
[圖6]對於配線基板30而從背面方向作了觀察的略平面圖。
[圖7]對於使用有半導體裝置100之具有PoP構造的半導體裝置之構成作展示的剖面圖。
[圖8]用以對於半導體裝置100的製造方法作說明之工程圖。
[圖9]用以對於半導體裝置100的製造方法作說明之工程圖。
[圖10]用以對於半導體裝置100的製造方法作說明之工程圖。
[圖11]用以對於半導體裝置100的製造方法作說明之工程圖。
[圖12]用以對於半導體裝置100的製造方法作說明之工程圖。
[圖13]用以對於半導體裝置100的製造方法作說明之工程圖。
[圖14]用以對於半導體裝置100的製造方法作說明之工程圖。
[圖15]用以對於在絕緣基材31之其中一面32上而將半導體晶片10作覆晶安裝之方法作說明的圖。
[圖16]用以對於半導體裝置100的由變形例所致之製造方法作說明之工程圖。
[圖17]用以對於半導體裝置100的由變形例所致之製造方法作說明之工程圖。
[圖18]對於由本發明之第2實施形態所致的半導體裝置200之構成作展示的剖面圖。
以下，參考所添附之圖面，針對本發明之理想實施形態作詳細說明。
圖1，係為對於由本發明之第1實施形態所致的半導體裝置100之構成作展示的剖面圖，圖2以及圖 3，係分別為對於半導體裝置100而從上面方向以及背面方向來作了觀察的略平面圖。又，圖4，係為從半導體裝置100而將配線基板30拔出而作展示的剖面圖，圖5以及圖6，係分別為對於配線基板30而從上面方向以及背面方向來作了觀察的略平面圖。
如圖1~圖3中所示一般，由本實施形態所致 之半導體裝置100，係具備有配線基板30以及分別被覆晶安裝於其之兩面上之2個的半導體晶片10、20。雖並未特別作限定，但是，在本實施形態中，半導體晶片10、20係為DRAM(Dynamic Random Access Memory)，並相互具備有相同的電路構成以及相同的墊片配置。但是，本發明係並不被限定於此，半導體晶片10、20係亦可為快閃記憶體等之其他種類的記憶體晶片，又，亦可構成為使半導體晶片10、20之其中一方身為記憶體晶片並使另外一方身為對此進行控制之控制晶片。
如圖2中所示一般，半導體晶片10，係為將 X方向作為長邊L11、L12，並將Y方向作為短邊L13、L14之矩形，在其之其中一面上，係沿著兩短邊L13、L14而於Y方向上被配列有複數之墊片電極11。半導體晶片10之各邊L11~L14，係為區劃出半導體晶片10之其中一面的端部，並分別與配線基板30之邊L31~L34相對向。在墊片電極11上，係被設置有從半導體晶片10之其中一面而突出的複數之第1凸塊電極12。凸塊電極12，係藉由銅等之金屬材料所構成，於其之前端處，係被 形成有焊錫層13。
如圖3中所示一般，半導體晶片20，係為將 X方向作為短邊L21、L22，並將Y方向作為長邊L23、L24之矩形，在其之其中一面上，係沿著兩短邊L21、L22而於X方向上被配列有複數之墊片電極21。半導體晶片20之各邊L21~L24，係為區劃出半導體晶片20之其中一面的端部，並分別與配線基板30之邊L31~L34相對向。在墊片電極21上，係被設置有從半導體晶片20之其中一面而突出的複數之第2凸塊電極22。凸塊電極22，係藉由銅等之金屬材料所構成，於其之前端處，係被形成有焊錫層23。
如此這般，半導體晶片10、20，係具備有沿 著短邊而被形成有凸塊電極12、22之邊緣墊片構造，並以相互作了90°旋轉的狀態而被搭載於配線基板30上。亦即是，半導體晶片10之長邊L11、L12和半導體晶片20之短邊L21、L22係被相互平行地作配置，半導體晶片20之短邊L13、L14和半導體晶片20之長邊L23、L24係被相互平行地作配置。因此，半導體晶片10之凸塊電極12，係位置在平面上而言與半導體晶片20之搭載位置相異的部份處，半導體晶片20之凸塊電極22，係位置在平面上而言與半導體晶片10之搭載位置相異的部份處。
配線基板30，係將在玻璃織材(glass cross)等之芯材中而含浸有環氧樹脂等所成的硬質之絕緣基材31作為母材，於其之其中一面32上，係被覆晶安裝有半 導體晶片10，於另外一面33上，係被覆晶安裝有半導體晶片20。雖並未特別作限定，但是，作為絕緣基材31之厚度，係可設為90μm程度。在絕緣基材31之其中一面32上，係被設置有複數之配線圖案41以及將此些作覆蓋的第1以及第2絕緣膜51、52。同樣的，在絕緣基材31之另外一面33上，係被設置有複數之配線圖案42以及將此些作覆蓋的第3以及第4絕緣膜53、54。作為絕緣膜51~54，係可使用所謂的抗焊劑。雖並未特別作限定，但是，絕緣膜52之膜厚係以較絕緣膜51而更薄為理想，同樣的，絕緣膜54之膜厚係以較絕緣膜53而更薄為理想。
如同圖5中所示一般，配線圖案41之一部 分，係具備有從絕緣膜51、52而露出之複數的第1連接墊片41a，半導體晶片10之凸塊電極12，係經由焊錫層13而被與此連接墊片41a相互接合。絕緣膜51，係被形成於絕緣基材31之其中一面32的外周區域處，於中央區域處係設置有並未被形成絕緣膜51之開口部51a。在該開口部51a內，係以使連接墊片41a露出的方式而被形成有絕緣膜52。之後，如圖2中所示一般，以使凸塊電極12與連接墊片41a相接合的方式，而將半導體晶片10安裝於開口部51a內。
半導體晶片10和絕緣膜52之間的空隙，係 被底部填充材61所填充。於此，若是將絕緣膜52之膜厚設定為薄，則係成為能夠確實地在半導體晶片10和絕緣膜52之間確保有空間，而能夠對起因於半導體晶片10和 絕緣膜52之間之干涉所導致的連接不良等作防止。又，起因於配線圖案41之存在而成為具有凹凸的絕緣基材31之其中一面32，由於係藉由絕緣膜52而被平坦化，因此係亦能夠確保在填充底部填充材61時之流動性。進而，若是將絕緣膜51之膜厚設定為較絕緣膜52而更厚，則由於配線基板30之剛性係被提高，因此在處理上係變得容易。
同樣的，如同圖6中所示一般，配線圖案42 之一部分，係具備有從絕緣膜53、54而露出之複數的連接墊片42a，半導體晶片20之凸塊電極22，係經由焊錫層23而被與此連接墊片42a相互接合。絕緣膜53，係被形成於絕緣基材31之另外一面33的外周區域處，於中央區域處係設置有並未被形成絕緣膜53之開口部53a。在該開口部53a內，係以使連接墊片42a露出的方式而被形成有絕緣膜54。之後，以使凸塊電極22與連接墊片42a相接合的方式，而將半導體晶片20安裝於開口部53a內。
半導體晶片20和絕緣膜54之間的空隙，係 被底部填充材62所填充。於此，若是將絕緣膜54之膜厚設定為薄，則係成為能夠確實地在半導體晶片20和絕緣膜54之間確保有空間，而能夠對起因於半導體晶片20和絕緣膜54之間之干涉所導致的連接不良等作防止。又，起因於配線圖案42之存在而成為具有凹凸的絕緣基材31之另外一面33，由於係藉由絕緣膜54而被平坦化，因此 係亦能夠確保在填充底部填充材62時之流動性。進而，若是將絕緣膜53之膜厚設定為較絕緣膜54而更厚，則由於配線基板30之剛性係被提高，因此在處理上係變得容易。
又，絕緣基材31之其中一面32，係以將半導 體晶片10之背面以及側面作覆蓋的方式，而被第1密封樹脂71所密封。同樣的，絕緣基材31之另外一面33，係以將半導體晶片20之背面以及側面作覆蓋的方式，而被第2密封樹脂72所密封。雖並未特別作限定，但是，密封樹脂71、72係由熱硬化性之環氧樹脂等所成。
進而，在絕緣基材31之另外一面33處，係 設置有被與連接墊片41a或42a作了電性連接的複數之焊墊42b。焊墊42b，係由身為配線圖案42之一部分並且從絕緣膜53而露出了的部份所構成。焊墊42b和連接墊片41a之間的連接，係經由貫通絕緣基材31所設置的通孔導體43來進行。雖並未特別作限定，但是，焊墊42b，係以包圍連接墊片42a的方式而沿著配線基板30之各邊L31~L34來分別被配列為2列。
如圖1中所示一般，在各焊墊42b之上，係 被設置有貫通密封樹脂72地所設置之由銅等所成的複數之導體柱44。藉由此，導體柱44之其中一端係被與相對應之焊墊42b作連接，導體柱44之另外一端係成為從密封樹脂72而露出了的狀態。於此，導體柱44之另外一端，係與密封樹脂72之表面構成同一平面。在導體柱44 之另外一端處，係被搭載有身為外部電極之焊錫球45。
藉由此種構成，半導體晶片10、20之凸塊電 極12、22，係均為經由導體柱44而被與焊錫球45作電性連接。焊錫球45，係為用以將由本實施形態所致之半導體裝置100與外部之裝置作連接的端子，當將由本實施形態所致之半導體裝置100直接搭載於主機板或模組基板等之上的情況時，係被與設置在主機板或模組基板處之焊墊作連接。又，當使用由本實施形態所致之半導體裝置100而構成具有PoP(Package on Package)構造之半導體裝置的情況時，如同圖7中所示一般，焊錫球45係被連接於設置在其他的封裝80之上面的焊墊81處。
圖7中所示之封裝80，係為使用有硬質之配 線基板82的封裝，其表面係被由抗焊劑所成之絕緣膜89所覆蓋。在配線基板82之其中一方的表面上，係被覆晶安裝有半導體晶片84，在配線基板82之另外一方的表面上，係被設置有焊錫球83。又，在配線基板82之其中一方的表面上係被設置有焊墊81，由本實施形態所致之半導體裝置100的焊錫球45係被與此焊墊81作連接。
半導體晶片84之凸塊電極84a，係被與連接 墊片85作連接，並經由未圖示之配線圖案而被與焊墊81作連接，且經由通孔導體86以及焊墊87而被與焊錫球83作連接。在半導體晶片84和配線基板82之間，係被填充有底部填充材88。
在圖7所示之具備有PoP構造的半導體裝置 中，由於係於封裝80之表面上被設置有其他的半導體晶片84等，因此在應搭載半導體裝置100之表面上係存在有凹凸。當將半導體裝置100搭載於此種存在有凹凸之表面上的情況時，係有必要對於密封樹脂72之表面和焊錫球45之前端間的高度差、亦即是對於所謂的腳高作充分的確保，但是，在由本實施形態所致之半導體裝置100中，由於導體柱44之另外一端和密封樹脂72之表面係構成同一平面，並在導體柱44之該另外一端處設置有焊錫球45，因此係能夠確保充分的腳高。藉由此，係成為能夠容易地得到圖7中所示一般之PoP構造。
又，由於係並不需要如同專利文獻1一般地 為了擴大腳高而將焊錫球45之尺寸大型化，因此係成為亦能夠將多數之焊錫球45以窄節距來作配列。進而，由於係並不會如同專利文獻2一般地而使導體柱44突出，因此也不會有使腳高成為過剩的情況。
並且，由本實施形態所致之半導體裝置100， 由於配線基板30之其中一面32係被密封樹脂71所覆蓋，且另外一面33係被密封樹脂72所覆蓋，因此從配線基板30所見之上下構造係成為略對稱。藉由此，係亦能夠得到難以發生起因於溫度變化所導致的半導體裝置100之彎曲的效果。
進而，在本實施形態中，由於係將半導體晶 片10、20在配線基板30上而相互錯開90°地作搭載，因此，關於半導體晶片10之凸塊電極12，係能夠對於圖2 中所示之區域A的焊錫球45而以短距離來作連接，關於半導體晶片20之凸塊電極22，係能夠對於圖3中所示之區域B的焊錫球45而以短距離來作連接。藉由此，由於係能夠使將半導體晶片10與焊錫球45作連接之配線距離和使將半導體晶片20與焊錫球45作連接之配線距離設為略等長，因此係成為能夠得到高的訊號品質。並且，由於配線圖案係並不會集中於配線基板30上之特定場所處，因此佈局之自由度係提高，並且亦成為能夠將製造良率提高。
接著，針對由本實施形態所致之半導體裝置100的製造方法作說明。
圖8~圖14，係為用以對於由本實施形態所致的半導體裝置100之製造方法作說明的工程圖。
首先，如同圖8中所示一般，準備在其中一面32上被設置有配線圖案41以及絕緣膜51、52，並在另外一面33上被設置有配線圖案42以及絕緣膜53(以及未圖示之絕緣膜54)的絕緣基材31之母材31X。被附加於母材31X上之元件符號D，係為切割線。如同上述一般，由於絕緣基材31係為在玻璃織材等之芯材中而含浸有環氧樹脂等所成的硬質之基板，因此係能夠並不使用其他之支持基板等的來進行處理。於此，於絕緣膜51、52處，係預先形成有使身為配線圖案41之一部分的連接墊片41a露出之開口部，於絕緣膜53、54處，係預先形成有使身為配線圖案42之一部分的連接墊片42a以及焊墊 42b露出之開口部。
接著，形成被與焊墊42b作了連接的複數之 導體柱44。針對導體柱44之形成方法，雖並未特別限定，但是，係以使用電解電鍍法為理想。作為其中一例，係可先在絕緣膜53、54上形成厚的阻劑遮罩，之後，藉由在相當於焊墊42b之場所處形成通孔而使焊墊42b露出，再對於露出了的焊墊42b施加電解電鍍，藉由此而形成導體柱44。
接著，如圖9中所示一般，以使連接墊片42a 與凸塊電極22相接合的方式，而將半導體晶片20覆晶安裝於絕緣基材31之另外一面33上。但是，若是預先在連接墊片42a處設置有突起部，則係並不需要在半導體晶片20處形成凸塊電極22。在安裝了半導體晶片20之後，對於半導體晶片20之主面和絕緣膜54之間的空隙供給底部填充材62，而將該空隙密封。另外，代替底部填充材62，係亦可使用NCF(Non-Conductive Film)或NCP(Non-Conductive Paste)。
接著，如圖10中所示一般，以使連接墊片 41a與凸塊電極12相接合的方式，而將半導體晶片10覆晶安裝於絕緣基材31之其中一面32上。但是，若是預先在連接墊片41a處設置有突起部，則係並不需要在半導體晶片10處形成凸塊電極12。在安裝了半導體晶片10之後，對於半導體晶片10之主面和絕緣膜52之間的空隙供給底部填充材61，而將該空隙密封。於此，亦同樣的， 代替底部填充材61，係亦可使用NCF或NCP。
圖15(a)~(c)，係為用以對於在絕緣基 材31之其中一面32上而將半導體晶片10作覆晶安裝之方法作說明的圖。
首先，如圖15(a)中所示一般，將被安裝有 半導體晶片20之絕緣基材31載置在平台90上。於平台90上，係被設置有用以防止半導體晶片20以及導體柱44之間的干涉之空腔91、92。接著，如圖15(b)中所示一般，藉由接合工具來將半導體晶片10從背面側而拾起，並將半導體晶片10之凸塊電極12對於絕緣基材31上之連接墊片41a而作定位。於接合工具93處，係被設置有用以吸附半導體晶片10之吸引噴嘴94，藉由此，係能夠從背面側來保持半導體晶片10。在本例中，於此時間點處，在半導體晶片10之其中一面上係被貼附有NCF(61)。
之後，如圖15(c)中所示一般，藉由使接合 工具93降下，而使半導體晶片10之凸塊電極12與連接墊片41a作接觸，並藉由在此狀態下而施加荷重以及超音波，來將凸塊電極12和連接墊片41a相接合。此時，被施加在配線基板30上之荷重，係集中於半導體晶片10之與凸塊電極12相對應的位置處。然而，在本實施形態中，荷重所集中之位置的背面、亦即是與凸塊電極12相對應之位置的背面，由於係藉由平台90而被作支持，因此係並不會有起因於荷重之施加而導致配線基板30變形 或者是導致背面之半導體晶片20破損的情形。此係因為，半導體晶片10、20之平面形狀係為長方形，並沿著其之短邊而配置有凸塊電極12、22，且半導體晶片10和半導體晶片20之搭載方向係相互錯開90°之故。藉由此，由於係能夠以良好之條件來安裝半導體晶片10，因此係成為能夠提高半導體裝置100之信賴性。
接著，如圖11中所示一般，以使半導體晶片 10、20以及導體柱44被埋入的方式，而將配線基板30之兩面藉由密封樹脂71、72來密封。密封樹脂71、72之形成，係可同時進行。之後，如圖12中所示一般，對於密封樹脂72之表面進行研削，直到導體柱44之前端44a露出為止。藉由此，導體柱44之端部和密封樹脂72之表面，係成為構成同一平面。在本實施形態中，由於導體柱44之高度係被設計為較半導體晶片20而更高，因此係並不會有起因於在對於密封樹脂72之研削中所產生的銅等之研削屑而導致半導體晶片20之背面被污染的情形。
之後，如圖13中所示一般，在導體柱44之 端部處搭載焊錫球45，之後，若是如圖14中所示一般，藉由沿著切割線D來將母材31X以及密封樹脂71、72切斷而進行個片化，則係完成由本實施形態所致之半導體裝置100。另外，焊錫球45之搭載，若是接續於藉由對於密封樹脂72之研削來使導體柱44作了露出之後而立即進行，則係能夠防止起因於導體柱44之前端44a之氧化所導致的連接不良。
如此這般，在由本實施形態所致之半導體裝 置100的製造工程中，由於係對於密封樹脂72進行研削直到導體柱44之前端44a露出為止，因此係成為能夠將全體之厚度減薄。並且，由於係將沿著短邊而被配置有凸塊電極12、22之半導體晶片10、20相互錯開90°之角度地而作安裝，因此係不會有使配線基板30產生變形等的情況，而成為能夠以良好之條件來進行半導體晶片10、20之安裝。
另外，半導體裝置100之製造工程，係並不 被限定於上述之工程順序，而亦可將一部分之工程的順序作交換。例如，亦可在經過了圖8以及圖9中所示的工程之後，如同圖16中所示一般地而先形成密封樹脂72，之後再如同圖17中所示一般地而安裝半導體晶片10。之後，只要形成覆蓋半導體晶片10之密封樹脂71，則係能夠得到圖11中所示之構造。若依據此方法，則由於密封樹脂71、72係相互藉由不同的工程來形成，因此係能夠選擇互為相異之材料。例如，由於在配線基板30之另外一面33處係存在有導體柱44，因此若是密封樹脂71、72之材料為相同，則密封樹脂71之硬化收縮相較於密封樹脂72之硬化收縮係會變大，而會有在配線基板30處產生彎曲的可能性。若是對於此事作考慮，並作為密封樹脂72之材料而選擇線膨脹係數為較密封樹脂71之材料更大的材料，則係成為能夠對於伴隨著硬化收縮所導致的配線基板30之彎曲作抑制。
接著，針對本發明之第2實施形態作說明。
圖18，係為對於由本發明之第2實施形態所致的半導體裝置200之構成作展示的剖面圖。
如圖18中所示一般，由本實施形態所致之半導體裝置200，其半導體晶片10之背面10a係從密封樹脂71而露出，在此點上，係與由第1實施形態所致之半導體裝置100相異。針對其他構成，由於係與由第1實施形態所致之半導體裝置100相同，因此，對於相同之要素，係附加相同之符號，並省略重複之說明。
在由本實施形態所致之半導體裝置200中，亦同樣的，係能夠得到與由第1實施形態所致之半導體裝置100相同的效果，並且係能夠將全體之厚度更加減薄。又，由於係能夠將易於發生硬化收縮之密封樹脂71的厚度設為較密封樹脂72而更薄，因此係亦能夠防止起因於硬化收縮之差異而導致的配線基板30之彎曲。
由本實施形態所致之半導體裝置200，係能夠藉由在經過了圖11中所示之工程之後，對於密封樹脂71之表面進行研削直到半導體晶片10之背面10a露出為止，而製作出來。由於在密封樹脂71中係並未被埋設有導體柱，因此在對於密封樹脂71之表面進行研削時係並不會有產生銅等之研削屑的情形。故而，半導體晶片10之背面10a係並不會有被銅等之研削屑所污染的情況。
以上，雖針對本發明之理想實施形態作了說明，但是本發明係並不限定於上述之實施形態，不用說， 在不脫離本發明之主旨的範圍內，係可進行各種之變更，且該些亦係為被包含於本發明之範圍內。
例如，在第1以及第2實施形態中，雖係使 用有由硬質之絕緣基材31所成的配線基板30，但是，代替硬質之絕緣基材，係亦可使用由聚醯亞胺等所成之可撓性的絕緣基材。進而，係亦可對於並未使用有絕緣基材之具有RDL(Re-Distribution Layer)構造的半導體裝置而適用本發明。
又，在圖8~圖14所示之製造工程中，雖係 將被形成有導體柱44之配線基板30藉由密封樹脂72而作覆蓋，但是，亦可在將並未被形成有導體柱之配線基板30藉由密封樹脂72來作了覆蓋之後，藉由雷射照射等而於密封樹脂72處形成貫通孔，並藉由將焊錫等之導體導入至此貫通孔內，來形成導體柱44。
10、20‧‧‧半導體晶片
11、21‧‧‧墊片電極
12、22‧‧‧凸塊電極
13、23‧‧‧焊錫層
30‧‧‧配線基板
31‧‧‧絕緣基材
32‧‧‧其中一面
33‧‧‧另外一面
41‧‧‧配線圖案
41a、42a‧‧‧連接墊片
42b‧‧‧焊墊
43‧‧‧通孔導體
44‧‧‧導體柱
45‧‧‧焊錫球
51、52、53‧‧‧絕緣膜
61、62‧‧‧底部填充材
71、72‧‧‧密封樹脂
100‧‧‧半導體裝置

Claims (15)

  1. 一種半導體裝置，其特徵為，係包含有：配線基板，係具備被形成於其中一面上之複數的第1連接墊片、和被形成為另外一面上之複數的第2連接墊片、以及被配置於前述另外一面上並被與前述第1或第2連接墊片作了電性連接之複數的焊墊；和第1半導體晶片，係具備藉由相互對向之第1以及第2端部和相互對向之第3以及第4端部所區劃出之其中一面、和沿著前述其中一面之前述第1以及第2端部的各者而被作了配置的複數之第1凸塊電極，並以使前述複數之第1凸塊電極被與前述複數之第1連接墊片作連接的方式，而被搭載於前述配線基板之前述其中一面上；和第1密封樹脂，係以覆蓋前述第1半導體晶片的方式而被形成於前述配線基板之前述其中一面上；和第2半導體晶片，係具備藉由相互對向之第1以及第2端部和相互對向之第3以及第4端部所區劃出之其中一面、和沿著前述其中一面之前述第1以及第2端部的各者而被作了配置的複數之第2凸塊電極，並以使前述複數之第2凸塊電極被與前述複數之第2連接墊片作連接且使前述第2半導體晶片之前述第1以及第2端部分別與前述第1半導體晶片之前述第3以及第4端部相互平行地來作配置的方式，而被搭載於前述配線基板之前述另外一面上；和第2密封樹脂，係以覆蓋前述第2半導體晶片的方式 而被形成於前述配線基板之前述另外一面上；和複數之導體柱，係貫通前述第2密封樹脂地而被設置，並使其中一端與分別所對應之前述複數之焊墊的其中一者作連接，且使另外一端從前述第2密封樹脂而作了露出；和複數之焊錫球，係被搭載於前述複數之導體柱的前述另外一端處。
  2. 如申請專利範圍第1項所記載之半導體裝置，其中，前述第1半導體晶片之其中一面，係為將前述第1以及第2端部作為短邊並將前述第3以及第4端部作為長邊之矩形狀，前述第2半導體晶片之其中一面，係為將前述第1以及第2端部作為短邊並將前述第3以及第4端部作為長邊之矩形狀。
  3. 如申請專利範圍第1項所記載之半導體裝置，其中，前述複數之墊片，係以將前述複數之第2連接墊片作包圍的方式，而被配置在前述配線基板之前述另外一面的周邊近旁處。
  4. 如申請專利範圍第1項所記載之半導體裝置，其中，前述第1以及第2半導體晶片，係為相互具備有相同之構成的半導體晶片。
  5. 如申請專利範圍第1項所記載之半導體裝置，其中，前述複數之導體柱的前述另外一端和前述第2密封樹 脂之表面，係構成同一平面。
  6. 如申請專利範圍第1項所記載之半導體裝置，其中，前述配線基板，係更進而具備有複數之第1以及第2配線圖案、和將前述複數之第1以及第2配線圖案的一部分作覆蓋之絕緣膜，前述複數之第1連接墊片，係由前述複數之第1配線圖案中的並未被前述絕緣膜而覆蓋之部分所成，前述複數之第2連接墊片，係由前述複數之第2配線圖案中的並未被前述絕緣膜而覆蓋之部分所成。
  7. 如申請專利範圍第6項所記載之半導體裝置，其中，前述絕緣膜，係包含將前述複數之第1配線圖案的一部分作覆蓋之第1以及第2絕緣膜，前述第1絕緣膜，係被配置在前述配線基板之前述其中一面和前述第1密封樹脂之間，前述第2絕緣膜，係被配置在前述配線基板之前述其中一面和前述第1半導體晶片之前述其中一面之間，前述第2絕緣膜，其膜厚係較前述第1絕緣膜更薄。
  8. 如申請專利範圍第6項所記載之半導體裝置，其中，前述絕緣膜，係包含將前述複數之第2配線圖案的一部分作覆蓋之第3以及第4絕緣膜，前述第3絕緣膜，係被配置在前述配線基板之前述另 外一面和前述第2密封樹脂之間，前述第4絕緣膜，係被配置在前述配線基板之前述另外一面和前述第2半導體晶片之前述其中一面之間，前述第4絕緣膜，其膜厚係較前述第3絕緣膜更薄。
  9. 如申請專利範圍第1項所記載之半導體裝置，其中，前述第1半導體晶片之位置於與前述其中一面相反側處的背面，係並未被前述第1密封樹脂所覆蓋地而露出。
  10. 如申請專利範圍第1~9項中之任一項所記載之半導體裝置，其中，前述第1密封樹脂和前述第2密封樹脂，係由互為相異之材料所成。
  11. 如申請專利範圍第10項所記載之半導體裝置，其中，前述第1密封樹脂和前述第2密封樹脂，其線膨脹係數係互為相異。
  12. 一種半導體裝置之製造方法，其特徵為，係具備有：在配線基板之其中一面上，形成複數的第1連接墊片，並在前述配線基板之另外一面上，形成複數的第2連接墊片、和被與前述第1或第2連接墊片作了電性連接之複數的焊墊、以及使其中一端分別與相對應之前述複數之墊片的其中一者作了連接的複數之導體柱之工程；和將具備藉由相互對向之第1以及第2端部和相互對向之第3以及第4端部所區劃出之其中一面與沿著前述其中一面之前述第1以及第2端部的各者而被作了配置的複數之第1凸塊電極的第1半導體晶片，以使前述複數之第1 凸塊電極被與前述複數之第1連接墊片作連接的方式，而搭載於前述配線基板之前述其中一面上之工程；和將具備藉由相互對向之第1以及第2端部和相互對向之第3以及第4端部所區劃出之其中一面與沿著前述其中一面之前述第1以及第2端部的各者而被作了配置的複數之第2凸塊電極的第2半導體晶片，以使前述複數之第2凸塊電極被與前述複數之第2連接墊片作連接且使前述第2半導體晶片之前述第1以及第2端部分別與前述第1半導體晶片之前述第3以及第4端部相互平行地來作配置的方式，而搭載於前述配線基板之前述另外一面上之工程；和以覆蓋前述第1以及第2半導體晶片的方式，而於前述配線基板之前述其中一面以及另外一面上分別形成第1以及第2密封樹脂之工程；和以使前述複數之導體柱的另外一端露出的方式，來對於前述第2密封樹脂進行研削之工程；和在前述複數之導體柱的前述另外一端處而搭載複數之焊錫球之工程。
  13. 如申請專利範圍第12項所記載之半導體裝置之製造方法，其中，係同時地形成前述第1以及第2密封樹脂。
  14. 如申請專利範圍第12項所記載之半導體裝置之製造方法，其中，係在形成了覆蓋前述第2半導體晶片之前述第2密封樹脂之後，在前述配線基板之前述其中一面 上搭載前述第1半導體晶片。
  15. 如申請專利範圍第12~14項中之任一項所記載之半導體裝置之製造方法，其中，係更進而具備有：以使前述第1半導體晶片之背面露出的方式，而對於前述第1密封樹脂進行研削之工程。
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Cited By (2)

* Cited by examiner, † Cited by third party
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TWI603407B (zh) * 2015-04-28 2017-10-21 精材科技股份有限公司 晶片封裝體及其製造方法
US11024757B2 (en) 2016-01-15 2021-06-01 Sony Corporation Semiconductor device and imaging apparatus

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6586629B2 (ja) * 2014-04-17 2019-10-09 パナソニックＩｐマネジメント株式会社 半導体パッケージ及び半導体装置
US10096573B2 (en) * 2015-07-28 2018-10-09 Bridge Semiconductor Corporation Face-to-face semiconductor assembly having semiconductor device in dielectric recess
US10304800B2 (en) * 2017-06-23 2019-05-28 Taiwan Semiconductor Manufacturing Company Ltd. Packaging with substrates connected by conductive bumps
JP7087325B2 (ja) 2017-09-29 2022-06-21 ブラザー工業株式会社 電子デバイス
US10527896B2 (en) * 2017-12-08 2020-01-07 L3 Technologies, Inc. Chip on glass protection
TWI733056B (zh) * 2018-09-19 2021-07-11 矽品精密工業股份有限公司 電子封裝件及其製法
US11558508B1 (en) * 2021-06-30 2023-01-17 Jpmorgan Chase Bank, N.A. Method and system for real time reporting of metrics to fungible agents in omnichannel contact center

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3223835B2 (ja) * 1997-03-28 2001-10-29 三菱電機株式会社 パワー半導体装置及びその製造方法
JP2001332681A (ja) * 2000-05-18 2001-11-30 Fujitsu Ltd 半導体装置
JP4865197B2 (ja) * 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP4952353B2 (ja) * 2007-04-18 2012-06-13 パナソニック株式会社 チップモジュールおよびメモリカード
WO2013035716A1 (ja) * 2011-09-07 2013-03-14 株式会社村田製作所 モジュールの製造方法
DE112013004495T5 (de) * 2012-09-14 2015-06-11 Ps5 Luxco S.A.R.L. Halbleiterbauelement und Verfahren zum Herstellen eines Halbleiterbauelements
JP2014082302A (ja) * 2012-10-16 2014-05-08 Ps4 Luxco S A R L 半導体装置
JP2014096547A (ja) * 2012-11-12 2014-05-22 Ps4 Luxco S A R L 半導体装置及びその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI603407B (zh) * 2015-04-28 2017-10-21 精材科技股份有限公司 晶片封裝體及其製造方法
US9831185B2 (en) 2015-04-28 2017-11-28 Xintec Inc. Chip package and fabrication method thereof
US11024757B2 (en) 2016-01-15 2021-06-01 Sony Corporation Semiconductor device and imaging apparatus
US11728447B2 (en) 2016-01-15 2023-08-15 Sony Group Corporation Semiconductor device and imaging apparatus

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