JP6586629B2 - 半導体パッケージ及び半導体装置 - Google Patents
半導体パッケージ及び半導体装置 Download PDFInfo
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Description
図1Aは、第1の実施形態の半導体パッケージ1の構造例(第1の表層7)を示す平面図である。図1Bは、第1の実施形態の半導体パッケージ1の構造例(第2の表層8)を示す平面図である。半導体パッケージ1は、第1の表層7及び第2の表層8が両面に形成された基板3(例えば樹脂基板)を有する。図1Aは、外部基板9(図3A参照)と対向する側の第1の表層7を示す。図1Bは、第1の表層7と反対側の基板3の、RFIC4(図3A参照)が実装される第2の表層8を示す。基板3は、第1の基板の一例であり、外部基板9は、第2の基板の一例である。
半導体装置では、BBICを実装する場合、半田ボールの大きさをBBICの高さ(BBICの厚み(高さ)とBBICのバンプとの合計値)より大きくする必要があった。このため、外部基板接続用のパッド領域における各パッドの間隔(パッド間隔)は、半田ボールの大きさに依存するので、パッド間隔を十分に狭くすることが困難であった。パッド間隔が広い場合、パッド数が少なくなり、BBICの機能や対応する外部インターフェースの種類が制限されることがあった。
本開示の第1の半導体パッケージは、
第1のIC(Integrated Circuit)に接続するための複数の第1パッドを含む第1のパッド領域と、第2の基板に接続するための複数の第2パッドを含む第2のパッド領域と、が形成された第1の表層と、
前記第1の表層と反対側に形成され、第2のICに接続するための複数の第3パッドを含む第3のパッド領域が形成された第2の表層と、
を含む第1の基板を備え、
前記複数の第2パッドは、前記第1のパッド領域の周りを少なくとも3列で囲み、
前記複数の第2パッドのうち、内周部に配置された1つ以上のパッドは、前記複数の第1パッドのうち1つ以上のパッドと、前記複数の第3パッドのうち1つ以上のパッドとの両方に接続されており、
前記複数の第2パッドのうち、外周部に配置された1つ以上のパッドは、前記複数の第1パッドのうち1つ以上のパッドと接続され、前記複数の第3パッドとは接続されておらず、
前記複数の第2パッドのうち、中間部に配置された1つ以上のパッドは、前記複数の第3パッドのうち1つ以上のパッドと接続され、前記複数の第1パッドとは接続されておらず、
前記第3のパッド領域に前記第2のICが実装され、前記第1のパッド領域に前記第1のICが実装されている場合、
前記複数の第2パッドのうち、前記外周部に配置された1つ以上のパッドと、前記中間部に配置された1つ以上のパッドを用いて、前記第2の基板と接続し、
前記第3のパッド領域に前記第2のICが実装され、前記第1のパッド領域に前記第1のICが実装されていない場合、
前記複数の第2パッドのうち、前記内周部に配置された1つ以上のパッドと、前記中間部に配置された1つ以上のパッドと、を用いて、前記第2の基板と接続される。
第1の半導体パッケージと、
前記第1のパッド領域に実装された第1のICと、
前記第3のパッド領域に実装された第2のICと、
前記第2の基板と、
前記第2のパッド領域の中間部及び外周部に配置された1つ以上のパッドと、前記第2の基板と、を接続する1つ以上の導電性部材と、
を備える。
更に、前記第2のパッド領域と前記第2の基板との間に配置された第3の基板を備え、
前記導電性部材は、前記第2のパッド領域の中間部及び外周部に配置された1つ以上のパッドと、前記第3の基板と、を接続する1つ以上の第1の導電性部材と、前記第3の基板と前記第2の基板とを接続する1つ以上の第2の導電性部材と、を備える。
第1の半導体パッケージと、
前記第3のパッド領域に実装された第2のICと、
前記第2の基板と、
前記第2のパッド領域の内周部及び中間部に配置された1つ以上のパッドと、前記第2の基板と、を接続する1つ以上の導電性部材と、
を備える。
3 基板
4 RFIC
5,5A BBIC
7 第1の表層
8 第2の表層
9 外部基板
9a,10A,11A,11B,11C,12A パッド
10 第1のパッド領域
11 第2のパッド領域
12 第3のパッド領域
20,20A 半導体装置
21A,21B,21C 線路
22,22A,22B 半田ボール
24 バンプ
31 キャビティ基板
Claims (4)
- 第1のIC(Integrated Circuit)に接続するための複数の第1パッドを含む第1のパッド領域と、第2の基板に接続するための複数の第2パッドを含む第2のパッド領域と、が形成された第1の表層と、
前記第1の表層と反対側に形成され、第2のICに接続するための複数の第3パッドを含む第3のパッド領域が形成された第2の表層と、
を含む第1の基板を備え、
前記複数の第2パッドは、前記第1のパッド領域の周りを少なくとも3列で囲み、
前記複数の第2パッドのうち、内周部に配置された1つ以上のパッドは、前記複数の第1パッドのうち1つ以上のパッドと、前記複数の第3パッドのうち1つ以上のパッドとの両方に接続されており、
前記複数の第2パッドのうち、外周部に配置された1つ以上のパッドは、前記複数の第1パッドのうち1つ以上のパッドと接続され、前記複数の第3パッドとは接続されておらず、
前記複数の第2パッドのうち、中間部に配置された1つ以上のパッドは、前記複数の第3パッドのうち1つ以上のパッドと接続され、前記複数の第1パッドとは接続されておらず、
前記第3のパッド領域に前記第2のICが実装され、前記第1のパッド領域に前記第1のICが実装されている場合、
前記複数の第2パッドのうち、前記外周部に配置された1つ以上のパッドと、前記中間部に配置された1つ以上のパッドを用いて、前記第2の基板と接続し、
前記第3のパッド領域に前記第2のICが実装され、前記第1のパッド領域に前記第1のICが実装されていない場合、
前記複数の第2パッドのうち、前記内周部に配置された1つ以上のパッドと、前記中間部に配置された1つ以上のパッドと、を用いて、前記第2の基板と接続する、
半導体パッケージ。 - 請求項1に記載の半導体パッケージと、
前記第2のパッド領域と前記第2の基板との間に配置された第3の基板を備え、
前記第2のパッド領域と前記第3の基板とは、導電性部材を用いて接続され、
前記第2の基板と前記第3の基板とは、前記導電性部材を用いて接続される、
半導体装置。 - 前記第1のICは、ベースバンド信号を出力するICであり、
前記第2のICは、無線信号を出力するICであり、
前記第2のパッド領域と前記第2の基板とは、導電性部材を用いて接続された、
請求項1に記載の半導体パッケージ。 - 請求項1に記載の半導体パッケージと、
前記第2のパッド領域と前記第2の基板との間に配置された第3の基板と、
を備え、
前記第2のパッド領域と前記第3の基板とは、導電性部材を用いて接続され、
前記第2の基板と前記第3の基板とは、前記導電性部材を用いて接続される、
半導体装置。
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US14/680,039 US9293419B2 (en) | 2014-04-17 | 2015-04-06 | Semiconductor package and semiconductor device |
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JP2001203318A (ja) * | 1999-12-17 | 2001-07-27 | Texas Instr Inc <Ti> | 複数のフリップチップを備えた半導体アセンブリ |
JP2001339043A (ja) * | 2000-05-30 | 2001-12-07 | Mitsubishi Electric Corp | 半導体装置及びそれを用いた半導体モジュール |
JP2002314034A (ja) * | 2001-04-18 | 2002-10-25 | Mitsubishi Electric Corp | 半導体装置 |
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US7122904B2 (en) * | 2002-04-25 | 2006-10-17 | Macronix International Co., Ltd. | Semiconductor packaging device and manufacture thereof |
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JP4986738B2 (ja) | 2007-06-27 | 2012-07-25 | 新光電気工業株式会社 | 半導体パッケージおよびこれを用いた半導体装置 |
JP4571679B2 (ja) * | 2008-01-18 | 2010-10-27 | Okiセミコンダクタ株式会社 | 半導体装置 |
JP2009278064A (ja) | 2008-04-17 | 2009-11-26 | Panasonic Corp | 半導体装置とその製造方法 |
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