TW201503299A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW201503299A
TW201503299A TW103116430A TW103116430A TW201503299A TW 201503299 A TW201503299 A TW 201503299A TW 103116430 A TW103116430 A TW 103116430A TW 103116430 A TW103116430 A TW 103116430A TW 201503299 A TW201503299 A TW 201503299A
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Taiwan
Prior art keywords
wafer
semiconductor wafer
semiconductor device
semiconductor
pad
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TW103116430A
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English (en)
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TWI620283B (zh
Inventor
谷藤雄一
岡浩偉
奧西敕子
高田圭太
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瑞薩電子股份有限公司
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Publication of TW201503299A publication Critical patent/TW201503299A/zh
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Publication of TWI620283B publication Critical patent/TWI620283B/zh

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    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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Abstract

本發明之一實施形態之半導體裝置係由樹脂密封搭載於晶片搭載部上之半導體晶片之半導體裝置，且於沿第1方向之上述半導體晶片之周緣部與上述晶片搭載部之周緣部之間的晶片搭載面側，固定有第1構件。又，上述第1構件被上述樹脂密封。又，於俯視下，上述第1方向上之上述晶片搭載部之上述第1部分之長度，長於上述第1方向上之上述半導體晶片之長度。

Description

半導體裝置
本發明係關於一種半導體裝置之技術，例如關於一種應用於在平面面積大於半導體晶片之安裝面之晶片焊墊上搭載半導體晶片之半導體裝置而有效之技術。
於日本專利特開2010-2245417號公報(專利文獻1)、日本專利特開2006-310397號公報(專利文獻2)、日本專利特開2006-140265號公報(專利文獻3)、日本專利特開2004-349497號公報(專利文獻4)、或日本專利特開2000-68303號公報(專利文獻5)中，記載有於樹脂密封型之半導體封裝中，使晶片焊墊之與密封體之密接面粗面化。
[先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開2010-2245417號公報
[專利文獻2]日本專利特開2006-310397號公報
[專利文獻3]日本專利特開2006-140265號公報
[專利文獻4]日本專利特開2004-349497號公報
[專利文獻5]日本專利特開2000-68303號公報
本案發明者對使半導體裝置之性能提高之技術進行研究，該半導體裝置係將半導體晶片搭載於晶片焊墊上且以樹脂密封而成。其結 果，本案發明者發現，若藉由使半導體晶片之平面尺寸小型化而使晶片焊墊之未搭載半導體晶片之區域之面積變大，則半導體晶片與晶片焊墊之接著面變得易損傷。
其他課題與新穎之特徵根據本說明書之記述及隨附圖式而得以明確。
一實施形態之半導體裝置係於俯視下在半導體晶片之周緣部與晶片焊墊之周緣部之間的晶片搭載面側固定有第1構件者。
根據上述一實施形態，可抑制半導體晶片與晶片焊墊之接著面之損傷。
20‧‧‧金屬帶
20a‧‧‧壓痕
21‧‧‧捲盤
23‧‧‧接合工具
24‧‧‧切割刀
25‧‧‧支持台
25a‧‧‧突出部保持面
25b‧‧‧帶連接部保持面
26‧‧‧接合工具
27‧‧‧導線
28‧‧‧帶導引件
31‧‧‧成形模具
32‧‧‧上模具(第1模具)
33‧‧‧下模具(第2模具)
34‧‧‧腔室
BP1‧‧‧晶片接合材(接著材)
BP2‧‧‧晶片接合材(接著材)
CH‧‧‧通道形成區域
CM1‧‧‧金屬膜(鍍膜、鍍金屬膜)
CM2‧‧‧金屬膜(鍍膜、鍍金屬膜)
D‧‧‧汲極
DE‧‧‧汲極電極
DP‧‧‧晶片焊墊(晶片搭載部)
DP1‧‧‧部分
DP2‧‧‧部分
DPb‧‧‧下表面(主面)
DPs1‧‧‧側面
DPs2‧‧‧側面
DPs3‧‧‧側面
DPs4‧‧‧側面
DPt‧‧‧上表面(主面)
EP‧‧‧磊晶層
G‧‧‧閘極電極
GE‧‧‧閘極電極焊墊
GI‧‧‧閘極絕緣膜
L1‧‧‧長度(距離)
L2‧‧‧長度(距離)
L3‧‧‧長度(距離)
Lc1‧‧‧長度(距離)
Lc2‧‧‧長度
LD‧‧‧引線(端子、外部端子)
LDb‧‧‧下表面(安裝面)
LDd‧‧‧引線(汲極引線、汲極端子)
LDg‧‧‧引線(閘極引線、閘極端子)
LDs‧‧‧引線(源極引線、源極端子)
LDt‧‧‧上表面
LF‧‧‧引線框架
LFa‧‧‧器件形成部
LFb‧‧‧外框
LFc‧‧‧框架部
Lps1‧‧‧長度
MB1‧‧‧金屬帶(導電性構件、金屬箔、帶狀金屬構件)
MB2‧‧‧金屬夾具(導電性構件、金屬板)
MR‧‧‧密封體(樹脂體)
MRb‧‧‧下表面(安裝面)
MRs‧‧‧側面
MRt‧‧‧上表面
MW1‧‧‧導線(金屬導線)
NZ1‧‧‧噴嘴
NZ2‧‧‧噴嘴
P1‧‧‧分離距離
P2‧‧‧分離距離
PK1‧‧‧半導體裝置
PK2‧‧‧半導體裝置
PK3‧‧‧半導體裝置
PK6‧‧‧半導體裝置
PK7‧‧‧半導體裝置
PK8‧‧‧半導體裝置
PKh1‧‧‧半導體裝置
PS1‧‧‧構件
PS2‧‧‧構件
PS3‧‧‧構件
PS3t‧‧‧上表面
PS4‧‧‧構件
PS5‧‧‧構件
Psb‧‧‧搭載面
Q1‧‧‧電晶體
RB1‧‧‧連接部(帶連接部)
RB2‧‧‧連接部(導線連接部)
RBb‧‧‧下表面
RBt‧‧‧上表面(連接面、帶連接面、導線連接面)
S‧‧‧源極
SC‧‧‧半導體晶片
SC1‧‧‧半導體晶片
SC2‧‧‧半導體晶片
SCb‧‧‧背面
SCs1‧‧‧側面
SCs2‧‧‧側面
SCs3‧‧‧側面
SCs4‧‧‧側面
SCt‧‧‧正面(面)
SD‧‧‧金屬膜(外覆鍍膜)
SDp1‧‧‧連接材料
SDp2‧‧‧連接材料
SE‧‧‧源極電極焊墊
SL1‧‧‧偏移部(彎曲加工部、傾斜部、階差部)
SL2‧‧‧偏移部(彎曲加工部、傾斜部、階差部)
SR‧‧‧源極區域
STB1‧‧‧柱狀凸塊
STB2‧‧‧柱狀凸塊
TL‧‧‧懸掛引線
TN1‧‧‧端子部
TN2‧‧‧端子部
TR1‧‧‧溝槽(開口部、槽)
Wa‧‧‧主面
WH‧‧‧半導體基板
圖1係模式性顯示一實施形態之半導體裝置所具備之電路之一例的說明圖。
圖2係顯示圖1所示之場效電晶體之元件構造例之主要部分剖面圖。
圖3係圖1所示之半導體裝置之俯視圖。
圖4係圖3所示之半導體裝置之仰視圖。
圖5係顯示卸除圖3所示之密封體之狀態下之半導體裝置之內部構造的透視俯視圖。
圖6係沿圖5之A-A線之剖面圖。
圖7係沿圖5之B-B線之剖面圖。
圖8係針對圖5之變化例，即顯示於晶片焊墊之未搭載半導體晶片之部分搭載有構件之狀態之主要部分放大俯視圖。
圖9係顯示使用圖1~圖7說明之半導體裝置之製造步驟之概要之說明圖。
圖10係顯示圖9所示之引線框架準備步驟中所準備之配線基板之整體構造的俯視圖。
圖11係圖10所示之1個器件形成部之放大俯視圖。
圖12係沿圖11之A-A線之放大剖面圖。
圖13係顯示於圖11所示之晶片焊墊部之一部分塗佈有銀漿之狀態的放大俯視圖。
圖14係沿圖13之A-A線之放大剖面圖。
圖15係模式性顯示於沿圖13之B-B線之放大剖面塗佈銀漿之方式之說明圖。
圖16係顯示針對圖15之變化例之說明圖。
圖17係顯示藉由圖16所示之方式形成之銀漿之平面形狀之放大俯視圖。
圖18係顯示於圖13所示之晶片焊墊上搭載有半導體晶片之狀態之放大俯視圖。
圖19係沿圖18之A-A線之放大剖面圖。
圖20係顯示將圖18所示之半導體晶片與引線經由金屬帶電性連接之狀態之放大俯視圖。
圖21係顯示於沿圖20之A-A線之剖面，連接金屬帶之狀態之放大剖面圖。
圖22係於沿圖20之A-A線之剖面，繼圖21後之階段性顯示之放大剖面圖。
圖23係顯示將圖20所示之半導體晶片與閘極用引線經由金屬導線電性連接之狀態之放大俯視圖。
圖24係顯示於沿圖23之A-A線之剖面，連接有導線之狀態之放大剖面圖。
圖25係顯示形成有密封圖23所示之半導體晶片及金屬帶之密封 體之狀態的放大俯視圖。
圖26係顯示於沿圖25之A-A線之剖面，在成形模具內配置有引線框架之狀態之放大剖面圖。
圖27係顯示於圖26所示之晶片焊墊及引線之自密封體之露出面形成有金屬膜之狀態之放大剖面圖。
圖28係顯示將圖27所示之引線框架單片化之狀態之放大俯視圖。
圖29係顯示針對圖6之變化例之剖面圖。
圖30係顯示針對圖5之變化例之透視俯視圖。
圖31係沿圖30之A-A線之剖面圖。
圖32係顯示針對圖5之其他變化例之俯視圖。
圖33係沿圖32之A-A線之剖面圖。
圖34係顯示針對圖33之變化例之俯視圖。
圖35係顯示針對圖5之其他變化例之俯視圖。
圖36係沿圖35之A-A線之剖面圖。
圖37係顯示針對圖5之其他變化例之俯視圖。
圖38係沿圖37之A-A線之剖面圖。
圖39係顯示針對圖5之其他變化例之透視俯視圖。
圖40係顯示作為針對圖5之比較例之半導體裝置之內部構造之透視俯視圖。
(本案中之記載形式、基本用語、用法之說明)
於本案中，方便起見，實施態樣之記載視需要分為複數個部分等進行記載，但其等並非彼此獨立之個體，除非特別明示其等為獨立之個體之情形，且不論記述之前後，單一之例之各部分、一者均為另一者之一部分詳情、或一部分或全部之變化例等。又，原則上省略相 同部分之重複說明。又，實施態樣中之各構成要件並非必需，除非特別明示其等為必需之情形、理論上限定其數量之情形及由上下文明確其等為必需之情形。
同樣地於實施形態等之記述中，關於材料、組成等，即使稱為「包含A之X」等，亦不排除包含A以外之要件之情形，除非特別明示排除包含A以外之要件之情形及由上下文明確包含A以外之要件之情形。例如，關於成分係指「包含以A為主要成分之X」等。例如，即便稱為「矽構件」等，亦並不限定為純矽之情形，當然亦包含SiGe(矽-鍺)合金或其他以矽為主要成分之多元合金、及包含其他添加物等之構件。又，即便稱為鍍金、Cu層、鍍鎳等，亦並不僅為純質者，而設為包含分別以金、Cu、鎳等為主要成分之構件，除非特別明示其為純質者之情形。
進而，言及特定數值、數量時，亦可為超過該特定數值之數值或未達該特定數值之數值，除非特別明示出即為該特定數值、數量之情形、理論上限定其數量之情形、及由上下文明確即為該特定數值、數量之情形。
又，於實施形態之各圖中，相同或同樣之部分係以相同或類似之標記或參照編號予以表示，且原則上不重複說明。
又，於隨附圖式中，相反存在於變得複雜之情形或與空隙之區別明確之情形時，即使為剖面亦省略陰影線等的情形。與之相關，於由說明等明確之情形等時，即使為平面上封閉之孔，亦有省略背景之輪廓線之情形。進而，即使並非為剖面，但為了明示其並非為空隙、或為了明示區域之邊界，亦會附註陰影線或點圖案。
<電路構成>
於本實施形態中，作為半導體裝置之例，提出組入電源電路等電力控制電路例如作為開關元件使用之所謂之被稱為功率器件之電力 控制用半導體裝置而進行說明。圖1係模式性顯示本實施形態之半導體裝置所具備之電路之一例的說明圖。又，圖2係顯示圖1所示之場效電晶體之元件構造例之主要部分剖面圖。
被稱為功率器件之電力控制用半導體裝置有具有例如二極體、閘流體、或電晶體等半導體元件者。如圖1所示，本實施形態之半導體裝置PK1具有形成有電晶體Q1之半導體晶片SC。於圖1及圖2所示之例中，形成於半導體晶片SC之電晶體Q1為場效電晶體，詳細而言為MOSFET(Metal Oxide Semiconductor Field Effect Transistor：金氧半場效電晶體)。於功率器件中，電晶體例如作為開關元件而使用。用於功率器件之MOSFET被稱為功率MOSFET。
上述MOSFET係作為泛指於閘極絕緣膜上配置包含導電性材料之閘極電極之構造之場效電晶體之用語而記述。因此，於記述為MOSFET之情形時，亦非將氧化膜以外之閘極絕緣膜除外。又，於記述為MOSFET之情形時，亦非將例如多晶矽等金屬以外之閘極電極材料除外。
又，圖1所示之電晶體Q1例如藉由如圖2所示之n通道型之場效電晶體形成。圖2係顯示圖1所示之場效電晶體之元件構造例之主要部分剖面圖。
於圖2所示之例中，例如於包含n型單晶矽之半導體基板WH之主面Wa上，形成有n-型之磊晶層EP。該半導體基板WH及磊晶層EP構成MOSFET之汲極區域(相當於圖1所示之汲極D之區域)。該汲極區域與形成於半導體晶片SC之背面側之汲極電極DE電性連接。
於磊晶層EP上，形成作為p+型之半導體區域之通道形成區域CH，且於該通道形成區域CH上，形成有作為n+型之半導體區域之源極區域(相當於圖1所示之源極S之區域)SR。源極區域SR經由引出配線而與形成於半導體晶片SC之主面側之源極電極焊墊SE電性連接。 又，於積層於半導體基板WH上之半導體區域，形成有自源極區域SR之上表面貫通通道形成區域CH並到達至磊晶層EP之內部之溝槽(開口部、溝)TR1。
又，於溝槽TR1之內壁形成有閘極絕緣膜GI。又，於閘極絕緣膜GI上形成有以嵌入溝槽TR1之方式積層之閘極電極G。閘極電極G經由引出配線與半導體晶片SC之閘極電極焊墊GE電性連接。
又，電晶體Q1隔著通道形成區域CH於厚度方向上配置汲極區域與源極區域SR，故於厚度方向形成通道(以下稱為縱型通道構造)。該情形時，與沿主面Wa形成通道之場效電晶體相比，可減小俯視下之元件之佔有面積。因此，可減小半導體晶片SC之平面尺寸。
又，於上述縱型通道構造之情形時，因可增加俯視下每單位面積之通道寬，故可降低接通電阻。再者，圖2係顯示場效電晶體之元件構造之圖，於圖1所示之半導體晶片SC中，並列連接有具有例如圖2所示般元件構造之複數個(多個)電晶體Q1。藉此，可構成流通例如超過1安培般之大電流之功率MOSFET。
如上所述，於並列連接縱型通道構造之複數個電晶體Q1而構成MOSFET之情形時，MOSFET之電性特性(主要為耐壓特性、接通電阻特性、電容特性)根據半導體晶片SC之平面尺寸而變化。例如，若增大半導體晶片SC之平面面積，則經並列連接之電晶體Q1之單元數(即元件數量)增加，故接通電阻降低，且電容增大。
<半導體裝置>
其次，說明圖1所示之半導體裝置PK1之封裝構造。圖3係圖1所示之半導體裝置之俯視圖。又，圖4係圖3所示之半導體裝置之仰視圖。又，圖5係顯示卸除圖3所示之密封體之狀態下之半導體裝置之內部構造的透視俯視圖。又，圖6係沿圖5之A-A線之剖面圖。又，圖7係沿圖5之B-B線之剖面圖。
上述MOSFET之電性特性之要求規格根據半導體裝置PK1(參照圖1)之用途而不同。因此，為了對應不同之要求規格，半導體裝置PK1之封裝構造較佳為預先設為能夠搭載平面尺寸不同之複數種半導體晶片SC之構造。另一方面，半導體裝置PK1之端子排列或平面尺寸較佳為無關於半導體晶片SC之平面尺寸而共通化。例如，藉由使半導體晶片SC以外之零件共通化，可提高製造效率。又，例如藉由使端子排列共通化，可使安裝半導體裝置PK1之安裝基板側之端子排列標準化。又，例如，若考慮半導體裝置PK1之散熱特性，則較佳為即便於半導體晶片SC之平面尺寸變小之情形時，亦不使散熱路徑之剖面積變化。
因此，本案發明者對能夠搭載平面尺寸不同之複數種半導體晶片SC之封裝進行研究。以下，使用圖3~圖7說明本實施形態之半導體裝置PK1之構造。
半導體裝置PK1具有半導體晶片SC(參照圖5、圖6)、搭載半導體晶片SC之晶片焊墊(晶片搭載部)DP(參照圖4~圖6)、及作為外部端子之複數條引線(端子)LD(參照圖4~圖6)。又，半導體晶片SC、晶片焊墊DP之上表面DPt及複數條引線之上表面LDt藉由密封體(樹脂體)MR統一密封。
於本實施形態中，如圖5所示，複數條引線LD沿Y方向與晶片焊墊DP並排配置，且沿與Y方向正交之X方向分別並排配置。又，如圖5所示，於俯視下，沿Y方向，源極用引線(源極引線、源極端子)LDs、晶片焊墊DP、汲極用引線(汲極引線、汲極端子)LDd以依序並排之方式排列。又，於圖5所示之例中，閘極用引線(閘極引線、閘極端子)LDg與源極用引線LDs相鄰且配置於汲極用引線LDd之相反側。
如圖6所示，半導體晶片SC具有正面(面、第1面)SCt、及位於正 面SCt之相反側之背面(面、第2面)SCb。又，如圖5所示，半導體晶片SC之正面SCt(或如圖6所示之背面SCb)於俯視下呈四邊形，且於周緣部具有包含側面SCs1、SCs2、SCs3、SCs4之四個側面。於圖5所示之例中，半導體晶片SC於俯視下呈長方形，且長邊沿X方向配置。
半導體晶片SC所具有之四個側面中，構成長邊之側面SCs1配置於源極用引線LDs側。又，構成另一長邊之側面SCs2配置於側面SCs1之相反側即引線LDs之相反側。又，以與各側面SCs1、SCs2交叉之方式配置側面SCs3。又，於側面SCs3之相反側配置側面SCs4。又，如圖5所示，於半導體晶片SC之正面SCt形成有與圖1所示之源極S電性連接之源極電極焊墊SE、及與圖1所示之閘極電極G電性連接之閘極電極焊墊GE。另一方面，如圖6所示，於半導體晶片SC之背面SCb形成有與圖1所示之汲極D電性連接之汲極電極DE。於圖6所示之例中，半導體晶片SC之整個背面SCb成為汲極電極DE。
如圖2所示，於將半導體晶片SC設為縱型通道構造之情形時，藉由使半導體晶片SC之厚度變薄(縮小圖6所示之正面SCt與背面SCb之距離)，可降低接通電阻。因此，較佳為使半導體晶片SC之厚度變薄，雖亦依據接通電阻值之規格上之要求，但半導體晶片SC之厚度較佳為100μm以下。例如，於圖6所示之例中，半導體晶片SC之厚度為50μm左右，且薄於晶片焊墊DP之厚度。
又，如圖5及圖6所示，半導體裝置PK1具有搭載半導體晶片SC之晶片焊墊(晶片搭載部)DP。如圖6所示，晶片焊墊DP具有供半導體晶片SC介隔晶片接合材BP1而搭載之上表面(晶片搭載面、第1主面)DPt、及與上表面DPt為相反之側之下表面(安裝面、第2主面)DPb。又，如圖5所示，晶片焊墊DP之上表面DPt(或圖6所示之背面DPb)於俯視下呈四邊形，且於周緣部具有包含側面DPs1、DPs2、DPs3、DPs4之四個側面。於四個側面中，側面DPs1配置於源極用引 線LDs側。又，側面DPs2配置於側面DPs1之相反側即引線LDs之相反側。又，以與各側面DPs1、DPs2交叉之方式配置側面DPs3。半導體晶片SC之側面SCs3沿晶片焊墊DP之側面DPs3配置。又，於側面SCs3之相反側配置側面SCs4。
又，晶片焊墊DP與作為汲極端子之引線LDd一體地形成。引線LDd係與圖1所示之汲極D電性連接之外部端子。又，如圖6所示，形成於半導體晶片SC之背面SCb之汲極電極DE介隔包含導電性材料之晶片接合材BP1而與晶片焊墊DP電性連接。又，於圖5所示之例中，半導體晶片SC之平面尺寸(正面SCt之面積)小於晶片焊墊DP之平面尺寸(上表面DPt之面積)。
又，如圖4及圖6所示，晶片焊墊DP之下表面DPb於密封體MR之下表面MRb自密封體MR露出。詳細而言，於本實施形態中，預先於晶片焊墊DP之周緣形成階差部，晶片焊墊DP之周緣之階差部被密封體MR密封。因此，晶片焊墊DP之下表面DPb中之一部分自密封體MR露出。藉由如本實施形態般將晶片焊墊DP之平面尺寸增大且使晶片焊墊DP之下表面DPb自密封體露出，可提高半導體晶片SC產生之熱之散熱效率。
又，藉由使作為外部端子即引線LDd之晶片焊墊DP之下表面DPb自密封體MR露出，可增大電流流通之導通路徑之剖面積。因此，可降低導通路徑中之阻抗成分。尤其，於引線LDd成為與半導體裝置PK1具有之電路之輸出節點對應之外部端子之情形時，可藉由降低連接於引線LDd之導通路徑之阻抗成分，而直接降低輸出配線之電力損失，該方面而言較佳。
又，於晶片焊墊DP之露出面即下表面DPb，形成有用以在將半導體裝置PK1安裝於未圖式之安裝基板時提高成為接合材之焊接材之潤濕性之金屬膜(外覆鍍膜)SD。於將半導體裝置PK1安裝於未圖示之安 裝基板(母板)時，作為電性連接半導體裝置PK1之複數條引線LD與安裝基板側之未圖示之端子之接合材，例如使用焊接材等。自提高作為接合材之焊接材之潤濕性之觀點而言，圖5及圖6所示之例如包含焊料之外覆鍍膜即金屬膜SD分別形成於半導體裝置PK1之端子之接合面。
又，藉由於晶片焊墊DP之周緣部形成階差部且密封階差部，晶片焊墊DP變得不易自密封體MR脫落。
圖5及圖6所示之晶片接合材(接著材)BP1係用以將半導體晶片SC固定於晶片焊墊DP上且電性連接半導體晶片SC與晶片焊墊DP之導電性構件(晶片接合材)。於本實施形態中，晶片接合材BP1係含有複數個銀(Ag)粒子(Ag填料)之所謂之被稱為銀(Ag)漿料之導電性樹脂接著材。銀漿可藉由例如環氧系熱硬化性樹脂之接著力而提高與半導體晶片SC之接著力，且經由複數個銀粒子確保導通路徑。
於將半導體裝置PK1安裝於未圖示之安裝基板之步驟中，為使未圖示之焊接材熔融而分別接合引線LD與未圖示之安裝基板側之端子，而實施被稱為回焊處理之加熱處理。於使用在樹脂中混合有導電性粒子之導電性接合材作為晶片接合材BP1之情形時，即便任意設定上述回焊處理之處理溫度，導電性接合材亦不會熔融。因此，可防止因半導體晶片SC與晶片焊墊DP之接合部之晶片接合材BP1於半導體裝置PK1之安裝時再熔融而產生之不良狀況，該方面而言較佳。
又，於本實施形態之情形時，以覆蓋晶片焊墊DP之上表面DPt之方式，形成例如包含銀之金屬膜(鍍膜、鍍金屬膜)CM1，且於金屬膜CM1上配置有晶片接合材BP1。金屬膜CM1例如可藉由電鍍法形成。藉由以覆蓋晶片焊墊DP之上表面DPt之方式形成金屬膜CM1，可抑制作為晶片焊墊DP之基材之銅(Cu)或銅合金之氧化。又，於使用銀漿作為晶片接合材BP1之情形時，藉由於晶片焊墊DP之上表面DPt形成與銀漿之接著性高於作為晶片焊墊DP之基材之銅(Cu)或銅合金之金屬膜 CM1，可提高晶片接合材BP1與晶片焊墊DP之接著強度。
如上所述，為了應對不同之要求規格，較佳為可預先製造平面尺寸不同之複數種半導體晶片SC，但較佳為使半導體晶片SC以外之零件共通化。因此，於本實施形態中，以覆蓋晶片焊墊DP之上表面DPt之大部分之方式形成有金屬膜CM1。藉此，即便於搭載平面尺寸大於圖5所示之半導體晶片SC之情形時，亦可於晶片接合材BP1與晶片焊墊DP之間介入金屬膜CM1。因此，於如圖5所示般搭載平面尺寸較小之半導體晶片SC之情形時，未搭載半導體晶片SC之區域變得大於搭載有半導體晶片之區域。
又，如圖5所示，晶片焊墊DP藉由懸掛引線TL支持。該懸掛引線TL係於半導體裝置PK1之製造步驟中用以將晶片焊墊DP固定於引線框架之框架部LFc之支持構件。
又，如圖5及圖6所示，半導體晶片SC之源極電極焊墊SE與引線LDs經由金屬帶(導電性構件、金屬箔、帶狀金屬構件)MB1電性連接。金屬帶MB1係相當於連接圖1所示之電晶體Q1之源極S與源極用引線LDs之配線之導電性構件，例如包含鋁(Al)。
詳細而言，如圖6所示，金屬帶MB1之一端接合於半導體晶片SC之源極電極焊墊SE。另一方面，金屬帶MB1之與上述一端為相反側之另一端接合於形成在引線LDs之一部分之連接部(帶連接部)RB1之上表面(連接面、帶連接面)RBt。於圖5所示之例中，半導體晶片SC於俯視下呈長方形，金屬帶MB1以與半導體晶片SC之長邊交叉之方式配置。
於金屬帶MB1與源極電極焊墊SE之接合部，露出於源極電極焊墊SE之最表面之金屬構件(例如鋁)、與構成金屬帶MB1之例如鋁帶呈金屬結合而接合。另一方面，於與金屬帶MB1連接之連接部RB1之上表面RBt，露出例如構成基材之銅(Cu)，且銅(Cu)之露出面與構成金 屬帶MB1之例如鋁帶呈金屬結合而接合。雖詳情於下文敍述，但於接合金屬帶MB1時，藉由自接合工具施加超音波，可形成如上所述之接合部。於將鋁帶接合至引線LD之情形時，與於接合面形成鍍銀膜相比，使構成基材之銅露出可提高接合強度。因此，於引線LDs之連接部RB1之上表面RBt，未形成如覆蓋晶片焊墊DP之上表面DPt之金屬膜CM1般之金屬膜，且露出有作為基材之銅或銅合金。
又，如圖6所示，引線LDs之連接部RB1之上表面RBt之高度配置於較晶片焊墊DP之上表面DPt高之位置。詳細而言，引線LDs具有連接金屬帶MB1之連接部RB1、及具有自密封體MR露出之下表面(安裝面)LDb之端子部TN1。又，引線LDs於連接部RB1與端子部TN1之間具有以連接部RB1之位置變得高於端子部TN1之位置之方式設置之偏移部(彎曲加工部、傾斜部、階差部)SL1。因此，連接部RB1之下表面RBb被密封體MR覆蓋。換言之，引線LDs之連接部RB1藉由密封體MR密封。藉由如此以密封體MR密封引線LD下表面之一部分，引線LD變得不易自密封體MR脫落。其結果，可提高半導體裝置PK1之電性連接可靠性。
又，如圖5及圖7所示，與晶片焊墊DP相鄰地配置與半導體晶片SC之閘極電極焊墊GE電性連接之作為外部端子之引線LDg。引線LDg與晶片焊墊DP分離設置。又，如圖7所示，引線LDg具有作為供導線MW1接合之接合區域之連接部(導線連接部)RB2、及具有自密封體MR露出之下表面LDb之端子部TN1。又，引線LDg於連接部RB2與端子部TN2之間，具有以連接部RB2之位置變得高於端子部TN2之位置之方式設置之偏移部(彎曲加工部、傾斜部、階差部)SL2。因此，連接部RB2之下表面RBb被密封體MR覆蓋。
又，連接閘極電極焊墊GE與引線LDg之導線MW1例如為包含金(Au)之金屬線。並且，於引線LD之連接部RB2之上表面(連接面、導 線連接面)RBt，形成有例如包含銀之金屬膜(鍍膜、鍍金屬膜)CM2。藉由以覆蓋引線LD之連接部RB2之上表面RBt之方式形成金屬膜CM2，可抑制作為引線LD之基材之銅(Cu)或銅合金之氧化。因氧化銅膜為阻礙電或熱之傳導性之主要原因，故藉由抑制基材之氧化可提高引線LD之電傳導性或熱傳導性。又，藉由以覆蓋連接部RB2之上表面RBt之方式形成金屬膜CM2，導線MW1接合時之打線接合性提高。因此，於本實施形態中，在供金製之導線MW1接合之連接部RB2之上表面RBt，選擇性形成有金屬膜CM2。再者，於分別以相同之金屬材料形成形成於晶片焊墊DP之上表面DPt之金屬膜CM1與形成於引線LDg之金屬膜CM2之情形時，可統一形成該等金屬膜CM1及金屬膜CM2。此時，較佳為不於圖6所示之供鋁帶連接之引線LDs之連接部RB1之上表面RBt形成金屬膜，故較佳為以由未圖示之掩膜覆蓋連接部RB1之上表面RBt之狀態形成。
又，如圖6所示，半導體晶片SC、引線LDs之連接部RB1、及金屬帶MB1由密封體MR密封。又，如圖7所示，引線LDg之連接部RB2、及導線MW1由密封體MR密封。
密封體MR係密封半導體晶片SC、金屬帶MB1及導線MW1之樹脂體，且具有上表面MRt(參照圖3、圖6)及位於上表面MRt之相反側之下表面(安裝面)MRb(參照圖4、圖6、圖7)。又，如圖3及圖4所示，密封體MR於俯視下呈四邊形，且具有4個側面MRs。
密封體MR例如主要由環氧系樹脂等熱硬化性樹脂構成。又，為使密封體MR之特性(例如因熱影響產生之膨脹特性)提高，例如亦有於樹脂材料中混合氧化矽(二氧化矽、SiO2)粒子等填料粒子之情形。
<晶片焊墊上之佈局詳情>
此處，說明圖5所示之晶片焊墊DP上之詳細佈局。圖8係針對圖5之變化例，顯示於晶片焊墊之未搭載半導體晶片之部分搭載有構件之 狀態之主要部分放大俯視圖。又，圖40係顯示作為針對圖5之比較例之半導體裝置之內部構造的透視俯視圖。
如上所述，於將平面尺寸不同之複數種半導體晶片搭載於一種平面尺寸之晶片焊墊DP之情形時，有如圖5所示般在晶片焊墊DP之上表面DPt殘留較寬之未搭載半導體晶片SC之區域之情形。換言之，有於俯視下，該晶片焊墊DP之上表面DPt之未搭載半導體晶片SC之區域之面積大於半導體晶片之面積之情形。於圖5中，晶片焊墊DP包含未搭載半導體晶片SC之部分DP1、及俯視下設置於部分DP1與引線LDs之間且搭載有半導體晶片SC之部分DP2。又，Y方向上之半導體晶片SC之長度Lc1短於(小於)Y方向上之部分DP1之長度L1。換言之，於Y方向上，晶片焊墊DP之部分DP1之長度L1長於(大於)部分DP2之長度L2。於圖5所示之例中，晶片焊墊DP之上表面DPt中，搭載有半導體晶片SC之區域之面積為一半以下。又，自將半導體晶片SC之源極電極焊墊SE與源極用引線LDs之連接距離靠近而降低阻抗成分之觀點而言，半導體晶片SC之搭載位置較佳為較晶片焊墊DP之中央部更靠近引線LDs側之位置。因此，位於較晶片焊墊DP之部分DP2離引線LDs更遠之側之部分DP1之面積進一步變大。
自半導體裝置PK1之通用性之觀點而言，因較佳為將端子排列共通化，故即便如圖5所示般殘留較寬之未搭載半導體晶片SC之區域亦無問題。又，自半導體裝置PK1之散熱性之觀點而言，因藉由增大晶片焊墊DP之平面面積而可增大散熱路徑之剖面積，故於半導體晶片SC之平面尺寸變小之情形時，晶片焊墊DP之平面尺寸亦較大者較佳。
然而，根據本案發明者之研究判定，若藉由將半導體晶片SC之平面尺寸小型化而使晶片焊墊DP之未搭載半導體晶片SC之區域之面積變大，則半導體晶片SC與晶片焊墊DP之接著面變得易損傷。詳細 而言，於如圖40所示之比較例之半導體裝置PKh1般於晶片焊墊DP之部分DP1上未配置圖5所示之構件PS1之情形時，判定接著固定半導體晶片SC與晶片焊墊DP之晶片接合材BP1產生龜裂，且該龜裂於晶片接合材BP1內蔓延(晶片接合材BP1整體破壞)，將半導體晶片SC與晶片焊墊DP剝離。該現象有時會因將半導體裝置PKh1安裝於未圖示之安裝基板時進行之回焊處理時之熱影響而產生。又，即使於回焊處理後未產生龜裂，亦有因其後之溫度循環負荷而產生龜裂之情形。又，若詳細檢查於該晶片接合材BP1內龜裂蔓延且剝離之半導體裝置PKh1，則判定於未搭載半導體晶片SC之部分DP1，密封體MR與晶片焊墊DP之接著界面亦遍及大致整面地剝離。
根據上述之見解，認為晶片接合材BP1產生龜裂之現象由以下之機制產生。即，若對半導體裝置PKh1施加溫度循環負荷，則因密封體MR與晶片焊墊DP之線膨脹係數之不同，而於密封體MR與晶片焊墊DP之接著界面產生應力。該應力之大小與線膨脹係數之差之大小、及接著界面之面積成比例地變大，故晶片焊墊DP之部分之DP1之面積越大，產生應力越大。又，於半導體晶片SC與晶片焊墊DP之接著界面，產生因半導體晶片SC與晶片焊墊DP之線膨脹係數之不同所引起之其他應力。因此，晶片焊墊DP與密封體MR之接著介面所產生之應力易集中於晶片焊墊DP之部分DP1與部分DP2之邊界。因此，認為於半導體晶片SC之平面尺寸較小之情形、即晶片焊墊DP1之面積較大之情形時，在晶片焊墊DP之部分DP1與部分DP2之邊界產生較大之應力，且因該應力而使晶片接合材BP1產生龜裂，以致剝離。
如圖6所示，因晶片焊墊DP與密封體MR之線膨脹係數之不同而產生之應力於晶片焊墊DP之下表面DPb自密封體MR露出之晶片焊墊露出型之半導體裝置中變得特別大。於晶片焊墊DP之整個下表面DPb由密封體MR密封之情形時，藉由以包圍晶片焊墊DP之方式形成密封 體MR，而容易抑制晶片焊墊DP之熱膨脹、熱收縮。然而，於晶片焊墊DP之下表面DPb自密封體MR露出之情形時，晶片焊墊DP易因熱影響而膨脹或收縮，故應力易變大。
又，若半導體晶片SC之厚度變薄至100μm以下左右，則必須減少包含導電性材料之晶片接合材BP1之供給量。其目的是防止包含導電性材料之晶片接合材BP1迴繞至半導體晶片SC之正面SCt側而導致背面SCb(參照圖6)側之汲極電極DE(參照圖6)與正面SCt側之源極電極焊墊SE短路。該情形時，於半導體晶片SC之周緣部，因晶片接合材BP1之圓角形狀難以形成，故與半導體晶片SC之厚度厚於100μm之情形相比，晶片接合材BP1變得易損傷。
因此，本案發明者對降低產生於晶片焊墊DP之部分DP1與部分DP2之邊界之應力之技術進行研究，發現了如下構成。即，如圖8所示，於晶片焊墊DP之部分DP1之上表面DPt，在半導體晶片SC之側面SCs1與晶片焊墊DP之周緣部(位於與引線LDs相反之側之側面DPs2)之間，固定有構件PS1。構件PS1只要可密接且固定於晶片焊墊DP之上表面DPt上(圖8所示之例中為金屬膜CM1上)，則可使用各種材料。於圖5或圖8所示之例中，例如構件PS1包含使與晶片接合材BP1相同之材料即於樹脂中含有複數個銀粒子之被稱為銀漿之導電性之樹脂接著材硬化者。藉由以相同材料構成晶片接合材BP1與構件PS1，可於半導體裝置PK1(參照圖5)之製造步驟中，減少用以形成構件PS1而追加之步驟。
該包含銀漿之構件PS1接著固定於晶片焊墊DP之上表面DPt上。如此，於在半導體晶片SC之側面SCs2與晶片焊墊DP之周緣部(位於與引線LDs相反之側之側面DPs2)之間接著固定有構件PS1之情形時，在對半導體裝置PK1施加溫度負荷時，應力之施加方法與圖40所示之半導體裝置PK1不同。即，因晶片焊墊DP與密封體MR(參照圖6)之線膨 脹係數之不同而產生之應力之一部分被分散至構件PS1。其結果，可使產生於晶片焊墊DP之部分DP1與部分DP2之邊界之應力降低。並且，藉由使產生於晶片焊墊DP之部分DP1與部分DP2之邊界之應力降低，可抑制半導體晶片SC與晶片焊墊DP之接著面之損傷。
然而，因構件PS1係用以抑制半導體晶片SC與晶片焊墊DP之接著面之損傷之構件，故無須與形成於半導體裝置PK1之電路電性連接。若如半導體晶片SC般經由圖5所示之金屬帶MB1或導線MW1等導電性構件與引線LD電性連接，則製造步驟變得煩雜。於本實施形態中，如上所述，自使製造步驟效率化之觀點而言，使用與晶片接合材BP1相同之銀漿形成構件PS1，故亦可認為構件PS1之搭載面PSb(參照圖6)與晶片焊墊DP電性連接。然而，自無須使構件PS1發揮電性功能而使雜訊降低之觀點而言，較佳為使構件PS1之電性功能降低。因此，構件PS1之搭載面PSb以外之部分未與其他引線LD或半導體晶片SC電性連接。換言之，本實施形態之構件PS1係與晶片焊墊DP及與晶片焊墊DP一體而形成之引線LDd以外之引線LD電性分離(絕緣)。因此，即使將構件PS1搭載於晶片焊墊DP之部分DP1，亦可抑制製造效率之降低。又，因構件PS1作為電性電路而成為開放端，故於在使用圖1說明之電晶體Q1中流通電流時，電流難以流至構件PS1。因此，即使以導電性構件形成構件PS1之情形時，亦可降低對電晶體Q1之電性特性造成之影響。
又，如圖8所示，自與Y方向正交之X方向上之半導體晶片SC之周緣部(側面SCs3)至晶片焊墊DP之周緣部(側面DPs3)之俯視下之長度(距離)L3短於(小於)Y方向上之部分DP1之長度L1。又，自與Y方向正交之X方向上之半導體晶片SC之周緣部(側面SCs4)至晶片焊墊DP之周緣部(側面DPs4)之俯視下之距離(省略符號之圖示)短於(小於)Y方向上之部分DP1之長度L1。即，Y方向上之未搭載半導體晶片SC之區域之 長度L1長於(大於)X方向上之未搭載半導體晶片SC之區域之長度L3。該情形時，半導體晶片SC之側面SCs3及側面SCs4產生之應力與側面SCs2產生之應力相比較小，故亦可不考慮。同樣地，半導體晶片SC之側面SCs1與晶片焊墊DP之側面DPs1之俯視下之距離小於長度L1，故亦可不考慮於半導體晶片SC之側面SCs1產生之應力。
即，藉由於產生最大應力之半導體晶片SC之側面SCs2與晶片焊墊DP之側面DPs2之間配置構件PS1，可抑制半導體晶片SC與晶片焊墊DP之接著面之損傷。
又，自增大使產生於晶片焊墊DP之部分DP1與部分DP2之邊界之應力降低之程度之觀點而言，較佳為縮小圖8所示之Y方向上之半導體晶片SC與構件PS1之分離距離P1。於圖8所示之例中，分離距離P1變得小於Y方向上之半導體晶片之長度Lc1。又，於圖5中，顯示有於半導體晶片SC之側面SCs2與晶片焊墊DP之周緣部(位於與引線LDs相反之側之側面DPs2)之間接著固定有複數個構件PS1之例，複數個構件PS1中之配置於最靠近半導體晶片SC1之構件PS1與半導體晶片SC之分離距離P1變得小於Y方向上之半導體晶片之長度Lc1。因產生於晶片焊墊DP之部分DP1與部分DP2之邊界之應力與Y方向上之構件PS1與半導體晶片SC之分離距離P1成比例地變大，故分離距離P1較佳為小於Y方向上之半導體晶片SC之長度Lc1。
又，自使藉由構件PS1分散應力之效果提高之觀點而言，構件PS1之厚度較佳為大於半導體晶片SC之厚度。如圖6所示，構件PS1之厚度大於半導體晶片SC之厚度。藉由增加構件PS1之厚度，可抑制密封體MR之熱膨脹、熱收縮對晶片接合材BP1之影響。再者，於圖6中，顯示有於晶片焊墊DP之部分DP1接著固定複數個構件PS1之例，複數個構件PS1之各者之厚度大於半導體晶片SC之厚度。例如，於圖6所示之例中，構件PS1之厚度為150μm左右。
又，自使產生於晶片焊墊DP之部分DP1與部分DP2之邊界之應力確實地分散之觀點而言，較佳為如圖8所示，X方向上之構件PS1之長度Lps1長於X方向上之半導體晶片SC之長度Lc12。於X方向上，若構件PS1延伸得較半導體晶片SC長，則可抑制應力自構件PS1之周圍迴繞而施加至晶片焊墊DP之部分DP1與部分DP2之邊界。於本實施形態中，在晶片焊墊DP之上表面DPt上形成金屬膜CM1，構件PS1以覆蓋金屬膜CM1之沿側面DPs3之邊至相反側之邊之方式沿X方向延伸。該情形時，可於俯視下在半導體晶片SC之側面SCs2與晶片焊墊DP之側面DPs2之間確實地介入構件PS1，故可大幅地降低產生於晶片焊墊DP之部分DP1與部分DP2之邊界之應力。
然而，考慮有構件PS1與晶片焊墊DP之側面DPs2之於Y方向上之分離距離較長之情形、應力集中產生於構件PS1致使構件PS1損傷或剝離之情形。若構件PS1自晶片焊墊DP剝離，則因無法獲得構件PS1之應力分散效果，故成為應力集中易產生於晶片焊墊DP之部分DP1與部分DP2之邊界之狀態。因此，自防止或抑制形成於最靠近半導體晶片SC之位置之構件PS1之剝離之觀點而言，較佳為如圖5所示之半導體裝置PK1般，於晶片焊墊DP之部分DP1搭載複數個構件PS1。再者，雖省略圖示，但作為針對圖5之變化例，亦考慮如下方法，即，例如藉由增加圖5所示之Y方向之長度(寬度)(例如設為將圖5所示之兩個構件PS1一體化之程度之寬度)，而抑制構件PS1之損傷。然而，自降低搭載於半導體裝置PK1內之材料之使用量之觀點而言，較佳為如圖5所示，搭載沿與Y方向正交之X方向延伸之複數個構件PS1。
又，自使應力確實地分散於複數個構件PS1間之觀點而言，較佳為如圖5所示，Y方向上之複數個構件PS1間之分離距離P2小於Y方向上之半導體晶片SC之長度Lc1。藉此，因可降低施加於複數個構件PS1之各者之應力，故可抑制構件PS1之剝離。
又，作為與本實施形態不同之態樣，考慮有如下方法，即，不設置圖5、圖6及圖8所示之構件PS1，取而代之於晶片焊墊DP形成未圖示之溝或複數個凹陷部(dimple)、或者實施粗面化處理。然而，若考慮如上所述搭載平面尺寸不同之複數種半導體晶片SC，則因搭載半導體晶片SC之區域之範圍不同，故難以個別地使形成溝或凹陷部之位置或實施粗面化處理之位置最佳化。另一方面，於本實施形態中，因藉由對共通之晶片焊墊DP追加構件PS1，而抑制晶片接合材BP1之損傷，故可根據半導體晶片SC之平面尺寸，容易地使構件PS1之搭載位置最佳化。
<半導體裝置之製造方法>
其次，對使用圖1~圖7說明之半導體裝置PK1之製造步驟進行說明。半導體裝置PK1按照圖9所示之流程製造。圖9係顯示使用圖1~圖7說明之半導體裝置之製造步驟之概要之說明圖。
<引線框架準備步驟>
首先，於圖9所示之引線框架準備步驟中，準備圖10~圖12所示之引線框架LF。圖10係顯示圖9所示之引線框架準備步驟中所要準備之配線基板之整體構造之俯視圖。又，圖11係圖10所示之1個器件形成部之放大俯視圖。又，圖12係沿圖11之A-A線之放大剖面圖。
如圖10所示，本步驟中準備之引線框架LF於外框LFb之內側具備複數個(圖10中為32個)器件形成部LFa。複數個器件形成部LFa各自相當於圖5所示之1個半導體裝置PK1。引線框架LF係複數個器件形成部LFa配置成矩陣狀之所謂之多腔基材。如此，藉由使用具備複數個器件形成部LFa之引線框架LF，可統一製造複數個半導體裝置PK1(參照圖3)，故可提高製造效率。引線框架LF包含例如以銅(Cu)為主體之金屬材料，其厚度例如為125μm~200μm左右。
又，如圖11所示，各器件形成部LFa之周圍以框架部LFc包圍。 框架部LFc係在圖9所示之單片化步驟之前的期間支持形成於器件形成部LFa內之各構件之支持部。
又，如圖11及圖12所示，於各器件形成部LFa已形成有使用圖5~圖7說明之晶片焊墊DP及複數條引線LD。晶片焊墊DP經由懸掛引線TL而與配置於器件形成部LFa之周圍之框架部LFc連結，且由框架部LFc支持。又，複數條引線LD分別連結於框架部LFc，且由框架部LFc支持。
於圖11所示之例中，自俯視下呈四邊形之器件形成部LFa之一邊側朝向對向邊，且沿Y方向以源極用引線LDs、晶片焊墊DP、與晶片焊墊DP一體地形成之汲極用引線LDd之順序排列。又，沿X方向，與引線LDs相鄰地排列有閘極用引線LDg。
又，於晶片焊墊DP之上表面DPt預先形成有包含鎳(Ni)、或銀(Ag)之金屬膜CM1。如上所述，因可搭載平面尺寸不同之複數種半導體晶片SC(參照圖5)，故金屬膜CM1以覆蓋晶片焊墊DP之上表面DPt之大部分之方式形成。換言之，於本實施形態中，以跨及未搭載半導體晶片之部分DP1與作為半導體晶片之搭載預定區域之部分DP2之方式形成有金屬膜CM1。
又，於複數條引線LD中之閘極用引線LDg之連接部Rb2之上表面RBt，預先形成有例如包含銀之金屬膜CM2。另一方面，於複數條引線LD中之源極用引線LDs之連接部RB1之上表面RBt未形成金屬膜CM2，而露出作為基材之銅合金。金屬膜CM1、CM2分別可藉由例如鍍敷法形成。又，於以相同材料形成金屬膜CM1、CM2之情形時，可統一形成。
又，對複數條引線LD中之引線LDs預先實施彎曲加工，形成以連接部RB1之位置變得高於端子部TN1之位置之方式設置之偏移部(彎曲加工部、傾斜部、階差部)SL1。又，亦對複數條引線中之與引線LDs 相鄰配置之引線LDg預先實施彎曲加工，形成以連接部RB2之位置變得高於端子部TN1之位置之方式設置之偏移部(彎曲加工部、傾斜部、階差部)SL1。偏移部SL1可藉由例如壓製加工形成。
本步驟中所要準備之引線框架LF之上述以外之特徵如使用圖5~圖8所說明般，故省略重複之說明。
<第1構件配置>
又，於圖9所示之第1構件配置步驟中，如圖13、圖14、及圖15所示，於晶片焊墊DP之部分DP1配置構件PS1。圖13係顯示於圖11所示之晶片焊墊之一部分塗佈有銀漿之狀態之放大俯視圖。又，圖14係沿圖13之A-A線之放大剖面圖。又，圖15係模式性顯示於沿圖13之B-B線之放大剖面塗佈銀漿之方式之說明圖。又，圖16係顯示針對圖15之變化例之說明圖。又，圖17係顯示藉由圖16所示之方式形成之銀漿之平面形狀之放大俯視圖。
於本步驟中，若為如圖13~圖15所示般可於晶片焊墊DP1上(於圖13~圖15中為金屬膜CM1上)密接固定者，則對於構件PS1之材料可應用多種變化例。於本實施形態之例中，作為構件PS1，使用與用以搭載半導體晶片之晶片接合材BP1相同之材料，例如含有複數個銀(Ag)粒子之被稱為銀(Ag)漿料之導電性之樹脂接著材。銀漿因於使樹脂成分硬化前具有流動性，故若如圖15所示，自噴嘴NZ1向晶片焊墊DP之上表面DPt塗佈漿料狀態之構件PS1，則構件PS1與晶片焊墊DP之部分DP1(詳細而言，為形成於晶片焊墊DP上之金屬膜CM1)密接。又，於圖15所示之例中，一面噴出包含銀漿之構件PS1，一面使噴嘴NZ1沿X方向移動。藉此，可如圖13及圖15所示，形成沿X方向延伸之構件PS1。以下，將如圖15所示般一面噴出漿料材一面使噴嘴移動塗佈之方式記述為拉線方式。
作為針對圖15之變化例，可如圖16所示，準備具有複數個噴出 口之噴嘴NZ2，且以自複數個噴出口統一噴出漿料狀之構件PS1之方式形成構件PS1。以下，如圖16所示，將自複數個噴出口噴出漿料材進行塗佈之方式記述為多點塗佈方式。
於以如圖15所示之拉線方式塗佈構件PS1之情形時，可防止構件PS1沿構件PS1之X方向被分斷。構件PS1係為降低於圖13所示之晶片焊墊DP之部分DP1與部分DP2之邊界產生之應力而使應力分散而設置之構件。於沿X方向延伸之構件PS1之一部分於途中被分斷之情形時，應力經由構件PS1之分斷部位傳遞，致使於晶片焊墊DP之部分DP1與部分DP2之邊界產生之應力變大。因此，自抑制傳遞至晶片焊墊DP之部分DP1與部分DP2之邊界之觀點而言，較佳為不使構件PS1沿X方向分斷。即，自降低產生於晶片焊墊DP之部分DP1與部分DP2之邊界之應力之觀點而言，較佳為圖15所示之拉線方式。
另一方面，於圖16所示之多點塗佈方式之情形時，因無需使噴嘴NZ2移動之時間，故可縮短塗佈時間。因此，自有效率地製造之觀點而言，較佳為圖16所示之多點塗佈方式。然而，於多點塗佈方式之情形時，統一對晶片焊墊DP上之複數個部位塗佈構件PS1。因此，較佳為使塗佈量較上述拉線方式之情形增多，以便使鄰接之構件PS1確實地接觸。換言之，自降低構件PS1之形成所需之銀漿之使用量之觀點而言，較佳為圖15所示之拉線方式。
再者，於藉由圖15所示之拉線方式形成構件PS1之情形時，如圖13所示與塗佈方向(X方向)正交之Y方向上之構件PS1之擴展相同。另一方面，於藉由圖16所示之多點塗佈方式形成構件PS1之情形時，如圖17所示，與塗佈方向(X方向)正交之Y方向上之構件PS1之擴展成為較大之部分與較小之部分彼此重複之形狀。
然而，如上所述，於本實施形態中，以與晶片接合材BP1相同之材料形成構件PS1。因此，於本步驟中，作為圖9所示之半導體晶片搭 載步驟之準備，可如圖13或圖17所示，預先將晶片接合材BP1塗佈於晶片焊墊DP之晶片搭載區域即部分DP2。
晶片接合材BP1之塗佈方法可應用使用圖15說明之拉線方式、或使用圖16說明之多點塗佈方式。然而，於半導體晶片之厚度較薄之情形時，自防止晶片接合材BP1迴繞於半導體晶片之正面側而產生短路之觀點而言，較佳為可降低晶片接合材BP1之塗佈量之拉線方式。又，藉由拉線方式分別形成晶片接合材BP1及構件PS1之情形時，可如圖15所示自噴嘴NZ1供給構件PS1及晶片接合材BP1之各者。即，因可使構件PS1之供給裝置與晶片接合材BP1之供給裝置兼用化，故可簡化製造裝置。
又，構件PS1與晶片接合材BP1之供給順序並無特別限定，但自抑制晶片接合材BP1之乾燥之觀點而言，較佳為先形成構件PS1。此時，於以拉線方式形成構件PS1之情形時，相較於多點塗佈方式，塗佈時間變長。因此，於圖9所示之半導體晶片搭載步驟中，自抑制晶片接合材BP1乾燥而難以擴展之情況之觀點而言，晶片接合材BP1較佳於半導體晶片搭載步驟之前塗佈。
再者，於本實施形態中，對如下之實施態樣進行了說明，即，自有效率地進行製造步驟之觀點而言，於半導體晶片搭載步驟前進行第1構件配置步驟，但作為變化例，亦可於半導體晶片搭載步驟後進行第1構件配置步驟。
<半導體晶片搭載步驟>
其次，於圖9所示之半導體晶片搭載步驟中，如圖18及圖19所示，於引線框架LF之晶片焊墊DP搭載半導體晶片SC。圖18係顯示於圖13所示之晶片焊墊上搭載有半導體晶片之狀態之放大俯視圖。又，圖19係沿圖18之A-A線之放大剖面圖。
於本步驟中，於與作為汲極端子之引線LDd一體地形成之晶片焊 墊DP之部分DP2介隔金屬接合材BP1搭載半導體晶片SC。於圖18所示之例中，半導體晶片SC係以半導體晶片SC之四個側面中的側面SCs1沿晶片焊墊DP之側面DPs1之方式配置於晶片焊墊DP上。換言之，半導體晶片SC係以側面SCs1與源極用引線LDs之前端(連接部RB1側之端部)對向之方式配置於晶片焊墊DP上。又，如圖19所示，半導體晶片SC係以形成有汲極電極DE之背面SCb與晶片焊墊DP之作為晶片搭載面之上表面DPt對向之方式經由晶片接合材BP1接著固定。藉此，半導體晶片SC之源極電極焊墊SE及閘極電極焊墊GE如圖18所示般露出。另一方面，如圖19所示，半導體晶片之汲極電極DE經由作為導電性接著材之晶片接合材BP1及金屬膜CM1而與晶片焊墊DP電性連接。
又，於本步驟中，為使半導體晶片SC與作為源極端子之引線LDs之連接部RB1之距離接近，半導體晶片SC於晶片焊墊DP之上表面DPt靠近引線LDs而配置。因此，與將半導體晶片SC搭載於晶片焊墊DP之中央部之情形相比，自半導體晶片SC之側面SCs2至晶片焊墊DP之部分DP1側之側面DPs2之距離變大。
又，晶片接合材BP1係於例如包含環氧樹脂等熱硬化性樹脂之樹脂材料中混合複數個導電性粒子(例如銀粒子)之樹脂接著材，且硬化前之性狀呈漿料狀。因此，如上所述，預先於晶片焊墊DP之部分DP2塗佈漿料狀之晶片接合材BP1後，將半導體晶片SC朝向晶片焊墊DP之上表面DPt按壓。藉此，可於半導體晶片SC與晶片焊墊DP之上表面DPt之間，使晶片接合材BP1擴展。
其次，於本步驟中，在將半導體晶片SC分別搭載於晶片焊墊DP上後，統一使晶片接合材BP1及構件PS1硬化(固化步驟)。因於晶片接合材BP1及構件PS1，如上所述分別包含有熱硬化性樹脂，故藉由實施加熱處理(烘烤處理)，而使熱硬化性樹脂成分硬化。藉由本步驟， 半導體晶片SC接著固定於晶片焊墊DP之部分DP2。又，構件PS1接著固定於晶片焊墊DP之部分DP1。
如本實施形態，藉由以相同材料構成晶片接合材BP1與構件PS1，且於半導體晶片搭載步驟前預先配置構件PS1，可統一使晶片接合材BP1與構件PS1硬化。
<帶接合步驟>
又，於圖9所示之帶接合步驟中，如圖20及圖21所示，將半導體晶片SC之源極電極焊墊SE與作為源極端子之引線LDs之連接部RB1之上表面RBt經由金屬帶MB1電性連接。圖20係顯示將圖18所示之半導體晶片與引線經由金屬帶電性連接之狀態之放大俯視圖。又，圖21及圖22係階段性顯示於沿圖20之A-A線之剖面連接金屬帶之狀態之放大剖面圖。
於本步驟中，如圖21及圖22所示，使用如下之帶連接裝置進行帶接合，該帶連接裝置具有：接合工具23，其將金屬帶20接合至被接合構件；切割刀24，其切斷接合後之金屬帶20；及帶導引件28，其於與接合工具23之間的間隙夾著金屬帶20，控制金屬帶20之送出方向。首先，如圖21所示，於半導體晶片SC之源極電極焊墊SE接合金屬帶20之一端(圖20所示之金屬帶MB1之一端)。於本步驟中，藉由將自接合工具23與帶引導件28之間的間隙送出之金屬帶20按壓至源極電極焊墊SE，而使金屬帶20之形狀按照接合工具23變形。又，藉由對接合工具23施加超音波，可於金屬帶20與源極電極焊墊SE之接觸界面形成金屬結合，而電性連接金屬帶20與源極電極焊墊SE。此時，於金屬帶20之被按壓面形成壓痕20a。
又，晶片焊墊DP之位於晶片搭載面之相反側之下表面DPb與支持台25之突出部保持面25a密接，且保持於支持台25。藉由如此般以將作為被接合部之源極電極焊墊SE由支持台25支持之狀態進行接合， 而使施加至接合工具23之超音波有效率地傳遞至金屬帶20之接合面。其結果，可提高金屬帶20與源極電極焊墊SE之接合強度。支持台25較佳為使用例如金屬製之平台(金屬平台)，以便將施加至接合工具23之超音波集中傳遞至接合界面。
其次，藉由接合工具23與帶導引件28，以金屬帶20之送出方向得以控制之狀態，一面自保持金屬帶20之捲盤21依序送出金屬帶20一面使接合工具23移動，如圖22所示，於引線LDs之連接部RB1之上表面RBt接合金屬帶20之另一端。此時，藉由將金屬帶20按壓至引線LDs之作為帶連接面之上表面RBt，而使金屬帶20按照接合工具23以與引線LDs之連接部RB1之上表面RBt密接之方式變形。又，藉由對接合工具23施加超音波，可於金屬帶20與連接部RB1之上表面RBt之接觸界面形成金屬結合，而電性連接金屬帶20與連接部RB1之上表面RBt。
又，連接部RB1之位於上表面RBt之相反側(正下方)之下表面RBb與支持台25之帶連接部保持面25b密接，且保持於支持台25。於圖22所示之例中，因於引線LDs設置有偏移部SL1，故於支持台25之一部分設置突出部，且突出部之上表面成為帶連接部保持面25b。如此，藉由以將作為被接合部之連接部RB1之下表面RBb由支持台25之帶連接部保持面25b支持之狀態進行接合，而使施加於接合工具23之超音波有效率地傳遞至金屬帶20之接合面。其結果，可提高金屬帶20與連接部RB1之接合強度。
其次，雖省略圖示，但進而使接合工具23及帶導引件28沿Y方向於向遠離半導體晶片SC之方向移動。並且，藉由將圖22所示之切割刀24向金屬帶20按壓，而切斷金屬帶20。藉此，電性連接半導體晶片SC之源極電極焊墊SE與源極用引線LDs之連接部RB1之金屬帶MB1(參照圖20)自金屬帶20分離而形成。此時，切割刀24之切割位置 較佳設於連接部RB1之上表面RBt上。以將金屬帶20夾在切割刀24與上表面RBt之間的狀態進行切斷能夠穩定地切斷金屬帶20。
藉由上述步驟，如圖20所示，半導體晶片SC之源極電極焊墊SE與引線LDs之連接部RB1之上表面RBt經由金屬帶MB1電性連接。
<打線接合步驟>
又，於圖9所示之打線接合步驟中，如圖23及圖24所示，將半導體晶片SC之閘極電極焊墊GE與閘極用引線LDg之連接部RB2之上表面RBt經由導線(金屬導線)MW1電性連接。
圖23係顯示將圖20所示之半導體晶片與閘極用引線經由金屬導線電性連接之狀態之放大俯視圖。又，圖24係顯示於沿圖23之A-A線之剖面連接有導線之狀態之放大剖面圖。
如圖24所示，於本步驟中，藉由對接合工具26施加超音波，使導線MW1之一部分與被接合部金屬結合而進行接合。例如，於圖24所示之例中，首先於形成於閘極電極焊墊GE之最表面之金屬膜(例如鋁膜或金膜)接合例如包含金(Au)之導線MW1之一端。此時，對接合工具26施加超音波，而於接合界面形成金屬結合。
其次，一面自接合工具26送出導線27，一面使接合工具26移動至引線LDg之連接部RB2上。於引線LDg之連接部RB2之上表面RBt，形成有可提高導線MW1與引線LDg之基材(例如銅)之連接強度之金屬膜CM2。引線LDg之基材例如包含銅(Cu)合金，金屬膜CM2例如包含銀(Ag)。並且，藉由對接合工具26施加超音波，而於導線27之一部分(第2接合部)與金屬膜CM2之接合界面形成金屬結合，而將其等電性連接。然後，若切斷導線27，則形成圖23及圖24所示之導線MW1。
於本步驟中，自使超音波有效率地傳遞至被接合部而提高接合強度之觀點而言，較佳為以由支持台25支持被接合部之狀態對接合工具26施加超音波。
又，如圖9所示，打線接合步驟較佳為於帶接合步驟後進行。於帶接合步驟中，於如上所述般連接半導體晶片SC與源極電極焊墊SE時，施加超音波進行連接。此時，於導線MW1與閘極電極焊墊GE預先連接之情形時，會因帶接合時之超音波之影響，而有可能損傷導線MW1或導線MW1之連接部分。因此，連接寬度較金屬帶MB1更窄之導線MW1之打線接合步驟較佳為於帶接合步驟之後進行。
<密封步驟>
其次，於圖9所示之密封步驟中，以絕緣樹脂密封圖23所示之半導體晶片SC、晶片焊墊DP之一部分、複數條引線LD之一部分、金屬帶MB1、及導線MW1，而形成圖25所示之密封體MR。圖25係顯示形成有密封圖23所示之半導體晶片及金屬帶之密封體之狀態之放大俯視圖。又，圖26係顯示於沿圖25之A-A線之剖面，在成形模具內配置有引線框架之狀態之放大剖面圖。
本步驟中，例如如圖26所示般使用具備上模具(第1模具)32、下模具(第2模具)33之成形模具31，藉由所謂之轉移模方式形成密封體MR。
於圖26所示之例中，以器件形成部LFa之晶片焊墊DP及與晶片焊墊DP相鄰配置之複數條引線LD位於形成於上模具32之腔室34內之方式配置引線框架LF，且以上模具32與下模具33夾合(夾入)。若以該狀態將已軟化(塑化)之熱硬化性樹脂(絕緣樹脂)壓入成形模具31之腔室34，則絕緣樹脂被供給至腔室34與下模具33形成之空間內，且按照腔室34之形狀成形。
此時，若將晶片焊墊DP之下表面DPb及引線LD之端子部TN1之下表面LDb與下模具33密接，則下模具DPb、LDb於密封體MR之下表面MRb自密封體MR露出。另一方面，不使引線LDs之連接部RB1之下表面RBb與下模具33密接。因此，連接部RB1被絕緣樹脂覆蓋，且藉 由密封體MR密封。又，於晶片焊墊DP之周緣部形成階差部，且晶片焊墊DP之周緣部之下表面被樹脂密封。如此，因晶片焊墊DP及引線LD之各者之一部分被密封體MR密封，故密封體MR變得不易自MR脫落。
又，密封體MR係將絕緣性樹脂作為主體而構成，但藉由將氧化矽(二氧化矽：SiO2)粒子等填料粒子混合至熱硬化性樹脂，可提高密封體MR之功能(例如針對翹曲變形之耐性)。
<鍍敷步驟>
其次，於圖9所示之鍍敷步驟中，如圖27所示，將引線框架LF浸入未圖示之鍍敷溶液，於自密封體MR露出之金屬部分之表面形成金屬膜SD。圖27係顯示於圖26所示之晶片焊墊及引線之自密封體之露出面形成有金屬膜之狀態之放大剖面圖。
於圖27所示之例中，例如將引線框架LF浸入焊接溶液，且藉由電性鍍敷方式形成作為焊接膜之金屬膜SD。金屬膜SD具有如下功能，即，於將已完成之半導體裝置PK1(參照圖6)安裝於未圖示之安裝基板時，例如使包含焊料之連接材之潤濕性提高。作為金屬膜SD之種類，可列舉例如錫-鉛鍍敷、無Pb鍍敷即純錫鍍敷、錫-鉍鍍敷等。
再者，亦可使用預先於引線框架形成導體膜之預鍍敷之引線框架。此時之導體膜多數情況下例如由鎳膜、形成於鎳膜上之鈀膜、及形成於鈀膜上之金膜而形成。於使用預鍍敷之引線框架之情形時，省略本鍍敷步驟。於使用預鍍敷之引線框架之情形時，即使不使作為基材之銅(Cu)或銅合金露出，與金屬帶MB1之金屬接合性亦良好。因此，於預鍍敷之情形時，於包含金屬帶MB1之接合區域之引線框架整體形成預鍍敷膜。
<單片化步驟>
其次，於圖9所示之單片化步驟中，如圖28所示，將引線框架LF 分割為各個器件形成部LFa。圖28係顯示將圖27所示之引線框架單片化之狀態之放大俯視圖。
於本步驟中，如圖28所示，切斷引線LD之一部分，將引線LD自框架部LFc分離。又，於本步驟中，切斷支持晶片焊墊DP之複數條懸掛引線TL之一部分，將晶片焊墊DP自框架部LFc分離。切斷方法並無特別限定，可藉由壓製加工、或使用旋轉刀之切削加工予以切斷。
藉由以上各步驟，獲得使用圖1~圖7說明之半導體裝置PK1。其後，進行外觀檢查或電性試驗等必要之檢查、試驗，且出貨、或者安裝至未圖示之安裝基板。
<變化例>
其次，說明針對上述實施形態所說明之實施態樣之各種變化例。
首先，於上述實施形態中，說明使用與晶片接合材BP1相同材料即銀漿作為構件PS1之實施態樣。然而，自抑制半導體晶片SC與晶片焊墊DP之接著界面之損傷之觀點而言，可使用如下材料作為構件PS1。
例如，圖29所示之半導體裝置PK2係使用未混合銀粒子等金屬粒子之非導電性之樹脂接著材作為搭載於晶片焊墊DP之部分DP1之構件PS2，以取代圖6所示之構件PS1。圖29係顯示針對圖6之變化例之剖面圖。
於晶片焊墊DP之部分DP1接著固定非導電性之構件(第1構件)PS2之情形時，構件PS2與晶片焊墊DP被電性分離。又，構件PS2與上述實施形態所說明之構件PS1同樣地未與晶片焊墊DP以外之端子(引線LD)電性連接。即，構件PS2與半導體裝置PK2具有之其他構件電性分離。因此，可降低針對半導體裝置PK2具有之電路之雜訊成分。
又，於半導體裝置PK2之製造步驟中，在上述第1構件配置步驟 中，無法兼用供給漿料狀之構件PS2之噴嘴、與供給漿料狀之晶片接合材BP1之噴嘴，必須自分別不同之噴嘴供給，該方面有所不同。但是，關於半導體晶片搭載步驟中所說明之固化步驟可兼用化。即，因於晶片接合材BP1及構件PS2分別含有熱硬化性樹脂，故藉由實施加熱處理(烘烤處理)，可使晶片接合材BP1及構件PS2統一硬化。
圖29所示之半導體裝置PK2除上述不同點外，與上述實施形態所說明之半導體裝置PK1相同。例如，於上述第1構件配置步驟中，可應用拉線方式或多點塗佈方式中任一者配置漿料狀之構件PS2。因此，省略可將上述實施形態所說明之構件PS1置換成構件PS2而應用之說明、及圖示。
又，例如，圖30及圖31所示之半導體裝置PK3係取代圖5及圖6所示之構件PS1，而於晶片焊墊DP之部分DP1介隔作為非導電性之樹脂接著材之構件PS2，固定有以與構件PS2不同之材料構成之構件PS3(圖30中標註點圖案而顯示之構件)。圖30係顯示針對圖5之變化例之透視俯視圖。又，圖31係沿圖30之A-A線之剖面圖。
如半導體裝置PK3般，可於介隔作為接著材之構件PS2接著固定其他構件PS3之情形時，便於加厚將構件PS2與構件PS3視作一體物之情形時之厚度。於例如圖31所示之例中，自構件PS3之上表面PS3t至晶片焊墊DP之上表面DPt之距離變得較自半導體晶片SC之表面SCt至晶片焊墊DP之距離遠。藉由加厚將構件PS2與構件PS3視作一體物之情形時之厚度，可使抑制密封體MR之熱膨脹量(或熱收縮量)之投錨效應變大。因此，可降低因密封體MR與晶片焊墊DP之線膨脹係數之不同而產生之晶片接合材BP1之損傷。
又，因構件PS2如上所述般為非導電性之樹脂接著材，故即使在選擇金屬材料作為構件PS3之情形時，亦可與晶片焊墊DP電性分離。因此，可降低針對半導體裝置PK3具有之電路之雜訊成分。
又，自抑制構件PS3與密封體MR之密接界面之剝離之觀點而言，構件PS3較佳為由線膨脹係數與密封體MR接近之材料、例如矽(Si)等構成。
又，於半導體裝置PK3之製造步驟中，在第1構件配置步驟後，追加將構件PS3搭載於構件PS2上之步驟、及藉由使構件PS2硬化而於晶片焊墊DP上接著固定構件PS3之步驟。其中，使構件PS2硬化之步驟(固化步驟)可於使晶片接合材BP1硬化時統一進行。
圖30及圖31所示之半導體裝置PK3除上述之不同點外，與上述實施形態所說明之半導體裝置PK1相同。因此，省略與上述實施形態重複之說明及圖示。
又，例如，圖32及圖33所示之半導體裝置PK4及圖34所示之半導體裝置PK5係取代圖5及圖6所示之構件PS1，於晶片焊墊DP之部分DP1，以沿X方向排列之方式接合有複數個柱狀凸塊STB1(圖34中為柱狀凸塊STB2)。圖32係顯示針對圖5之其他變化例之透視俯視圖。又，圖33係沿圖32之A-A線之剖面圖。又，圖34係顯示針對圖33之變化例之剖面圖。
圖32及圖33所示之柱狀凸塊STB1可使用上述打線接合步驟中所說明之接合工具26(參照圖24)形成。即，於接合工具26之前端部分，加熱導線27之前端而形成球部(省略圖示)。接著，將該球部接合至圖32及圖33所示之晶片焊墊DP之部分DP1。接合方式可與上述打線接合步驟同樣地應用對接合工具26施加超音波而於接合界面形成金屬結合之方式。並且，若在接合有球部後切斷導線27，則形成圖32及圖33所示之柱狀凸塊STB1。又，圖34所示之柱狀凸塊STB2係於圖33所示之柱狀凸塊STB1上進而形成柱狀凸塊STB1而獲得。若如此般積層複數個柱狀凸塊STB1，則可增高作為與使用圖5說明之構件PS1對應之構件之柱狀凸塊STB2(參照圖34)之高度。其結果，因柱狀凸塊與密封體 MR之接觸面積較柱狀凸塊為1段(柱狀凸塊STB1)時增加，故投錨效應變大。因此，可降低因密封體MR與晶片焊墊DP之線膨脹係數之不同而產生之晶片接合材BP1之損傷。
因本變化例之柱狀凸塊STB1、STB2可如所上述般使用打線接合步驟中所使用之接合工具26(參照圖24)而形成，故圖9所示之第1構件配置步驟較佳為於打線接合步驟即將開始之前或打線接合剛結束後進行。
圖32及圖33所示之半導體裝置PK4及圖34所示之半導體裝置PK5除上述不同點外，與上述實施形態所說明之半導體裝置PK1相同。因此，省略與上述實施形態重複之說明及圖示。
其次，於上述實施形態中，說明將半導體晶片SC介隔包含作為導電性之樹脂接著材之銀漿之晶片接合材BP1搭載於晶片焊墊DP上之實施態樣。然而，作為搭載半導體晶片SC之接著材，可應用多種變化例。
例如，雖省略圖示，但在於半導體晶片SC之背面未形成電極且無須將晶片焊墊DP與半導體晶片SC電性連接之情形時，可使用非導電性之樹脂接著材。該情形時，若與列舉圖29所示之半導體裝置PK2為例進行說明之變化例組合應用，則可於上述第1構件配置步驟中，兼用供給漿料狀之構件PS2之噴嘴、與供給漿料狀且非導電性之晶片接合材之噴嘴。
又，例如於圖35及圖36所示之半導體裝置PK6中，將半導體晶片SC介隔包含焊料之晶片接合材BP12固定於晶片焊墊DP之部分DP2上。圖35係顯示針對圖5之其他變化例之俯視圖，圖36係沿圖35之A-A線之剖面圖。
於如半導體裝置PK6般經由焊料連接半導體晶片SC與晶片焊墊DP之情形時，與使用上述實施形態所說明之銀漿之情形相比，可使 晶片焊墊DP與半導體晶片SC之汲極電極DE(參照圖36)之電性連接可靠性提高。
又，於介隔包含焊料之晶片接合材BP12搭載半導體晶片SC之情形時，自使製造步驟效率化之觀點而言，為使集中於半導體晶片SC與晶片焊墊DP之連接界面之應力分散而設置於部分DP1之構件(第1構件)PS4較佳為以與晶片接合材BP12相同之焊接材料構成。但是，若於將包含漿料狀之焊料之構件PS4塗佈於晶片焊墊DP之部分DP1後，進行回焊處理而使構件PS4熔融，則焊接材沿晶片焊墊DP之上表面DPt擴展，難以加厚構件PS4之厚度。因此，於將包含焊料之構件PS4固定於晶片焊墊DP之部分DP1之情形時，較佳為介隔構件PS4，固定以與構件PS4不同之材料構成之構件PS5(圖35中標註點圖案而顯示之構件)。
又，構件PS5較佳為以金屬材料構成，以使構件PS4所含之焊接成分易潤濕。藉此，因可抑制包含焊料之構件PS4沿晶片焊墊DP之上表面DPt擴展，故可加厚將構件PS2與構件PS3視作一體物之情形時之厚度。
又，於將包含焊料之晶片接合材BP12固定於晶片焊墊DP上之情形時，若如圖5所示之半導體裝置PK1般將金屬CM1形成於晶片焊墊DP上，則因晶片接合材BP1(及構件PS4)變得易沿金屬膜CM1擴展，故變得難以控制半導體晶片SC之搭載位置。另一方面，無法如上述實施形態所說明般，為將平面尺寸不同之複數種半導體晶片SC搭載於共通之晶片焊墊DP而預先設定半導體晶片SC之搭載預定區域。因此，於使用包含焊料之晶片接合材BP12之情形時，較佳為不於晶片焊墊DP之上表面DPt形成圖5所示之金屬膜CM1，使作為基材之銅或銅合金露出。
又，半導體裝置PK6係半導體晶片SC之源極電極焊墊SE與源極 用之引線LDs經由例如包含銅(Cu)之金屬夾具(導電性構件、金屬板)MB2連接。金屬夾具MB2係以跨及半導體晶片SC之側面SCs1之方式配置，且一部分經由導電性之連接材SDp1而與半導體晶片SC之源極電極焊墊SE電性連接，另一部分經由導電性之連接材SDp2而與源極用之引線LDs之連接部RB1之上表面RBt電性連接。關於金屬夾具MB2，對金屬板實施壓製加工或蝕刻加工等加工處理，以預先成形之狀態搭載於半導體晶片SC上，故與圖5所示之金屬帶MB1相比可形成複雜之形狀。
又，導電性之連接材SDp1、連接材SDp2可分別使用焊接材。該情形時，於半導體裝置PK6之製造步驟中，於介隔漿料狀之焊料(成為焊接漿料或焊接膏)將半導體晶片SC及構件PS5配置於晶片焊墊DP上之後，於進行回焊處理前，經由連接材SDp1、SDp2配置金屬夾具MB2。其後，藉由進行回焊處理，使晶片接合材BP12、構件PS4、連接材SDp1、及連接材SDp2統一熔融。接著，若將晶片接合材BP12冷卻，則半導體晶片SC介隔晶片接合材BP12與晶片焊墊DP電性連接，且固定於晶片焊墊DP上。又，構件PS5介隔構件PS4固定於晶片焊墊DP之部分DP1上。又，金屬夾具MB2之一部分經由連接材SDp1而與源極電極焊墊SE電性連接，且金屬夾具MB2之另一部分經由連接材SDp2而與源極用之引線LDs電性連接。
又，於半導體裝置PK6之製造步驟中，因有於回焊步驟後進行洗淨步驟之情形，故打線接合步驟係於進行回焊步驟後之洗淨步驟後進行。
圖35及圖36所示之半導體裝置PK6除上述之不同點外，與上述實施形態所說明之PS1相同。因此，省略與上述實施形態重複之說明及圖示。
其次，於上述實施形態中說明了如下之實施態樣，即，如圖5所 示，於俯視下沿Y方向，將源極用引線LDs、晶片焊墊DP、汲極用引線LDd以依序並排之方式排列，閘極用引線LDg配置為與源極用引線LDs相鄰且為汲極用引線LDd之相反側，但端子排列可應用多種變化例。
例如，於圖37所示之半導體裝置PK7中，沿Y方向將源極用引線LDs、晶片焊墊DP、及閘極用引線LDg以依序並排之方式排列。圖37係顯示針對圖5之其他變化例之透射俯視圖。又，圖38係沿圖37之A-A線之剖面圖。
半導體裝置PK7係如圖5所示之引線LDd般，不具有以自晶片焊墊DP延伸之方式形成之端子，且晶片焊墊DP係作為汲極端子而發揮功能。又，半導體裝置PK7具有與半導體裝置PK7所具有之其他構件電性分離(換言之，呈電性浮動)之引線LD。
於如半導體裝置PK7般之端子排列之情形時，電性連接半導體晶片SC與閘極用引線LDg之導線MW1係以於俯視下跨及構件PS4及構件PS5之方式形成。因此，於半導體裝置PK7之製造步驟中，自防止於固定構件PS4、PS5時導線MW1損傷之觀點而言，較佳於先固定構件PS4、PS5後，進行打線接合步驟。
圖37及圖38所示之半導體裝置PK7除上述之不同點外，與使用圖35及圖36說明之半導體裝置PK6相同。因此，省略重複之說明及圖示。
其次，於上述實施形態中，說明了於一個封裝(密封體MR)內搭載一個半導體晶片SC之實施態樣。然而，亦可應用於在一個封裝內搭載複數個半導體晶片SC之半導體裝置。
於例如圖39所示之半導體裝置PK8中，沿X方向將半導體晶片SC1與半導體晶片SC2係以鄰接之方式搭載。圖39係顯示針對圖5之其他變化例之透視俯視圖。於如半導體裝置PK8般在一個晶片焊墊DP搭 載有複數個半導體晶片SC之情形時，藉由使複數個半導體晶片SC之各者與構件PS1以呈上述實施形態所說明之關係之方式配置，而獲得上述實施形態所說明之效果。例如，只要於晶片焊墊DP之部分DP2固定構件PS1，且於俯視下在晶片焊墊DP之周緣部與半導體晶片SC1之間配置構件PS1，則可抑制半導體晶片SC1與晶片焊墊DP之接著界面之損傷。又，只要於晶片焊墊DP之部分DP2固定構件PS1，且於俯視下在晶片焊墊DP之周緣部與半導體晶片SC2之間配置構件PS1，則可抑制半導體晶片SC2與晶片焊墊DP之接著界面之損傷。
此外，雖省略重複之說明，但藉由將上述實施形態或作為變化例進行說明之實施態樣應用於半導體晶片SC1、SC2之各者，可獲得上述實施形態或變化例中所說明之效果。
其次，於上述實施形態中，對應用於將晶片焊墊DP之下表面DPb之至少一部分自密封體MR露出之晶片焊墊露出型之半導體裝置之實施態樣進行了說明。然而，作為變化例，亦可於晶片焊墊DP之下表面DPb之整體被密封體MR密封之半導體裝置中，應用上述實施形態或作為變化例說明之技術。如上述實施形態中說明般，於晶片焊墊DP之下表面DPb之整體被密封體MR密封之情形時，藉由以包圍晶片焊墊DP之方式形成密封體MR，便於抑制晶片焊墊DP之熱膨脹、熱收縮。因此，晶片焊墊DP與密封體MR之密接界面不易產生剝離，且半導體晶片SC與晶片焊墊DP之接著界面亦不易產生損傷。然而，例如於密封體MR與晶片焊墊DP之線膨脹係數之差較大之情形時，即使晶片焊墊DP之下表面DPb之整體被密封體MR密封，亦有產生晶片焊墊DP與密封體MR之剝離之可能性。該情形時，藉由應用上述實施形態或作為變化例說明之技術，可抑制半導體晶片SC與晶片焊墊DP之接著界面之損傷。
以上，雖基於實施形態具體地說明瞭由本發明者完成之發明， 但本發明並不限定於上述實施形態，除上述例示出之變化例外，當然可在不脫離其主旨之範圍內進行各種變更。
又，若送出有關上述實施形態所說明之半導體裝置之製造方法之技術性思想，則可以下述方式表現。
[附記1]
一種半導體裝置之製造方法，其包含：(a)步驟，其準備引線框架，該引線框架係將晶片搭載部與複數個外部端子支持於框部而形成，該晶片搭載部具有第1主面、及位於上述第1主面之相反側之第2主面，該等複數個外部端子於俯視下沿第1方向與上述晶片搭載部並排配置，且沿與上述第1方向正交之第2方向分別並排配置；(b)步驟，其係於上述(a)步驟後，於上述晶片搭載部之第1部分之上述第1主面上配置第1構件；(c)步驟，其係於上述(a)步驟後，將具有形成有第1電極焊墊之第1面與位於上述第1面相反側之第2面之半導體晶片，以上述第2面與上述晶片搭載部之上述第1主面對向之方式，介隔接著材搭載於上述晶片搭載部之第2部分；(d)步驟，其係於上述(b)及(c)步驟後，將上述半導體晶片之上述第1電極焊墊與上述複數個外部端子中之第1外部端子經由第1導電性構件電性連接；及(e)步驟，其係密封上述半導體晶片、上述晶片搭載部之上述第1主面、上述複數個外部端子之各者之一部分、及上述第1導電性構件，而形成密封體；且於俯視下，上述晶片搭載部之上述第2部分配置於上述第1部分與上述第1外部端子之間；於俯視下，上述第1方向上之上述晶片搭載部之上述第1部分之 長度，長於上述第1方向上之上述半導體晶片之長度；於上述(e)步驟後，上述第1構件與上述晶片搭載部以外之端子電性分離。
[附記2]
如附記1之半導體裝置之製造方法，其中於上述(c)步驟中，以於俯視下上述第1方向上之上述晶片搭載部之上述第1部分之長度，長於上述第2方向上之自上述半導體晶片之周緣部至上述晶片焊墊之周緣部之距離之方式搭載上述半導體晶片。
[附記3]
如附記2之半導體裝置之製造方法，其中於上述(c)步驟中，以於俯視下上述第1方向上之自上述半導體晶片至上述第1構件之距離短於上述第1方向上之上述半導體晶片之長度之方式搭載上述半導體晶片。
[附記4]
如附記3之半導體裝置之製造方法，其中於上述(b)步驟中，以於俯視下上述第2方向上之上述第1構件之長度變得長於上述(c)步驟中所要搭載之上述半導體晶片之上述第2方向上之長度之方式進行。
[附記5]
如附記4之半導體裝置之製造方法，其中於上述(e)步驟中，以上述晶片搭載部之上述第2主面之一部分自上述密封體露出之方式進行。
[附記6]
如附記3之半導體裝置之製造方法，其中於上述(b)步驟中，以於俯視下上述第1構件沿上述1方向配置複數個之方式，且以各者之分離距離短於上述第1方向上之上述半導體 晶片之長度之方式進行。
[附記7]
如附記1之半導體裝置之製造方法，其中上述第1構件以與上述接著材相同之材料構成。
[附記8]
如附記7之半導體裝置之製造方法，其中上述第1構件及上述接著材係含有複數個銀粒子之導電性接著材。
[附記9]
如附記1之半導體裝置之製造方法，其中上述半導體晶片之厚度薄於上述晶片搭載部之厚度。
[附記10]
如附記9之半導體裝置之製造方法，其中上述半導體晶片之厚度為100μm以下。
[附記11]
如附記1之半導體裝置之製造方法，其係於上述半導體晶片之上述第1面形成第2電極焊墊；於上述半導體晶片之上述第2面形成第3電極；上述(c)步驟包含介隔上述接著材將上述晶片搭載部之上述第1主面與上述半導體晶片之上述第3電極電性連接的步驟；上述(d)步驟包含將上述半導體晶片之上述第2電極焊墊與上述複數個外部端子中之第2外部端子電性連接的步驟；上述(e)步驟係以上述晶片搭載部之上述第2主面之一部分自上述密封體露出之方式進行。
[附記12]
如附記11之半導體裝置之製造方法，其中 上述半導體晶片包含縱型通道構造之MOSFET；上述第1電極焊墊與上述MOSFET之源極電極電性連接；上述第2電極焊墊與上述MOSFET之閘極電極電性連接；上述第3電極為上述MOSFET之閘極電極。
[附記13]
如附記11之半導體裝置之製造方法，其中於上述(e)步驟後，上述第1外部端子、上述第2外部端子、及上述晶片搭載部之上述第2主面之自上述密封體露出之部分，具有在將上述半導體裝置安裝於安裝基板時可焊接之部分。
[附記14]
如附記1之半導體裝置之製造方法，其中上述(c)步驟包含於上述晶片搭載部之上述第1部分之上述第1主面上介隔上述第1構件搭載以與上述第1構件不同之材料構成之第2構件的步驟。
[附記15]
如附記1之半導體裝置之製造方法，其中於上述晶片搭載部之上述第1主面上形成金屬膜；上述(b)步驟包含將上述第1構件供給至上述金屬膜上的步驟；上述(c)步驟包含將上述接著材供給至上述金屬膜上的步驟。
BP1‧‧‧晶片接合材
CM1‧‧‧金屬膜
DP‧‧‧晶片焊墊
DP1‧‧‧部分
DP2‧‧‧部分
DPs1‧‧‧側面
DPs2‧‧‧側面
DPs3‧‧‧側面
DPs4‧‧‧側面
DPt‧‧‧上表面
L1‧‧‧長度
L2‧‧‧長度
L3‧‧‧長度
Lc1‧‧‧長度
Lc2‧‧‧長度
LD‧‧‧引線
LDs‧‧‧引線
LDt‧‧‧上表面
Lps1‧‧‧長度
P1‧‧‧分離距離
PS1‧‧‧構件
RB1‧‧‧連接部
RBt‧‧‧上表面
SC‧‧‧半導體晶片
SCs1‧‧‧側面
SCs2‧‧‧側面
SCs3‧‧‧側面
SCs4‧‧‧側面
SCt‧‧‧正面

Claims (20)

  1. 一種半導體裝置，其包含：半導體晶片，其具有形成有第1電極焊墊之第1面、及位於上述第1面之相反側之第2面；晶片搭載部，其具有介隔接著材搭載有上述半導體晶片之第1主面、及位於上述第1主面之相反側之第2主面；複數個外部端子，其等於俯視下沿第1方向與上述晶片搭載部並排配置，且沿與上述第1方向正交之第2方向分別並排配置；第1導電性構件，其將上述半導體晶片之上述第1電極與上述複數個外部端子中之第1外部端子電性連接；及密封體，其密封上述半導體晶片、上述晶片搭載部之上述第1主面、上述複數個外部端子之各者之一部分、及上述第1導電性構件；且上述晶片搭載部具有第1部分及第2部分，該第2部分配置於上述第1部分與上述第1端子之間，且於其上述第1主面搭載有上述半導體晶片；於上述第1部分之上述第1主面上，固定與上述晶片搭載部以外之端子電性分離之第1構件；於俯視下，上述第1方向上之上述晶片搭載部之上述第1部分之長度，長於上述第1方向上之上述半導體晶片之長度。
  2. 如請求項1之半導體裝置，其中於俯視下，上述第1方向上之上述晶片搭載部之上述第1部分之長度，長於上述第2方向上之自上述半導體晶片之周緣部至上述晶片焊墊之周緣部之距離。
  3. 如請求項2之半導體裝置，其中 於俯視下，上述第1方向上之自上述半導體晶片至上述第1構件之距離短於上述第1方向上之上述半導體晶片之長度。
  4. 如請求項3之半導體裝置，其中於俯視下，上述第2方向上之上述第1構件之長度長於上述第2方向上之上述半導體晶片之長度。
  5. 如請求項4之半導體裝置，其中上述晶片搭載部之上述第2主面之一部分自上述密封體露出。
  6. 如請求項3之半導體裝置，其中於俯視下，上述第1構件沿上述1方向固定有複數個，且各者之分離距離短於上述第1方向上之上述半導體晶片之長度。
  7. 如請求項1之半導體裝置，其中上述第1構件由與上述接著材相同之材料構成。
  8. 如請求項7之半導體裝置，其中上述第1構件及上述接著材係含有複數個銀粒子(Ag填料)之導電性接著材。
  9. 如請求項1之半導體裝置，其中上述半導體晶片之厚度薄於上述晶片搭載部之厚度。
  10. 如請求項9之半導體裝置，其中上述半導體晶片之厚度為100μm以下。
  11. 如請求項1之半導體裝置，其中於上述半導體晶片之上述第1面，形成與上述複數個外部端子中之第2外部端子電性連接之第2電極焊墊；上述半導體晶片之上述第2面形成介隔上述接著材與上述晶片搭載部之上述第1主面電性連接之第3電極；上述晶片搭載部之上述第2主面之一部分自上述密封體露出。
  12. 如請求項11之半導體裝置，其中 上述半導體晶片包含縱型通道構造之MOSFET；上述第1電極焊墊與上述MOSFET之源極電極電性連接；上述第2電極焊墊與上述MOSFET之閘極電極電性連接；上述第3電極為上述MOSFET之閘極電極。
  13. 如請求項11之半導體裝置，其中上述第1外部端子、上述第2外部端子、及上述晶片搭載部之上述第2主面之自上述密封體露出之部分，具有於將上述半導體裝置安裝於安裝基板時可焊接之部分。
  14. 如請求項1之半導體裝置，其中於上述晶片搭載部之上述第1部分之上述第1主面上，介隔上述第1構件固定有由與上述第1構件不同之材料構成之第2構件。
  15. 如請求項1之半導體裝置，其中於上述晶片搭載部之上述第1主面上形成金屬膜；且上述接著材與上述第1構件固定於上述金屬膜上。
  16. 一種半導體裝置，其包含：半導體晶片，其具備縱型通道構造之MOSFET，且具有形成有源極電極焊墊與閘極電極焊墊之第1面、及位於上述第1面之相反側且形成有汲極電極之第2面；晶片搭載部，其具有介隔接著材搭載且電性連接上述半導體晶片之第1主面、及位於上述第1主面之相反側之第2主面；複數條引線，其等於俯視下，沿第1方向與上述晶片搭載部並排配置，且沿與上述第1方向正交之第2方向分別並排配置；第1導電性構件，其將上述半導體晶片之上述源極電極與上述複數條引線中之源極引線電性連接；第2導電性構件，其將上述半導體晶片之上述閘極電極與上述複數條引線中之閘極引線電性連接；及 密封體，其密封上述半導體晶片、上述晶片搭載部之上述第1主面、上述複數條引線之各者之一部分、上述第1導電性構件及上述第2導電性構件；且上述晶片搭載部之上述第2主面之一部分自上述密封體露出；上述晶片搭載部具有第1部分及第2部分，該第2部分配置於上述第1部分與上述第1端子之間，且於其上述第1主面搭載上述半導體晶片；於上述第1部分之上述第1主面上，固定與上述晶片搭載部以外之端子電性分離之以與上述接著材相同之材料構成之第1構件；於俯視下，上述第1方向上之上述晶片搭載部之上述第1部分之長度長於上述第1方向上之上述半導體晶片之長度。
  17. 如請求項16之半導體裝置，其中上述接著材與上述第1構件係含有複數個銀粒子之導電性接著材。
  18. 如請求項17之半導體裝置，其中上述第1導電性構件為金屬箔，上述第2導電性構件為金屬導線。
  19. 如請求項18之半導體裝置，其中上述晶片搭載部、上述源極引線、及上述閘極引線由以銅為主要成分之材料構成；於上述晶片搭載部之上述第1主面之固定上述接著材與上述第1構件之部分、與上述閘極引線之連接上述第2導電性構件之部分形成金屬膜；於上述源極引線之連接上述第1導電性構件之部分未形成上述金屬膜。
  20. 如請求項18之半導體裝置，其中於俯視下，上述半導體晶片為長方形形狀；上述半導體晶片係以其長邊沿著上述第2方向之方式搭載於上述晶片搭載部之上述第1主面上；於俯視下，上述第1導電性構件與上述半導體晶片之上述長邊交叉。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105723619A (zh) 2013-11-20 2016-06-29 罗姆股份有限公司 开关器件及电子电路
DE102015104956A1 (de) * 2015-03-31 2016-10-06 Infineon Technologies Ag Gedruckte Leiterplatte mit einem Leiterrahmen mit eingefügten gehäusten Halbleiterchips
US9754864B1 (en) * 2016-06-23 2017-09-05 Alpha And Omega Semiconductor Incorporated Semiconductor power device having single in-line lead module and method of making the same
JP2019012755A (ja) * 2017-06-29 2019-01-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
CN111316428B (zh) * 2017-10-26 2023-10-20 新电元工业株式会社 半导体装置以及半导体装置的制造方法
US10692801B2 (en) * 2018-05-31 2020-06-23 Infineon Technologies Austria Ag Bond pad and clip configuration for packaged semiconductor device
DE102018124497B4 (de) * 2018-10-04 2022-06-30 Infineon Technologies Ag Halbleitervorrichtung und Verfahren zum Bilden einer Halbleitervorrichtung
JP7109347B2 (ja) * 2018-12-03 2022-07-29 三菱電機株式会社 半導体装置および電力変換装置
WO2020261969A1 (ja) * 2019-06-24 2020-12-30 株式会社村田製作所 電子モジュール
KR102152014B1 (ko) * 2020-03-03 2020-09-04 제엠제코(주) 가압형 반도체 패키지 및 이의 제조방법
US11222858B1 (en) * 2020-06-19 2022-01-11 Alpha And Omega Semiconductor International Lp Semiconductor package having enlarged gate pad and method of making the same

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2981390B2 (ja) * 1993-12-27 1999-11-22 シャープ株式会社 電力半導体装置
JP3179374B2 (ja) * 1997-06-30 2001-06-25 日本電気株式会社 半導体装置用リードフレームおよび半導体装置
JP3678392B2 (ja) * 1998-04-09 2005-08-03 株式会社東芝 光半導体装置
JP2000068303A (ja) 1998-08-24 2000-03-03 Sony Corp 半導体装置の製造方法
JP2000286379A (ja) * 1999-01-28 2000-10-13 Fujitsu Ltd 半導体装置及びその製造方法
JP3841768B2 (ja) 2003-05-22 2006-11-01 新光電気工業株式会社 パッケージ部品及び半導体パッケージ
DE102005016830A1 (de) * 2004-04-14 2005-11-03 Denso Corp., Kariya Halbleitervorrichtung und Verfahren zu ihrer Herstellung
JP4329678B2 (ja) 2004-11-11 2009-09-09 株式会社デンソー 半導体装置に用いるリードフレームの製造方法
JP4262672B2 (ja) * 2004-12-24 2009-05-13 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP4547279B2 (ja) * 2005-02-08 2010-09-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2006253374A (ja) * 2005-03-10 2006-09-21 Matsushita Electric Ind Co Ltd 樹脂封止型半導体装置
JP4857594B2 (ja) 2005-04-26 2012-01-18 大日本印刷株式会社 回路部材、及び回路部材の製造方法
US20070035019A1 (en) * 2005-08-15 2007-02-15 Semiconductor Components Industries, Llc. Semiconductor component and method of manufacture
JP4916745B2 (ja) * 2006-03-28 2012-04-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2008270455A (ja) * 2007-04-19 2008-11-06 Hitachi Ltd パワー半導体モジュール
JP2013016837A (ja) * 2007-04-27 2013-01-24 Renesas Electronics Corp 半導体装置
JP2009200338A (ja) * 2008-02-22 2009-09-03 Renesas Technology Corp 半導体装置の製造方法
JP2010034294A (ja) * 2008-07-29 2010-02-12 Nec Electronics Corp 半導体装置およびその設計方法
JP5107839B2 (ja) * 2008-09-10 2012-12-26 ルネサスエレクトロニクス株式会社 半導体装置
JP2010135723A (ja) 2008-10-29 2010-06-17 Panasonic Corp 半導体装置
JP2010245417A (ja) 2009-04-09 2010-10-28 Renesas Electronics Corp 半導体装置およびその製造方法
JP5271778B2 (ja) * 2009-04-10 2013-08-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5467799B2 (ja) * 2009-05-14 2014-04-09 ルネサスエレクトロニクス株式会社 半導体装置
CN102484080B (zh) * 2009-06-18 2015-07-22 罗姆股份有限公司 半导体装置
JP5569097B2 (ja) * 2010-03-29 2014-08-13 富士通セミコンダクター株式会社 半導体装置及びリードフレーム
JP5868043B2 (ja) * 2011-07-04 2016-02-24 ルネサスエレクトロニクス株式会社 半導体装置
JP5863174B2 (ja) * 2012-03-01 2016-02-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6161251B2 (ja) * 2012-10-17 2017-07-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5493021B2 (ja) * 2013-03-08 2014-05-14 ルネサスエレクトロニクス株式会社 半導体装置

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