CN105264659A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN105264659A CN105264659A CN201380076866.4A CN201380076866A CN105264659A CN 105264659 A CN105264659 A CN 105264659A CN 201380076866 A CN201380076866 A CN 201380076866A CN 105264659 A CN105264659 A CN 105264659A
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- semiconductor chip
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Abstract
一种实施方式的半导体装置是用树脂密封了在芯片搭载部上搭载了的半导体芯片的半导体装置,其中,在沿着第1方向的上述半导体芯片的边缘部与上述芯片搭载部的边缘部之间的芯片搭载面侧,固定了第1部件。另外,上述第1部件被上述树脂密封。另外,在俯视时,上述第1方向上的上述芯片搭载部的上述第1部分的长度比上述第1方向上的上述半导体芯片的长度更长。
Description
技术领域
本发明涉及半导体装置的技术,涉及例如适用于在平面面积比半导体芯片的安装面更大的管芯焊盘上搭载半导体芯片的半导体装置的有效技术。
背景技术
在日本特开2010-2245417号公报(专利文献1)、日本特开2006-310397号公报专利文献2)、日本特开2006-140265号公报(专利文献3)、日本特开2004-349497号公报(专利文献4)或者日本特开2000-68303号公报(专利文献5)中,记载了在树脂密封型的半导体封装中,使管芯焊盘的与密封体的密合面粗糙化。
专利文献1:日本特开2010-2245417号公报
专利文献2:日本特开2006-310397号公报
专利文献3:日本特开2006-140265号公报
专利文献4:日本特开2004-349497号公报
专利文献5:日本特开2000-68303号公报
发明内容
本申请发明者研究了在管芯焊盘上搭载半导体芯片而提高用树脂密封了的半导体装置的性能的技术。其结果,本申请发明者发现了如果通过使半导体芯片的平面尺寸小型化而管芯焊盘的未搭载半导体芯片的区域的面积变大,则半导体芯片和管芯焊盘的粘结面容易损伤。
其他课题和新的特征根据本说明书的记述以及附图将更加明确。
在一种实施方式的半导体装置中,在俯视时,在半导体芯片的边缘部与管芯焊盘的边缘部之间的芯片搭载面侧,固定了第1部件。
根据上述一种实施方式,能够抑制半导体芯片和管芯焊盘的粘结面的损伤。
附图说明
图1是示意地示出一种实施方式的半导体装置具备的电路的一个例子的说明图。
图2是示出图1所示的场效应晶体管的元件构造例的主要部分剖面图。
图3是图1所示的半导体装置的俯视图。
图4是图3所示的半导体装置的仰视图。
图5是在去掉了图3所示的密封体的状态下示出半导体装置的内部构造的透视俯视图。
图6是沿着图5的A-A线的剖面图。
图7是沿着图5的B-B线的剖面图。
图8是示出作为针对图5的变形例的在管芯焊盘的未搭载半导体芯片的部分处搭载了部件的状态的主要部分放大俯视图。
图9是示出使用图1~图7说明了的半导体装置的制造工序的概要的说明图。
图10是示出在图9所示的引线框架准备工序中准备的布线基板的整体构造的俯视图。
图11是相当于图10所示的器件形成部一个的量的放大俯视图。
图12是沿着图11的A-A线的放大剖面图。
图13是示出在图11所示的管芯焊盘的一部分处涂覆了银膏的状态的放大俯视图。
图14是沿着图13的A-A线的放大剖面图。
图15是示意地示出在沿着图13的B-B线的放大剖面涂覆银膏的方式的说明图。
图16是示出针对图15的变形例的说明图。
图17是示出通过图16所示的方式形成了的银膏的平面形状的放大俯视图。
图18是示出在图13所示的管芯焊盘上搭载了半导体芯片的状态的放大俯视图。
图19是沿着图18的A-A线的放大剖面图。
图20是示出将图18所示的半导体芯片和引线经由金属条带电连接了的状态的放大俯视图。
图21是示出在沿着图20的A-A线的剖面连接金属条带的状态的放大剖面图。
图22是关于沿着图20的A-A线的剖面,在接着图21的阶段示出的放大剖面图。
图23是示出经由金属导线电连接了图20所示的半导体芯片和栅极用的引线的状态的放大俯视图。
图24是示出在沿着图23的A-A线的剖面连接了导线的状态的放大剖面图。
图25是示出形成了对图23所示的半导体芯片以及金属条带进行密封的密封体的状态的放大俯视图。
图26是示出在沿着图25的A-A线的剖面,在成型模具内配置了引线框架的状态的放大剖面图。
图27是示出在图26所示的管芯焊盘以及引线的从密封体的露出面形成了金属膜的状态的放大剖面图。
图28是示出使图27所示的引线框架单片化了的状态的放大俯视图。
图29是示出针对图6的变形例的剖面图。
图30是示出针对图5的变形例的透视俯视图。
图31是沿着图30的A-A线的剖面图。
图32是示出针对图5的其他变形例的俯视图。
图33是沿着图32的A-A线的剖面图。
图34是示出针对图33的变形例的俯视图。
图35是示出针对图5的其他变形例的俯视图。
图36是示出沿着图35的A-A线的剖面图。
图37是示出针对图5的其他变形例的俯视图。
图38是沿着图37的A-A线的剖面图。
图39是示出针对图5的其他变形例的透视俯视图。
图40是示出作为针对图5的比较例的半导体装置的内部构造的透视俯视图。
符号说明
20:金属带;20a:压痕;21:卷盘;23:结合工具;24:切断刃;25:支撑台;25a:片保持面;25b:条带连接部保持面;26:结合工具;27:导线;31:成型模具;32:上模(第1模具);33:下模(第2模具);34:空腔;BP1、BP2:管芯结合材料(粘结材料);CH:沟道形成区域;CM1、CM2:金属膜(镀层膜、镀层金属膜);D:漏极;DE:漏电极;DP:管芯焊盘(芯片搭载部);DP1、DP2:部分;DPb:下表面(主面);DPs1、DPs2、DPs3、DPs4:侧面;DPt:上表面(主面);EP:外延层;G:栅电极;GE:栅电极焊盘;GI:栅极绝缘膜;L1、L2、L3、Lc1:长度(距离);LD:引线(端子、外部端子);LDb:下表面(安装面);LDd:引线(漏极引线、漏极端子);LDg:引线(栅极引线、栅极端子);LDs:引线(源极引线、源极端子);LDt:上表面;LF:引线框架;LF:焊料溶液的引线框架;LFa:器件形成部;LFb:外框;LFc:框部;Lps1:长度;MB1:金属条带(导电性部件、金属箔、带状金属部件);MB2:金属夹片(导电性部件、金属板);MR:密封体(树脂体);MRb:下表面(安装面);MRs:侧面;MRt:上表面;MW1:导线(金属导线);NZ1、NZ2:喷嘴;P1、P2:间隔距离;PK1、PK2、PK3、PK6、PK7、PK8、PKh1:半导体装置;PS1、PS2.PS3、PS4、PS5:部件;PSb:搭载面;Q1:晶体管;RB1:连接部(条带连接部);RB2:连接部(导线连接部);RBb:下表面;RBt:上表面(连接面、条带连接面、导线连接面);S:源极;SC、SC1、SC2:半导体芯片;SCb:背面(面);SCs1、SCs2、SCs3、SCs4:侧面;SCt:表面(面);SD:金属膜(外装镀层膜);SDp1、SDp2:连接材料;SE:源电极焊盘;SL1、SL2:偏置部(弯曲加工部、倾斜部、高低差部);SR:源极区域;TL:悬置引线;TN1、TN2:端子部;TR1:沟槽(开口部、槽);Wa:主面;WH:半导体基板。
具体实施方式
(本申请中的记载形式、基本的用语、用法的说明)
在本申请中,关于实施方式的记载,根据需要,为便于说明分成多个分段等而记载,但除了特别明示了并非如此的意思的情况以外,它们并非相互独立,不论记载在前或后,单一的例子的各部分、一方是另一方的一部分详细或者一部分或者全部的变形例等。另外,原则上,同样的部分省略反复的说明。另外,关于实施方式中的各构成要素,除了特别明示了并非如此的意思的情况、理论上限定于该数量的情况以及根据文脉明确地并非如此的情况以外,并非必须。
同样地,在实施方式等的记载中,关于材料、组成等,对于“由A构成的X”等,除了特别明示了并非如此的意思的情况以及根据文脉明确地并非如此的情况以外,不排除包括A以外的要素的部分。例如,对于成分,是“包含A作为主要成分的X”等意义。例如,对于“硅部件”等,也不限于纯粹的硅,当然还包括SiGe(硅/锗)合金、其他以硅为主要的成分的多元合金、包含其他添加物等的部件。另外,对于金镀层、Cu层、镍镀层等,除了并非如此的意思、特别明示的情况以外,并非纯粹的物质,而还包括分别以金、Cu、镍等为主要的成分的部件。
进而,即使在言及特定的数值、数量时,除了特别明示了并非如此的意思的情况、理论上限定于该数量的情况以及根据文脉明确地并非如此的情况以外,既可以是超过其特定的数值的数值,也可以是小于其特定的数值的数值。
另外,在实施方式的各图中,同一或者同样的部分用同一或者类似的记号或者参照编号表示,说明原则上不反复。
另外,在附图中,在反而变得繁杂的情况下或者在与空隙的区分明确的情况下,即便是剖面也有时省略阴影线等。与其关联地,在根据说明等明确的情况等下,即使平面上关闭的孔,也有时省略背景的轮廓线。进而,即便并非剖面,为了明示并非空隙或者明示区域的边界,有时附加阴影线、点图案。
<电路结构>
在本实施方式中,作为半导体装置的例子,举出嵌入到电源电路等电力控制电路而被用作例如开关元件的、被称为所谓功率器件的电力控制用的半导体装置来进行说明。图1是示意地示出本实施方式的半导体装置具备的电路的一个例子的说明图。另外,图2是示出图1所示的场效应晶体管的元件构造例的主要部分剖面图。
在被称为功率器件的电力控制用的半导体装置中,有例如具有二极管、晶闸管或者晶体管等半导体元件的例子。本实施方式的半导体装置PK1如图1所示,具有形成了晶体管Q1的半导体芯片SC。在图1以及图2所示的例子中,形成于半导体芯片SC的晶体管Q1是场效应晶体管、详细而言MOSFET(MetalOxideSemiconductorFieldEffectTransistor,金属氧化物半导体场效应晶体管)。在功率器件中,晶体管被用作例如开关元件。在功率器件中使用的MOSFET被称为功率MOSFET。
上述MOSFET记载为广泛表示在栅极绝缘膜上配置了由导电性材料构成的栅电极的构造的场效应晶体管的用语。因此,即使在记载为MOSFET的情况下,也不排除氧化膜以外的栅极绝缘膜。另外,即使在记载为MOSFET的情况下,也不排除例如多晶硅等金属以外的栅电极材料。
另外,图1所示的晶体管Q1由例如图2所示的n沟道型的场效应晶体管形成。图2是示出图1所示的场效应晶体管的元件构造例的主要部分剖面图。
在图2所示的例子中,在由例如n型单结晶硅构成的半导体基板WH的主面Wa上,形成了n-型的外延层EP。该半导体基板WH以及外延层EP构成MOSFET的漏极区域(与图1所示的漏极D相当的区域)。该漏极区域与在半导体芯片SC的背面侧形成了的漏电极DE电连接。
在外延层EP上,形成了作为p+型的半导体区域的沟道形成区域CH,在该沟道形成区域CH上,形成了作为n+型的半导体区域的源极区域(与图1所示的源极S相当的区域)SR。源极区域SR经由引出布线与在半导体芯片SC的主面侧形成了的源电极焊盘SE电连接。另外,在半导体基板WH上层叠了的半导体区域中,形成了从源极区域SR的上表面贯通沟道形成区域CH而到达外延层EP的内部的沟槽(开口部、槽)TR1。
另外,在沟槽TR1的内壁形成了栅极绝缘膜GI。另外,在栅极绝缘膜GI上,形成了以埋入沟槽TR1的方式层叠了的栅电极G。栅电极G经由引出布线与半导体芯片SC的栅电极焊盘GE电连接。
另外,在晶体管Q1中,夹着沟道形成区域CH,在厚度方向上配置漏极区域和源极区域SR,所以在厚度方向上形成沟道(以下称为纵向沟道构造)。在该情况下,相比于沿着主面Wa形成沟道的场效应晶体管,能够降低俯视时的元件的占有面积。因此,能够降低半导体芯片SC的平面尺寸。
另外,在上述纵向沟道构造的情况下,在俯视时,能够增加每单位面积的沟道宽度,所以能够降低导通电阻。另外,图2是示出场效应晶体管的元件构造的图,在图1所示的半导体芯片SC中,并联连接了具有例如图2所示的元件构造的多个(多数)晶体管Q1。由此,能够构成流过超过例如1安培那样的大电流的功率MOSFET。
如上述那样,在将纵向沟道构造的多个晶体管Q1并联连接而构成MOSFET的情况下,MOSFET的电气特性(主要是耐压特性、导通电阻特性、电容特性)根据半导体芯片SC的平面尺寸而变化。例如,如果增大半导体芯片SC的平面面积,则并联连接了的晶体管Q1的单元数(即元件的数量)增加,所以导通电阻降低,电容增大。
<半导体装置>
接下来,说明图1所示的半导体装置PK1的封装构造。图3是图1所示的半导体装置的俯视图。另外,图4是图3所示的半导体装置的仰视图。另外,图5是在去掉了图3所示的密封体的状态下,示出半导体装置的内部构造的透视俯视图。另外,图6是沿着图5的A-A线的剖面图。另外,图7是沿着图5的B-B线的剖面图。
关于上述MOSFET的电气特性,根据半导体装置PK1(参照图1)的用途,要求规格不同。因此,为了应对于不同的要求规格,半导体装置PK1的封装构造优选做成能够搭载平面尺寸不同的多个种类的半导体芯片SC的构造。另一方面,半导体装置PK1的端子排列、平面尺寸优选无论半导体芯片SC的平面尺寸多少都共同化。例如,通过使半导体芯片SC以外的零件共同化,能够提高制造效率。另外,例如,通过使端子排列共同化,能够使安装半导体装置PK1的安装基板侧的端子排列标准化。另外,例如,如果考虑半导体装置PK1的散热特性,则优选即使在半导体芯片SC的平面尺寸变小的情况下,散热路径的剖面积也不变化。
因此,本申请发明者针对能够搭载平面尺寸不同的多个种类的半导体芯片SC的封装进行了研究。以下,使用图3~图7,说明本实施方式的半导体装置PK1的构造。
半导体装置PK1具有半导体芯片SC(参照图5、图6)、搭载半导体芯片SC的管芯焊盘(芯片搭载部)DP(参照图4~图6)以及作为外部端子的多个引线(端子)LD(参照图4~图6)。另外,半导体芯片SC、管芯焊盘DP的上表面DPt以及多个引线的上表面LDt通过密封体(树脂体)MR被一并地密封。
在本实施方式中,如图5所示,关于多个引线LD,沿着Y方向与管芯焊盘DP并列地配置,并且,沿着与Y方向正交的X方向,分别并列配置。另外,如图5所示,在俯视时,沿着Y方向,以依次排列的方式,排列了源极用的引线(源极引线、源极端子)LDs、管芯焊盘DP、漏极用的引线(漏极引线、漏极端子)LDd。另外,在图5所示的例子中,栅极用的引线(栅极引线、栅极端子)LDg配置于源极用的引线LDs的旁边并且漏极用的引线LDd的相反侧。
如图6所示,半导体芯片SC具有表面(面、第1面)SCt和位于表面SCt的相反侧的背面(面、第2面)SCb。另外,如图5所示,半导体芯片SC的表面SCt(或者图6所示的背面SCb)在俯视时形成四边形,在边缘部具有由侧面SCs1、SCs2、SCs3、SCs4构成的四个侧面。在图5所示的例子中,半导体芯片SC在俯视时形成长方形,沿着X方向配置了长边。
半导体芯片SC具有的四个侧面中的、构成长边的侧面SCs1配置于源极用的引线LDs侧。另外,构成另一个长边的侧面SCs2配置于侧面SCs1的相反侧、即引线LDs的相反侧。另外,以与侧面SCs1、SCs2分别交叉的方式,配置侧面SCs3。另外,在侧面SCs3的相反侧配置侧面SCs4。另外,如图5所示,在半导体芯片SC的表面SCt,形成了与图1所示的源极S电连接的源电极焊盘SE和与图1所示的栅电极G电连接的栅电极焊盘GE。另一方面,如图6所示,在半导体芯片SC的背面SCb,形成了与图1所示的漏极D电连接的漏电极DE。在图6所示的例子中,半导体芯片SC的背面SCb整体成为漏电极DE。
如图2所示,在将半导体芯片SC做成纵向沟道构造的情况下,通过使半导体芯片SC的厚度变薄(减小图6所示的表面SCt和背面SCb的距离),能够降低导通电阻。因此,半导体芯片SC的厚度优选薄,虽然还取决于导通电阻值的规格上的要求,但半导体芯片SC的厚度优选为100μm以下。例如,在图6所示的例子中,半导体芯片SC的厚度是50μm左右,比管芯焊盘DP的厚度更薄。
另外,如图5以及图6所示,半导体装置PK1具有搭载半导体芯片SC的管芯焊盘(芯片搭载部)DP。如图6所示,管芯焊盘DP具有经由管芯结合材料BP1搭载了半导体芯片SC的上表面(芯片搭载面、第1主面)DPt和与上表面DPt相反的一侧的下表面(安装面、第2主面)DPb。另外,如图5所示,管芯焊盘DP的上表面DPt(或者图6所示的背面DPb)在俯视时形成四边形,在边缘部具有由侧面DPs1、DPs2、DPs3、DPs4构成的四个侧面。四个侧面中的侧面DPs1配置于源极用的引线LDs侧。另外,侧面DPs2配置于侧面DPs1的相反侧、即引线LDs的相反侧。另外,以与侧面DPs1、DPs2分别交叉的方式,配置侧面DPs3。沿着管芯焊盘DP的侧面DPs3配置半导体芯片SC的侧面SCs3。另外,在侧面SCs3的相反侧配置侧面SCs4。
另外,管芯焊盘DP与作为漏极端子的引线LDd一体地形成。引线LDd是与图1所示的漏极D电连接的外部端子。另外,如图6所示,在半导体芯片SC的背面SCb形成了的漏电极DE经由由导电性材料构成的管芯结合材料BP1与管芯焊盘DP电连接。另外,在图5所示的例子中,半导体芯片SC的平面尺寸(表面SCt的面积)小于管芯焊盘DP的平面尺寸(上表面DPt的面积)。
另外,如图4以及图6所示,管芯焊盘DP的下表面DPb在密封体MR的下表面MRb,从密封体MR露出。详细而言,在本实施方式中,在管芯焊盘DP的边缘形成了高低差部,管芯焊盘DP的边缘的高低差部被密封体MR密封。因此,管芯焊盘DP的下表面DPb中的一部分从密封体MR露出。通过如本实施方式那样增大管芯焊盘DP的平面尺寸、并且使管芯焊盘DP的下表面DPb从密封体露出,能够提高在半导体芯片SC中产生了的热的散热效率。
另外,通过使作为外部端子的作为引线LDd的管芯焊盘DP的下表面DPb从密封体MR露出,能够增大电流流过的导通路径的剖面积。因此,能够降低导通路径中的阻抗分量。特别,在引线LDd成为与半导体装置PK1具有的电路的输出节点对应的外部端子的情况下,通过降低与引线LDd连接的导通路径的阻抗分量,能够直接地降低输出布线的电力损失,在这一点上是优选的。
另外,在作为管芯焊盘DP的露出面的下表面DPb,形成了用于在将半导体装置PK1安装到未图示的安装基板时提高成为接合材料的焊料材料的湿润性的金属膜(外装镀层膜)SD。在将半导体装置PK1安装到未图示的安装基板(主板)时,作为对半导体装置PK1的多个引线LD和安装基板侧的未图示的端子进行电连接的接合材料,使用例如焊料材料等。根据提高作为接合材料的焊料材料的湿润性的观点,在半导体装置PK1的端子的接合面,分别形成了图5以及图6所示的由例如焊料构成的作为外装镀层膜的金属膜SD。
另外,通过在管芯焊盘DP的边缘部形成高低差部,并对高低差部进行密封,管芯焊盘DP不易从密封体MR脱落。
图5以及图6所示的管芯结合材料(粘结材料)BP1是用于将半导体芯片SC固定到管芯焊盘DP上并且对半导体芯片SC和管芯焊盘DP进行电连接的导电性部件(管芯结合材料)。在本实施方式中,管芯结合材料BP1是含有多个银(Ag)粒子(Ag填料)的被称为所谓银(Ag)膏的导电性的树脂粘结材料。银膏能够通过例如环氧系的热硬化性树脂的粘结力,提高与半导体芯片SC的粘结力,并且经由多个银粒子确保导通路径。
在将半导体装置PK1安装到未图示的安装基板的工序中,为了使未图示的焊料材料熔融而将引线LD和未图示的安装基板侧的端子分别接合,实施被称为回流处理的加热处理。在作为管芯结合材料BP1而使用在树脂中混合了导电性粒子的导电性粘结材料的情况下,即使任意地设定上述回流处理的处理温度,导电性接合材料也不会熔融。因此,能够防止半导体芯片SC和管芯焊盘DP的接合部的管芯结合材料BP1在半导体装置PK1的安装时再熔融所致的不佳状况,在这一点上是优选的。
另外,在本实施方式的情况下,以覆盖管芯焊盘DP的上表面DPt的方式,形成由例如银构成的金属膜(镀层膜、镀层金属膜)CM1,在金属膜CM1上配置了管芯结合材料BP1。金属膜CM1能够通过例如电镀法形成。通过以覆盖管芯焊盘DP的上表面DPt的方式形成金属膜CM1,能够抑制作为管芯焊盘DP的基体材料的铜(Cu)或者铜合金的氧化。另外,在作为管芯结合材料BP1使用银膏的情况下,通过在管芯焊盘DP的上表面DPt形成与银膏的粘结性比作为管芯焊盘DP的基体材料的铜(Cu)或者铜合金更高的金属膜CM1,能够提高管芯结合材料BP1和管芯焊盘DP的粘结强度。
如上述那样,为了应对于不同的要求规格,优选能够制造平面尺寸不同的多个种类的半导体芯片SC,但半导体芯片SC以外的零件优选共同化。因此,在本实施方式中,以覆盖管芯焊盘DP的上表面DPt的大部分的方式,形成了金属膜CM1。由此,即使在搭载平面尺寸比图5所示的更大的半导体芯片SC的情况下,也能够在管芯结合材料BP1与管芯焊盘DP之间,介有金属膜CM1。因此,如图5所示,在搭载平面尺寸小的半导体芯片SC的情况下,相比于搭载半导体芯片的区域,未搭载半导体芯片SC的区域更大。
另外,如图5所示,管芯焊盘DP被悬置引线TL支撑。该悬置引线TL是用于在半导体装置PK1的制造工序中在引线框架的框部LFc固定管芯焊盘DP的支撑部件。
另外,如图5以及图6所示,半导体芯片SC的源电极焊盘SE和引线LDs经由金属条带(导电性部件、金属箔、带状金属部件)MB1电连接。金属条带MB1是相当于连接图1所示的晶体管Q1的源极S和源极用的引线LDs的布线的导电性部件,由例如铝(Al)构成。
详细而言,如图6所示,金属条带MB1的一端被接合到半导体芯片SC的源电极焊盘SE。另一方面,金属条带MB1的与上述一端相反一侧的另一端被接合到在引线LDs的一部分处形成了的连接部(条带连接部)RB1的上表面(连接面、条带连接面)RBt。在图5所示的例子中,半导体芯片SC在俯视时形成长方形,金属条带MB1被配置为与半导体芯片SC的长边交叉。
在金属条带MB1和源电极焊盘SE的接合部,在源电极焊盘SE的最表面露出的金属部件(例如铝)和构成金属条带MB1的例如铝条带形成金属结合而被接合。另一方面,在与金属条带MB1连接的连接部RB1的上表面RBt,构成例如基体材料的铜(Cu)露出,铜(Cu)的露出面和构成金属条带MB1的例如铝条带形成金属结合而被接合。详细情况在后面叙述,在接合金属条带MB1时,通过从结合工具施加超声波,能够形成上述那样的接合部。在将铝条带接合到引线LD的情况下,相比于在接合面形成银的镀层膜,在使构成基体材料的铜露出时,能够提高接合强度。因此,在引线LDs的连接部RB1的上表面RBt,未形成覆盖管芯焊盘DP的上表面DPt的金属膜CM1那样的金属膜,作为基体材料的铜或者铜合金露出。
另外,如图6所示,引线LDs的连接部RB1的上表面RBt的高度配置于比管芯焊盘DP的上表面DPt更高的位置。详细而言,引线LDs具有被连接金属条带MB1的连接部RB1和具有从密封体MR露出的下表面(安装面)LDb的端子部TN1。另外,引线LDs在连接部RB1与端子部TN1之间,具有以使连接部RB1的位置比端子部TN1的位置更高的方式设置了的偏置部(弯曲加工部、倾斜部、高低差部)SL1。因此,连接部RB1的下表面RBb被密封体MR覆盖。换言之,引线LDs的连接部RB1被密封体MR密封。通过这样用密封体MR密封引线LD下表面的一部分,引线LD不易从密封体MR脱落。其结果,能够提高半导体装置PK1的电连接可靠性。
另外,如图5以及图7所示,在管芯焊盘DP的旁边,配置作为与半导体芯片SC的栅电极焊盘GE电连接的外部端子的引线LDg。与管芯焊盘DP相间隔地设置了引线LDg。另外,如图7所示,引线LDg具有作为被接合导线MW1的结合区域的连接部(导线连接部)RB2以及具有从密封体MR露出的下表面LDb的端子部TN1。另外,引线LDg在连接部RB2与端子部TN2之间,具有以使连接部RB2的位置比端子部TN2的位置更高的方式设置了的偏置部(弯曲加工部、倾斜部、高低差部)SL2。因此,连接部RB2的下表面RBb被密封体MR覆盖。
另外,连接栅电极焊盘GE和引线LDg的导线MW1是由例如金(Au)构成的金属线。另外,在引线LD的连接部RB2的上表面(连接面、导线连接面)RBt,形成了由例如银构成的金属膜(镀层膜、镀层金属膜)CM2。通过以覆盖引线LD的连接部RB2的上表面RBt的方式形成金属膜CM2,能够抑制作为引线LD的基体材料的铜(Cu)或者铜合金的氧化。氧化铜膜成为阻碍电、热的传导性的主要原因,所以通过抑制基体材料的氧化,能够提高引线LD的电传导性、热传导性。另外,通过以覆盖连接部RB2的上表面RBt的方式形成金属膜CM2,接合导线MW1时的导线结合性提高。因此,在本实施方式中,在被接合金制的导线MW1的连接部RB2的上表面RBt,选择性地形成了金属膜CM2。另外,在用相同的金属材料分别形成在管芯焊盘DP的上表面DPt形成的金属膜CM1和形成于引线LDg的金属膜CM2的情况下,能够一并地形成这些金属膜CM1以及金属膜CM2。此时,优选在被连接图6所示的铝条带的引线LDs的连接部RB1的上表面RBt,不形成金属膜,所以优选在用未图示的掩膜覆盖了连接部RB1的上表面RBt的状态下形成。
另外,如图6所示,半导体芯片SC、引线LDs的连接部RB1以及金属条带MB1被密封体MR密封。另外,如图7所示,引线LDg的连接部RB2以及导线MW1被密封体MR密封。
密封体MR是对半导体芯片SC、金属条带MB1以及导线MW1进行密封的树脂体,具有上表面MRt(参照图3、图6)以及位于上表面MRt的相反侧的下表面(安装面)MRb(参照图4、图6、图7)。另外,如图3以及图4所示,密封体MR在俯视时形成四边形,具有4个侧面MRs。
密封体MR例如主要由环氧系树脂等热硬化性树脂构成。另外,为了提高密封体MR的特性(例如热影响所致的膨胀特性),例如,还有时在树脂材料中混合二氧化硅(SiO2)粒子等填料粒子。
<管芯焊盘上的布局详细情况>
此处,详细说明图5所示的管芯焊盘DP上的布局。图8是示出作为针对图5的变形例的在管芯焊盘的未搭载半导体芯片的部分处搭载了部件的状态的主要部分放大俯视图。另外,图40是示出作为针对图5的比较例的半导体装置的内部构造的透视俯视图。
如上述那样,在一个种类的平面尺寸的管芯焊盘DP上搭载平面尺寸不同的多个种类的半导体芯片的情况下,如图5所示,在管芯焊盘DP的上表面DPt未搭载半导体芯片SC的区域有时更广地残留。换言之,在俯视时,该管芯焊盘DP的上表面DPt的未搭载半导体芯片SC的区域的面积有时大于半导体芯片的面积。在图5中,管芯焊盘DP包括未搭载半导体芯片SC的部分DP1以及在俯视时设置于部分DP1与引线LDs之间并且搭载了半导体芯片SC的部分DP2。另外,Y方向上的半导体芯片SC的长度Lc1比Y方向上的部分DP1的长度L1更短(小)。换言之,另外,在Y方向上,管芯焊盘DP的部分DP1的长度L1比部分DP2的长度L2更长(大)。在图5所示的例子中,管芯焊盘DP的上表面DPt中的、未搭载半导体芯片SC的区域的面积是一半以下。另外,根据使半导体芯片SC的源电极焊盘SE和源极用的引线LDs的连接距离接近来降低阻抗分量的观点,半导体芯片SC的搭载位置优选为比管芯焊盘DP的中央部更接近引线LDs侧的位置。因此,位于比管芯焊盘DP的部分DP2更远离引线LDs的一侧的部分DP1的面积进一步变大。
根据半导体装置PK1的通用性的观点,优选使端子排列共同化,所以如图5那样,即使未搭载半导体芯片SC的区域较广地残留,也没有问题。另外,根据半导体装置PK1的散热性的观点,通过增大管芯焊盘DP的平面面积,能够增大散热路径的剖面积,所以即使在半导体芯片SC的平面尺寸变小的情况下,管芯焊盘DP的平面尺寸也优选大。
但是,根据本申请发明者的研究,判明了如果通过使半导体芯片SC的平面尺寸小型化而管芯焊盘DP的未搭载半导体芯片SC的区域的面积变大,则半导体芯片SC和管芯焊盘DP的粘结面容易损伤。详细而言,判明了在如图40所示的比较例的半导体装置PKh1那样,在管芯焊盘DP的部分DP1上未配置图5所示的部件PS1的情况下,在将半导体芯片SC和管芯焊盘DP粘结固定的管芯结合材料BP1中产生裂纹,该裂纹在管芯结合材料BP1内发展(管芯结合材料BP1发生衬底破坏),半导体芯片SC和管芯焊盘DP剥离。该现象有时由于在将半导体装置PKh1安装到未图示的安装基板时进行的回流处理时的热影响而产生。另外,还有时即使在回流处理之后未产生裂纹,由于之后的温度循环负荷而产生裂纹。另外,如果详细调查裂纹在该管芯结合材料BP1内发展而剥离的半导体装置PKh1,则判明了在未搭载半导体芯片SC的部分DP1,密封体MR和管芯焊盘DP的粘结界面也在大致在整个面剥离。
根据上述意见,考虑为按照以下的机理产生在管芯结合材料BP1中产生裂纹的现象。即,如果对半导体装置PKh1施加温度循环负荷,则由于密封体MR和管芯焊盘DP的线膨胀系数的差异,在密封体MR和管芯焊盘DP的粘结界面产生应力。该应力的大小与线膨胀系数的差的大小以及粘结界面的面积成比例地变大,所以管芯焊盘DP的部分DP1的面积越大,产生越大的应力。另外,在半导体芯片SC和管芯焊盘DP的粘结界面,产生由半导体芯片SC和管芯焊盘DP的线膨胀系数的差异所引起的其他应力。因此,在管芯焊盘DP和密封体MR的粘结界面产生了的应力容易集中到管芯焊盘DP的部分DP1和部分DP2的边界。因此,考虑为在半导体芯片SC的平面尺寸小的情况下,即在管芯焊盘DP1的面积大的情况下,在管芯焊盘DP的部分DP1和部分DP2的边界产生大的应力,由于该应力在管芯结合材料BP1中产生裂纹,而导致剥离。
关于由于管芯焊盘DP和密封体MR的线膨胀系数的差异而产生的应力,如图6所示,在管芯焊盘DP的下表面DPb从密封体MR露出的、管芯焊盘露出型的半导体装置中,变得特别大。在管芯焊盘DP的下表面DPb的整体被密封体MR密封了的情况下,通过以包围管芯焊盘DP的方式形成了密封体MR,容易抑制管芯焊盘DP的热膨胀、热收缩。但是,在管芯焊盘DP的下表面DPb从密封体MR露出了的情况下,管芯焊盘DP容易由于热影响而膨胀或者收缩,所以应力容易变大。
另外,如果半导体芯片SC的厚度薄至100μm以下左右,则需要减小由导电性材料构成的管芯结合材料BP1的供给量。其原因是,防止由导电性材料构成的管芯结合材料BP1蔓延到半导体芯片SC的表面SCt侧,而背面SCb(参照图6)侧的漏电极DE(参照图6)和表面SCt侧的源电极焊盘SE短路。在该情况下,在半导体芯片SC的边缘部,难以形成管芯结合材料BP1的嵌条形状,所以相比于半导体芯片SC的厚度比100μm更厚的情况,管芯结合材料BP1更容易损伤。
因此,本申请发明者研究降低在管芯焊盘DP的部分DP1和部分DP2的边界产生的应力的技术,发现了以下的结构。即,如图8所示,在管芯焊盘DP的部分DP1的上表面DPt,在半导体芯片SC的侧面SCs1与管芯焊盘DP的边缘部(位于与引线LDs相反的一侧的侧面DPs2)之间,固定了部件PS1。部件PS1只要能够在管芯焊盘DP的上表面DPt上(在图8所示的例子中是在金属膜CM1上)紧贴地固定,则能够使用各种材料。在图5、图8所示的例子中,例如部件PS1由使与管芯结合材料BP1相同的材料、即在树脂中含有多个银粒子的被称为银膏的导电性的树脂粘结材料硬化而得到的部件构成。通过用相同的材料构成管芯结合材料BP1和部件PS1,在半导体装置PK1(参照图5)的制造工序中,能够降低为了形成部件PS1而追加的工序。
由该银膏构成的部件PS1被粘结固定到管芯焊盘DP的上表面DPt上。这样,在半导体芯片SC的侧面SCs2与管芯焊盘DP的边缘部(位于与引线LDs相反的一侧的侧面DPs2)之间粘结固定了部件PS1的情况下,在对半导体装置PK1施加了温度负荷时,应力的施加方法与图40所示的半导体装置PK1不同。即,由于管芯焊盘DP和密封体MR(参照图6)的线膨胀系数的差异而产生了的应力的一部分被分散到部件PS1。其结果,能够降低在管芯焊盘DP的部分DP1和部分DP2的边界产生的应力。另外,通过降低在管芯焊盘DP的部分DP1和部分DP2的边界产生的应力,能够抑制半导体芯片SC和管芯焊盘DP的粘结面的损伤。
但是,部件PS1是用于抑制半导体芯片SC和管芯焊盘DP的粘结面的损伤的部件,所以无需与在半导体装置PK1中形成了的电路电连接。如果如半导体芯片SC那样经由图5所示的金属条带MB1、导线MW1等导电性部件与引线LD电连接,则制造工序变得繁杂。在本实施方式中,根据如上述那样使制造工序高效化的观点,使用与管芯结合材料BP1相同的银膏来形成了部件PS1,所以部件PS1的搭载面PSb(参照图6)还能够考虑为与管芯焊盘DP电连接。但是,根据无需使部件PS1电气地发挥功能而使噪声降低的观点,优选降低部件PS1的电气功能。因此,部件PS1的搭载面PSb以外的部分未与其他引线LD、半导体芯片SC电连接。换言之,本实施方式的部件PS1和与管芯焊盘DP以及管芯焊盘DP一体地形成了的引线LDd以外的引线LD被电分离(绝缘)。因此,即使在将部件PS1搭载到管芯焊盘DP的部分DP1,也能够抑制制造效率的降低。另外,部件PS1作为电气电路成为开路端,所以在使用图1说明的晶体管Q1中流过电流时在部件PS1中难以流过电流。因此,即使在用导电性部件形成了部件PS1的情况下,也能够降低对晶体管Q1的电气特性波及的影响。
另外,如图8所示,与Y方向正交的X方向上的半导体芯片SC的边缘部(侧面SCs3)至管芯焊盘DP的边缘部(侧面DPs3)的俯视时的长度(距离)L3比Y方向上的部分DP1的长度L1更短(小)。另外,与Y方向正交的X方向上的半导体芯片SC的边缘部(侧面SCs4)至管芯焊盘DP的边缘部(侧面DPs4)的俯视时的距离(省略基于符号的图示)比Y方向上的部分DP1的长度L1更短(小)。即,Y方向上的未搭载半导体芯片SC的区域的长度L1比X方向上的未搭载半导体芯片SC的区域的长度L3更长(大)。在该情况下,在半导体芯片SC的侧面SCs3以及侧面SCs4产生的应力比在侧面SCs2产生的应力更小,所以也可以不考虑。同样地,半导体芯片SC的侧面SCs1和管芯焊盘DP的侧面DPs1的俯视时的距离比长度L1更小,所以在半导体芯片SC的侧面SCs1产生的应力也可以不考虑。
即,通过在产生最大的应力的半导体芯片SC的侧面SCs2与管芯焊盘DP的侧面DPs2之间配置部件PS1,能够抑制半导体芯片SC和管芯焊盘DP的粘结面的损伤。
另外,根据增大使在管芯焊盘DP的部分DP1和部分DP2的边界产生的应力降低的程度的观点,优选减小图8所示的Y方向上的半导体芯片SC和部件PS1的间隔距离P1。在图8所示的例子中,间隔距离P1比Y方向上的半导体芯片的长度Lc1更小。另外,在图5中,示出了在半导体芯片SC的侧面SCs2与管芯焊盘DP的边缘部(位于与引线LDs相反的一侧的侧面DPs2)之间,粘结固定了多个部件PS1的例子,但多个部件PS1中的、最接近半导体芯片SC1地配置的部件PS1和半导体芯片SC的间隔距离P1比Y方向上的半导体芯片的长度Lc1更小。在管芯焊盘DP的部分DP1和部分DP2的边界产生的应力与Y方向上的部件PS1和半导体芯片SC的间隔距离P1成比例地变大,所以间隔距离P1优选小于Y方向上的半导体芯片SC的长度Lc1。
另外,根据提高通过部件PS1使应力分散的效果的观点,部件PS1的厚度优选比半导体芯片SC的厚度更大。如图6所示,部件PS1的厚度比半导体芯片SC的厚度更大。通过增大部件PS1的厚度,能够抑制密封体MR的热膨胀、热收缩的影响波及到管芯结合材料BP1。另外,在图6中,示出了在管芯焊盘DP的部分DP1上粘结固定多个部件PS1的例子,但多个部件PS1各自的厚度大于半导体芯片SC的厚度。例如,在图6所示的例子中,部件PS1的厚度是150μm左右。
另外,根据使在管芯焊盘DP的部分DP1和部分DP2的边界产生的应力可靠地分散的观点,如图8所示,优选X方向上的部件PS1的长度Lps1比X方向上的半导体芯片SC的长度Lc12更长。如果在X方向上,使部件PS1比半导体芯片SC更长地延伸,则能够抑制应力从部件PS1的周围蔓延而施加到管芯焊盘DP的部分DP1和部分DP2的边界。在本实施方式中,在管芯焊盘DP的上表面DPt上形成了金属膜CM1,部件PS1以覆盖金属膜CM1的沿着侧面DPs3的边至相反侧的边的范围的方式沿着X方向延伸。在该情况下,在俯视时,能够在半导体芯片SC的侧面SCs2与管芯焊盘DP的侧面DPs2之间,可靠地介有部件PS1,所以能够大幅降低在管芯焊盘DP的部分DP1和部分DP2的边界产生的应力。
但是,考虑在部件PS1和管芯焊盘DP的侧面DPs2的Y方向上的间隔距离长的情况下,在部件PS1处产生应力集中而部件PS1损伤或者剥离的情况。如果部件PS1从管芯焊盘DP剥离,则得不到基于部件PS1的应力分散效果,所以成为容易在管芯焊盘DP的部分DP1和部分DP2的边界产生应力集中的状态。因此,根据防止或者抑制在最接近半导体芯片SC的位置形成了的部件PS1的剥离的观点,优选如图5所示的半导体装置PK1那样,在管芯焊盘DP的部分DP1,搭载多个部件PS1。另外,虽然图示省略,作为针对图5的变形例,还考虑通过增大例如图5所示的Y方向的长度(宽度)(成为使例如图5所示的二个部件PS1一体化的程度的宽度),抑制部件PS1的损伤的方法。但是,根据降低在半导体装置PK1内搭载的材料的使用量的观点,优选如图5所示,搭载沿着与Y方向正交的X方向延伸的多个部件PS1。
另外,根据在多个部件PS1之间使应力可靠地分散的观点,如图5所示,Y方向上的多个部件PS1间的间隔距离P2优选比Y方向上的半导体芯片SC的长度Lc1更小。由此,能够降低对多个部件PS1的各个部件施加的应力,所以能够抑制部件PS1的剥离。
另外,作为与本实施方式不同的方式,考虑不设置图5、图6以及图8所示的部件PS1而替代地在管芯焊盘DP中形成未图示的槽、多个凹陷部(凹座)的方法或者实施粗糙化处理的方法。但是,如果考虑搭载如上述那样平面尺寸不同的多个种类的半导体芯片SC,则搭载半导体芯片SC的区域的范围不同,所以难以使形成槽、凹陷部的位置、实施粗糙化处理的位置单独地最佳化。另一方面,在本实施方式中,通过对共同的管芯焊盘DP追加部件PS1,抑制管芯结合材料BP1的损伤,所以能够根据半导体芯片SC的平面尺寸,使部件PS1的搭载位置容易地最佳化。
<半导体装置的制造方法>
接下来,说明使用图1~图7说明了的半导体装置PK1的制造工序。按照图9所示的流程,制造半导体装置PK1。图9是示出使用图1~图7说明了的半导体装置的制造工序的概要的说明图。
<引线框架准备工序>
首先,在图9所示的引线框架准备工序中,准备图10~图12所示的引线框架LF。图10是示出在图9所示的引线框架准备工序中准备的布线基板的整体构造的俯视图。另外,图11是相当于图10所示的器件形成部一个的量的放大俯视图。另外,图12是沿着图11的A-A线的放大剖面图。
如图10所示,在本工序中准备的引线框架LF在外框LFb的内侧具备多个(在图10中32个)器件形成部LFa。多个器件形成部LFa分别相当于图5所示的半导体装置PK1的一个量。引线框架LF是矩阵状地配置了多个器件形成部LFa的所谓多型腔基体材料。这样,通过使用具备多个器件形成部LFa的引线框架LF,能够一并地制造多个半导体装置PK1(参照图3),所以能够提高制造效率。引线框架LF由以例如铜(Cu)为主体的金属材料构成,其厚度是例如125μm~200μm左右。
另外,如图11所示,各器件形成部LFa的周围被框部LFc包围。框部LFc是在图9所示的直至单片化工序的期间支撑在器件形成部LFa内形成了的各部件的支撑部。
另外,如图11以及图12所示,在各器件形成部LFa中,已经形成了使用图5~图7说明了的管芯焊盘DP以及多个引线LD。管芯焊盘DP经由悬置引线TL与在器件形成部LFa的周围配置了的框部LFc连结,被框部LFc支撑。另外,多个引线LD分别与框部LFc连结,被框部LFc支撑。
在图11所示的例子中,从在俯视时形成四边形的器件形成部LFa的一边侧朝向对置边,沿着Y方向,按照源极用的引线LDs、管芯焊盘DP、与管芯焊盘DP一体地形成了的漏极用的引线LDd的顺序排列。另外,沿着X方向,在引线LDs的旁边,排列了栅极用的引线LDg。
另外,在管芯焊盘DP的上表面DPt,预先形成了由镍(Ni)或者银(Ag)构成的金属膜CM1。如上述那样,为了能够搭载平面尺寸不同的多个种类的半导体芯片SC(参照图5),金属膜CM1以覆盖管芯焊盘DP的上表面DPt的大部分的方式形成。换言之,在本实施方式中,以跨过未搭载半导体芯片的部分DP1和作为半导体芯片的搭载预定区域的部分DP2的方式,形成了金属膜CM1。
另外,在多个引线LD中的、栅极用的引线LDg的连接部Rb2的上表面RBt,预先形成了由例如银构成的金属膜CM2。另一方面,在多个引线LD中的、源极用的引线LDs的连接部RB1的上表面RBt上,不形成金属膜CM2,而作为基体材料的铜合金露出。金属膜CM1、CM2分别能够通过例如镀层法形成。另外,在用相同的材料形成金属膜CM1、CM2的情况下,能够一并地形成。
另外,对多个引线LD中的引线LDs,预先实施弯曲加工,形成了以使连接部RB1的位置比端子部TN1的位置更高的方式设置了的偏置部(弯曲加工部、倾斜部、高低差部)SL1。另外,对多个引线中的、在引线LDs的旁边配置了的引线LDg,也预先实施弯曲加工,形成了以使连接部RB2的位置比端子部TN1的位置更高的方式设置了的偏置部(弯曲加工部、倾斜部、高低差部)SL1。偏置部SL1能够通过例如加压加工形成。
在本工序中准备的引线框架LF的上述以外的特征如使用图5~图8说明,所以重复的说明省略。
<第1部件配置>
另外,在图9所示的第1部件配置工序中,如图13、图14以及图15所示,在管芯焊盘DP的部分DP1配置部件PS1。图13是示出在图11所示的管芯焊盘的一部分处涂覆了银膏的状态的放大俯视图。另外,图14是沿着图13的A-A线的放大剖面图。另外,图15是示意地示出在沿着图13的B-B线的放大剖面,涂覆银膏的方式的说明图。另外,图16是示出针对图15的变形例的说明图。另外,图17是示出通过图16所示的方式形成了的银膏的平面形状的放大俯视图。
在本工序中,如图13~图15所示,只要能够在管芯焊盘DP1上(在图13~图15中在金属膜CM1上)紧贴固定,则能够针对部件PS1的材料应用各种变形例。在本实施方式的例子中,作为部件PS1,使用与用于搭载半导体芯片的管芯结合材料BP1相同的材料、例如含有多个银(Ag)粒子的、被称为银(Ag)膏的导电性的树脂粘结材料。银膏在使树脂成分硬化之前具有流动性,所以如果如图15所示,从喷嘴NZ1朝向管芯焊盘DP的上表面DPt涂覆膏状态的部件PS1,则部件PS1和管芯焊盘DP的部分DP1(详细而言在管芯焊盘DP上形成了的金属膜CM1)紧贴。另外,在图15所示的例子中,在排出由银膏构成的部件PS1的同时使喷嘴NZ1沿着X方向移动。由此,如图13以及图15所示,能够形成沿着X方向延伸的部件PS1。以下,将如图15所示在排出膏材的同时使喷嘴NZ1移动来涂覆的方式记载为拉线方式。
作为针对图15的变形例,如图16所示,能够准备具有多个排出口的喷嘴NZ2,按照从多个排出口一并地排出膏状的部件PS1的方式,形成部件PS1。以下,将如图16所示,从多个排出口排出膏材来涂覆的方式记载为多点涂覆方式。
在按照图15所示的拉线方式涂覆部件PS1的情况下,能够防止部件PS1沿着部件PS1的X方向被分断。部件PS1是为了降低在图13所示的管芯焊盘DP的部分DP1和部分DP2的边界产生的应力,为了使应力分散而设置的部件。在沿着X方向延伸的部件PS1的一部分在中途被分断了的情况下,应力经由部件PS1的分断部位被传递,在管芯焊盘DP的部分DP1和部分DP2的边界产生的应力变大。因此,根据抑制被传递到管芯焊盘DP的部分DP1和部分DP2的边界的观点,优选防止部件PS1沿着X方向分断。即,根据降低在管芯焊盘DP的部分DP1和部分DP2的边界产生的应力的观点,优选图15所示的拉线方式。
另一方面,在图16所示的多点涂覆方式的情况下,不需要使喷嘴NZ2移动的时间,所以能够缩短涂覆时间。因此,根据高效地制造的观点,优选图16所示的多点涂覆方式。但是,在多点涂覆方式的情况下,在管芯焊盘DP上的多个部位一并地涂覆部件PS1。因此,优选以使相邻的部件PS1可靠地接触的方式,比上述拉线方式的情况,增加涂覆量。换言之,根据降低部件PS1的形成所需的银膏的使用量的观点,优选图15所示的拉线方式。
另外,在通过图15所示的拉线方式形成了部件PS1的情况下,如图13所示,与涂覆方向(X方向)正交的Y方向上的部件PS1的扩展变得均匀。另一方面,在通过图16所示的多点涂覆方式形成了部件PS1的情况下,如图17所示,与涂覆方向(X方向)正交的Y方向上的部件PS1的扩展成为交替反复了大的部分和小的部分的形状。
但是,如上述那样,在本实施方式中,用与管芯结合材料BP1相同的材料形成部件PS1。因此,在本工序中,作为图9所示的半导体芯片搭载工序的准备,如图13、图17所示,能够将管芯结合材料BP1预先涂覆到作为管芯焊盘DP的芯片搭载区域的部分DP2。
在管芯结合材料BP1的涂覆方法中,能够应用使用图15说明了的拉线方式或者使用图16说明了的多点涂覆方式。但是,在半导体芯片的厚度薄的情况下,根据防止管芯结合材料BP1蔓延到半导体芯片的表面侧而短路的观点,优选能够降低管芯结合材料BP1的涂覆量的拉线方式。另外,在通过拉线方式分别形成管芯结合材料BP1以及部件PS1的情况下,能够从图15所示的喷嘴NZ1分别供给部件PS1以及管芯结合材料BP1。即,能够使部件PS1的供给装置和管芯结合材料BP1的供给装置兼用化,所以能够简化制造装置。
另外,部件PS1和管芯结合材料BP1的供给顺序未特别限定,但根据抑制管芯结合材料BP1的干燥的观点,优选首先形成部件PS1。有时,在按照拉线方式形成部件PS1的情况下,相比于多点涂覆方式,涂覆时间更长。因此,在图9所示的半导体芯片搭载工序中,根据抑制管芯结合材料BP1干燥而难以扩展的观点,优选在紧接着半导体芯片搭载工序之前涂覆管芯结合材料BP1。
另外,在本实施方式中,说明了根据高效地进行制造工序的观点,在半导体芯片搭载工序之前进行第1部件配置工序的实施方式,但作为变形例,还能够在半导体芯片搭载工序之后,进行第1部件配置工序。
<半导体芯片搭载工序>
接下来,在图9所示的半导体芯片搭载工序中,如图18以及图19所示,在引线框架LF的管芯焊盘DP上搭载半导体芯片SC。图18是示出在图13所示的管芯焊盘上搭载了半导体芯片的状态的放大俯视图。另外,图19是沿着图18的A-A线的放大剖面图。
在本工序中,在与作为漏极端子的引线LDd一体地形成了的管芯焊盘DP的部分DP2上经由管芯结合材料BP1搭载半导体芯片SC。在图18所示的例子中,以使半导体芯片SC的四个侧面的侧面SCs1沿着管芯焊盘DP的侧面DPs1的方式,在管芯焊盘DP上配置半导体芯片SC。换言之,以使侧面SCs1与源极用的引线LDs的前端(连接部RB1侧的端部)对置的方式,在管芯焊盘DP上配置半导体芯片SC。另外,如图19所示,以使形成了漏电极DE的背面SCb与作为管芯焊盘DP的芯片搭载面的上表面DPt对置的方式,经由管芯结合材料BP1粘结固定半导体芯片SC。由此,半导体芯片SC的源电极焊盘SE以及栅电极焊盘GE如图18所示露出。另一方面,如图19所示,半导体芯片SC的漏电极DE经由作为导电性粘结材料的管芯结合材料BP1以及金属膜CM1与管芯焊盘DP电连接。
另外,在本工序中,以使半导体芯片SC和作为源极端子的引线LDs的连接部RB1的距离接近的方式,在管芯焊盘DP的上表面DPt上靠近引线LDs地配置半导体芯片SC。因此,相比于将半导体芯片SC搭载于管芯焊盘DP的中央部的情况,半导体芯片SC的侧面SCs2至管芯焊盘DP的部分DP1侧的侧面DPs2的距离变大。
另外,管芯结合材料BP1是在包含例如环氧树脂等热硬化性树脂的树脂材料中混合了多个导电性粒子(例如银粒子)的树脂粘结材料,硬化之前的性状呈膏状。因此,如上述那样,在预先在管芯焊盘DP的部分DP2处涂覆了膏状的管芯结合材料BP1之后,将半导体芯片SC朝向管芯焊盘DP的上表面DPt按压。由此,能够在半导体芯片SC与管芯焊盘DP的上表面DPt之间扩展管芯结合材料BP1。
接下来,在本工序中,在将半导体芯片SC分别搭载于管芯焊盘DP上之后,使管芯结合材料BP1以及部件PS1一并地硬化(固化工序)。在管芯结合材料BP1以及部件PS1中,如上述那样分别包含热硬化性树脂,所以通过实施加热处理(烘烤处理),使热硬化性树脂成分硬化。通过本工序,半导体芯片SC被粘结固定到管芯焊盘DP的部分DP2。另外,部件PS1被粘结固定到管芯焊盘DP的部分DP1。
如本实施方式那样,通过用相同的材料构成管芯结合材料BP1和部件PS1,在半导体芯片搭载工序之前配置部件PS1,能够使管芯结合材料BP1和部件PS1一并地硬化。
<条带结合工序>
另外,在图9所示的条带结合工序中,如图20以及图21所示,经由金属条带MB1,电连接半导体芯片SC的源电极焊盘SE和作为源极端子的引线LDs的连接部RB1的上表面RBt。图20是示出经由金属条带电连接了图18所示的半导体芯片和引线的状态的放大俯视图。另外,图21以及图22是阶段状地示出在沿着图20的A-A线的剖面,连接金属条带的状态的放大剖面图。
在本工序中,使用如图21以及图22所示具有将金属带20接合到被接合部件的结合工具23、切断接合之后的金属带20的切断刃24以及在与结合工具23之间的间隙中夹住金属带20而控制金属带20的抽出方向的条带导引28的条带连接装置来进行条带结合。首先,如图21所示,对半导体芯片SC的源电极焊盘SE接合金属带20的一端(图20所示的金属条带MB1的一端)。在本工序中,通过将从结合工具23与条带导引28之间的间隙抽出了的金属带20按压到源电极焊盘SE,仿照结合工具23,金属带20的形状变形。另外,通过对结合工具23施加超声波,能够在金属带20和源电极焊盘SE的接触界面形成金属结合,电连接金属带20和源电极焊盘SE。此时,在金属带20的被按压面,形成压痕20a。
另外,管芯焊盘DP的位于芯片搭载面的相反侧的下表面DPb与支撑台25的片保持面25a紧贴,被保持于支撑台25。通过在这样作为被接合部的源电极焊盘SE被支撑台25支撑了的状态下进行结合,对结合工具23施加了的超声波被高效地传递给金属带20的接合面。其结果,能够提高金属带20和源电极焊盘SE的接合强度。关于支撑台25,为了使对结合工具23施加了的超声波集中地传递给接合界面,优选使用例如金属造的载置台(金属载置台)。
接下来,在通过结合工具23和条带导引28控制了金属带20的抽出方向的状态下,在从保持金属带20的卷盘21依次抽出金属带20的同时使结合工具23移动,如图22所示,对引线LDs的连接部RB1的上表面RBt接合金属带20的另一端。此时,通过将金属带20按压到作为引线LDs的条带连接面的上表面RBt,仿照结合工具23,以使金属带20与引线LDs的连接部RB1的上表面RBt紧贴的方式变形。另外,通过对结合工具23施加超声波,能够在金属带20和连接部RB1的上表面RBt的接触界面形成金属结合,电连接金属带20和连接部RB1的上表面RBt。
另外,连接部RB1的位于上表面RBt的相反侧(正下方)的下表面RBb与支撑台25的条带连接部保持面25b紧贴,而被保持于支撑台25。在图22所示的例子中,在引线LDs处设置了偏置部SL1,所以在支撑台25的一部分处设置突出部,突出部的上表面成为条带连接部保持面25b。通过在这样作为被接合部的连接部RB1的下表面RBb被支撑台25的条带连接部保持面25b支撑了的状态下进行结合,对结合工具23施加了的超声波被高效地传递给金属带20的接合面。其结果,能够提高金属带20和连接部RB1的接合强度。
接下来,虽然图示省略,使结合工具23以及条带导引28沿着Y方向向远离半导体芯片SC的方向进一步移动。然后,通过将图22所示的切断刃24朝向金属带20按压,切断金属带20。由此,从金属带20分离地形成电连接半导体芯片SC的源电极焊盘SE和源极用的引线LDs的连接部RB1的金属条带MB1(参照图20)。此时,利用切断刃24的切断位置优选设为连接部RB1的上表面RBt上。在切断刃24和上表面Rbt之间夹入了金属带20的状态下切断时,能够稳定地切断金属带20。
通过以上的工序,如图20所示,半导体芯片SC的源电极焊盘SE和引线LDs的连接部RB1的上表面RBt经由金属条带MB1电连接。
<导线结合工序>
另外,在图9所示的导线结合工序中,如图23以及图24所示,将半导体芯片SC的栅电极焊盘GE和栅极用的引线LDg的连接部RB2的上表面RBt经由导线(金属导线)MW1电连接。
图23是示出经由金属导线电连接了图20所示的半导体芯片和栅极用的引线的状态的放大俯视图。另外,图24是示出在沿着图23的A-A线的剖面连接了导线的状态的放大剖面图。
如图24所示,在本工序中,通过对结合工具26施加超声波,通过使导线MW1的一部分与被接合部金属结合而接合。例如,在图24所示的例子中,首先,对在栅电极焊盘GE的最表面形成了的金属膜(例如铝膜或者金膜)接合由例如金(Au)构成的导线MW1的一端。此时,对结合工具26施加超声波而在接合界面形成金属结合。
接下来,在从结合工具26抽出导线27的同时使结合工具26在引线LDg的连接部RB2上移动。在引线LDg的连接部RB2的上表面RBt,形成了能够提高导线MW1和引线LDg的基体材料(例如铜)的连接强度的金属膜CM2。引线LDg的基体材料由例如铜(Cu)合金构成,金属膜CM2由例如银(Ag)构成。然后,通过对结合工具26施加超声波,在导线27的一部分(第2结合部)和金属膜CM2的接合界面形成金属结合,将它们电连接。接下来,如果切断导线27,则形成图23以及图24所示的导线MW1。
在本工序中,根据对被接合部高效地传递超声波而提高接合强度的观点,优选在通过支撑台25支撑了被接合部的状态下对结合工具26施加超声波。
另外,如图9所示,优选在条带结合工序之后进行导线结合工序。在条带结合工序中,在如上述那样连接半导体芯片SC和源电极焊盘SE时,施加超声波而连接。此时,在预先连接了导线MW1和栅电极焊盘GE的情况下,由于条带结合时的超声波的影响,存在导线MW1或者导线MW1的连接部分损伤的可能性。因此,优选在条带结合工序之后,进行连接宽度比金属条带MB1窄的导线MW1的导线结合工序。
<密封工序>
接下来,在图9所示的密封工序中,用绝缘树脂对图23所示的、半导体芯片SC、管芯焊盘DP的一部分、多个引线LD的一部分、金属条带MB1以及导线MW1进行密封,形成图25所示的密封体MR。图25是示出形成了对图23所示的半导体芯片以及金属条带进行密封的密封体的状态的放大俯视图。另外,图26是示出在沿着图25的A-A线的剖面在成型模具内配置了引线框架的状态的放大剖面图。
在本工序中,例如,使用如图26所示具备上模(第1模具)32和下模(第2模具)33的成型模具31,通过所谓传递模方式,形成密封体MR。
在图26所示的例子中,以使器件形成部LFa的管芯焊盘DP以及在管芯焊盘DP的旁边配置了的多个引线LD位于形成于上模32的空腔34内的方式,配置引线框架LF,通过上模32和下模33夹紧(夹入)。如果在该状态下,将软化(可塑化)了的热硬化性树脂(绝缘树脂)压入到成型模具31的空腔34,则绝缘树脂被供给到由空腔34和下模33形成了的空间内,仿照空腔34的形状而成型。
此时,如果使管芯焊盘DP的下表面DPb以及引线LD的端子部TN1的下表面LDb与下模33紧贴,则下表面DPb、LDb在密封体MR的下表面MRb从密封体MR露出。另一方面,引线LDs的连接部RB1的下表面RBb与下模33不紧贴。因此,连接部RB1被绝缘树脂覆盖,被密封体MR密封。另外,在管芯焊盘DP的边缘部预先形成了高低差部,管芯焊盘DP的边缘部的下表面被树脂密封。这样,由于管芯焊盘DP以及引线LD各自的一部分被密封体MR密封,不易从密封体MR脱落。
另外,密封体MR是以绝缘性的树脂为主体而构成的,但通过例如将二氧化硅(SiO2)粒子等填料粒子混合到热硬化性树脂,能够提高密封体MR的功能(例如针对翘曲变形的耐性)。
<镀层工序>
接下来,在图9所示的镀层工序中,如图27所示,将引线框架LF浸渍到未图示的镀液,在从密封体MR露出了的金属部分的表面形成金属膜SD。图27是示出在图26所示的管芯焊盘以及引线的从密封体的露出面形成了金属膜的状态的放大剖面图。
在图27所示的例子中,例如,在焊料溶液中浸渍引线框架LF,通过电镀方式,形成作为焊料膜的金属膜SD。金属膜SD具有在将完成了的半导体装置PK1(参照图6)安装到未图示的安装基板时,提高由例如焊料构成的连接材料的湿润性的功能。作为金属膜SD的种类,例如,可以举出锡-铅镀层、作为无Pb镀层的纯锡镀层、锡-铋镀层等。
另外,也可以使用预先在引线框架上形成了导体膜的料嘴加工镀层的引线框架。此时的导体膜由例如镍膜、在镍膜上形成了的钯膜以及在钯膜上形成了的金膜形成的情况较多。在使用料嘴加工镀层的引线框架的情况下,本镀层工序被省略。在使用料嘴加工镀层的引线框架的情况下,即使使作为基体材料的铜(Cu)、铜合金不露出,与金属条带MB1的金属接合性也良好。因此,在料嘴加工镀层的情况下,在包括金属条带MB1的接合区域的引线框架整体上形成料嘴加工镀层膜。
<单片化工序>
接下来,在图9所示的单片化工序中,如图28所示,针对每个器件形成部LFa,分割引线框架LF。图28是示出使图27所示的引线框架单片化了的状态的放大俯视图。
在本工序中,如图28所示,切断引线LD的一部分,将引线LD从框部LFc切离。另外,在本工序中,切断支撑管芯焊盘DP的多个悬置引线TL的一部分,将管芯焊盘DP从框部LFc切离。切断方法没有特别限定,能够通过加压加工或者使用旋转刃的切削加工来切断。
通过以上的各工序,得到使用图1~图7说明了的半导体装置PK1。之后,进行外观检查、电气试验等必要的检查、试验,出货或者安装到未图示的安装基板。
<变形例>
接下来,说明针对在上述实施方式中说明了的实施方式的各种变形例。
首先,在上述实施方式中,说明了作为部件PS1使用作为与管芯结合材料BP1相同的材料的银膏的实施方式。但是,根据抑制半导体芯片SC和管芯焊盘DP的粘结界面的损伤的观点,作为部件PS1,能够使用以下那样的材料。
例如,在图29所示的半导体装置PK2中,代替图6所示的部件PS1,而使用了作为在管芯焊盘DP的部分DP1搭载的部件PS2未混合银粒子等金属粒子的非导电性的树脂粘结材料。图29是示出针对图6的变形例的剖面图。
在管芯焊盘DP的部分DP1粘结固定非导电性的部件(第1部件)PS2的情况下,部件PS2和管芯焊盘DP被电分离。另外,部件PS2与在上述实施方式中说明了的部件PS1同样地,未与管芯焊盘DP以外的端子(引线LD)电连接。即,部件PS2与半导体装置PK2具有的其他部件电分离。因此,能够降低针对半导体装置PK2具有的电路的噪声分量。
另外,在半导体装置PK2的制造工序中,在上述第1部件配置工序中,无法使供给膏状的部件PS2的喷嘴和供给膏状的管芯结合材料BP1的喷嘴兼用化,需要分别从不同的喷嘴供给这一点不同。但是,关于在半导体芯片搭载工序中说明了的固化工序,能够兼用化。即,在管芯结合材料BP1以及部件PS2,分别包含热硬化性树脂,所以通过实施加热处理(烘烤处理),能够使管芯结合材料BP1以及部件PS2一并地硬化。
图29所示的半导体装置PK2除了上述不同点以外,与在上述实施方式中说明了的半导体装置PK1相同。例如,在上述第1部件配置工序中,能够应用拉线方式或者多点涂覆方式中的某一种来配置膏状的部件PS2。因此,省略能够将在上述实施方式中说明了的部件PS1置换为部件PS2而应用的说明以及图示。
另外,例如,关于图30以及图31所示的半导体装置PK3,代替图5以及图6所示的部件PS1,而在管芯焊盘DP的部分DP1,经由作为非导电性的树脂粘结材料的部件PS2,固定了由与部件PS2不同的材料构成了的部件PS3(在图30中附加点图案而表示的部件)。图30是示出针对图5的变形例的透视俯视图。另外,图31是沿着图30的A-A线的剖面图。
在如半导体装置PK3那样,经由作为粘结材料的部件PS2粘结固定其他部件PS3的情况下,能够使将部件PS2和部件PS3当作一体物的情况下的厚度容易地变厚。例如,在图31所示的例子中,部件PS3的上表面PS3t至管芯焊盘DP的上表面DPt的距离比半导体芯片SC的表面SCt至管芯焊盘DP的距离更远。通过使将部件PS2和部件PS3当作一体物的情况下的厚度变厚,抑制密封体MR的热膨胀量(或者热收缩量)的锚定效应变大。因此,能够降低由于密封体MR和管芯焊盘DP的线膨胀系数的差异而产生的管芯结合材料BP1的损伤。
另外,如上所述,部件PS2是非导电性的树脂粘结材料,所以即使在作为部件PS3选择了金属材料的情况下,也能够与管芯焊盘DP电分离。因此,能够降低针对半导体装置PK3具有的电路的噪声分量。
另外,根据抑制部件PS3和密封体MR的紧贴界面的剥离的观点,部件PS3优选由线膨胀系数与密封体MR接近的材料、例如硅(Si)等构成。
另外,在半导体装置PK3的制造工序中,在第1部件配置工序之后,追加将部件PS3搭载到部件PS2上的工序以及通过使部件PS2硬化而将部件PS3粘结固定到管芯焊盘DP上的工序。但是,在使管芯结合材料BP1硬化时,能够一并地进行使部件PS2硬化的工序(固化工序)。
图30以及图31所示的半导体装置PK3除了上述不同点以外,与在上述实施方式中说明了的半导体装置PK1相同。因此,省略与上述实施方式重复的说明以及图示。
另外,例如,关于图32以及图33所示的半导体装置PK4以及图34所示的半导体装置PK5,代替图5以及图6所示的部件PS1,而在管芯焊盘DP的部分DP1,以使多个凸块STB1(在图34中凸块STB2)沿着X方向排列的方式被接合。图32是示出针对图5的其他变形例的透视俯视图。另外,图33是沿着图32的A-A线的剖面图。另外,图34是示出针对图33的变形例的剖面图。
能够使用在上述导线结合工序中说明了的结合工具26(参照图24)来形成图32以及图33所示的凸块STB1。即,在结合工具26的前端部分处,对导线27的前端进行加热来形成滚珠部(图示省略)。另外,将该滚珠部接合到图32以及图33所示的管芯焊盘DP的部分DP1。在接合方式中,能够应用与上述导线结合工序同样地,对结合工具26施加超声波而在接合界面形成金属结合的方式。另外,如果在接合了滚珠部之后,切断导线27,则形成图32以及图33所示的凸块STB1。另外,在图33所示的凸块STB1上,进而形成凸块STB1而得到图34所示的凸块STB2。如果这样层叠多个凸块STB1,则能够提高使用图5说明了的作为与部件PS1对应的部件的凸块STB2(参照图34)的高度。其结果,相比于凸块是1级(凸块STB1)时,凸块和密封体MR的接触面积增加,所以锚定效应变大。因此,能够降低由于密封体MR和管芯焊盘DP的线膨胀系数的差异而产生的管芯结合材料BP1的损伤。
能够使用如上述那样在导线结合工序中使用的结合工具26(参照图24)来形成本变形例的凸块STB1、STB2,所以优选在紧接着导线结合工序之前或者在紧接着导线结合之后进行图9所示的第1部件配置工序。
图32以及图33所示的半导体装置PK4以及图34所示的半导体装置PK5除了上述不同点以外,与在上述实施方式中说明了的半导体装置PK1相同。因此,省略与上述实施方式重复的说明以及图示。
接下来,在上述实施方式中,说明了将半导体芯片SC经由作为导电性的树脂粘结材料的由银膏构成的管芯结合材料BP1搭载到管芯焊盘DP上的实施方式。但是,作为搭载半导体芯片SC的粘结材料,能够应用各种变形例。
例如,虽然图示省略,在半导体芯片SC的背面未形成电极而无需电连接管芯焊盘DP和半导体芯片SC的情况下,能够使用非导电性的树脂粘结材料。在该情况下,如果与以图29所示的半导体装置PK2为例子而说明了的变形例组合来应用,则在上述第1部件配置工序中,能够使供给膏状的部件PS2的喷嘴和供给膏状并且非导电性的管芯结合材料的喷嘴兼用化。
另外,例如,在图35以及图36所示的半导体装置PK6中,将半导体芯片SC经由由焊料构成的管芯结合材料BP12固定到管芯焊盘DP的部分DP2上。图35是示出针对图5的其他变形例的俯视图,图36是沿着图35的A-A线的剖面图。
在如半导体装置PK6那样经由焊料连接半导体芯片SC和管芯焊盘DP的情况下,相比于使用在上述实施方式中说明了的银膏的情况,能够提高管芯焊盘DP和半导体芯片SC的漏电极DE(参照图36)的电连接可靠性。
另外,在经由由焊料构成的管芯结合材料BP12搭载半导体芯片SC的情况下,根据使制造工序高效化的观点,为了使集中到半导体芯片SC和管芯焊盘DP的连接界面的应力分散而在部分DP1中设置的部件(第1部件)PS4优选由与管芯结合材料BP12相同的焊料材料构成。但是,如果在将由膏状的焊料构成的部件PS4涂覆到管芯焊盘DP的部分DP1之后,进行回流处理,使部件PS4熔融,则焊料材料沿着管芯焊盘DP的上表面DPt扩展,难以使部件PS4的厚度变厚。因此,在将由焊料构成的部件PS4固定到管芯焊盘DP的部分DP1的情况下,优选经由部件PS4来固定由与部件PS4不同的材料构成了的部件PS5(在图35中附加点图案而表示的部件)。
另外,部件PS5优选以使在部件PS4中包含的焊料成分容易湿润的方式由金属材料构成。由此,能够抑制由焊料构成的部件PS4沿着管芯焊盘DP的上表面DPt扩展,所以能够使在将部件PS2和部件PS3当作一体物的情况下的厚度变厚。
另外,在将由焊料构成的管芯结合材料BP12固定到管芯焊盘DP上的情况下,如果如图5所示的半导体装置PK1那样,在管芯焊盘DP上形成了金属膜CM1,则管芯结合材料BP1(以及部件PS4)容易沿着金属膜CM1扩展,所以半导体芯片SC的搭载位置的控制变得困难。另一方面,无法如在上述实施方式中说明,为了将平面尺寸不同的多个种类的半导体芯片SC搭载到共同的管芯焊盘DP,预先设定半导体芯片SC的搭载预定区域。因此,在使用由焊料构成的管芯结合材料BP12的情况下,优选在管芯焊盘DP的上表面DPt,不形成图5所示的金属膜CM1,而使作为基体材料的铜或者铜合金露出。
另外,在半导体装置PK6中,半导体芯片SC的源电极焊盘SE和源极用的引线LDs经由由例如铜(Cu)构成的金属夹片(导电性部件、金属板)MB2连接。金属夹片MB2被配置为跨过半导体芯片SC的侧面SCs1,一部分经由导电性的连接材料SDp1与半导体芯片SC的源电极焊盘SE电连接,另一部分经由导电性的连接材料SDp2与源极用的引线LDs的连接部RB1的上表面RBt电连接。关于金属夹片MB2,在针对金属板实施加压加工、蚀刻加工等加工处理而预先成型了的状态下,搭载到半导体芯片SC上,所以相比于图5所示的金属条带MB1,能够做成复杂的形状。
另外,在导电性的连接材料SDp1、连接材料SDp2中,能够分别使用焊料材料。在该情况下,在半导体装置PK6的制造工序中,在经由膏状的焊料(称为焊料膏或者油焊料)将半导体芯片SC以及部件PS5配置于管芯焊盘DP上之后,在进行回流处理之前,经由连接材料SDp1、SDp2配置金属夹片MB2。之后,通过进行回流处理,使管芯结合材料BP12、部件PS4、连接材料SDp1以及连接材料SDp2一并地熔融。然后,如果管芯结合材料BP12被冷却,则半导体芯片SC经由管芯结合材料BP12与管芯焊盘DP电连接,并且,被固定到管芯焊盘DP上。另外,部件PS5经由部件PS4被固定到管芯焊盘DP的部分DP1上。另外,金属夹片MB2的一部分经由连接材料SDp1与源电极焊盘SE电连接,金属夹片MB2的另一部分经由连接材料SDp2与源极用的引线LDs电连接。
另外,在半导体装置PK6的制造工序中,有时在回流工序之后,进行洗净工序,所以在进行了回流工序后的洗净工序之后,进行导线结合工序。
图35以及图36所示的半导体装置PK6除了上述不同点以外,与在上述实施方式中说明了的PS1相同。因此,省略与上述实施方式重复的说明以及图示。
接下来,在上述实施方式中,说明了如图5所示,在俯视时,沿着Y方向,以依次并列的方式排列源极用的引线LDs、管芯焊盘DP、漏极用的引线LDd,将栅极用的引线LDg配置于源极用的引线LDs的旁边并且漏极用的引线LDd的相反侧的实施方式,但能够对端子排列应用各种变形例。
例如,在图37所示的半导体装置PK7中,沿着Y方向,以依次并列的方式排列了源极用的引线LDs、管芯焊盘DP以及栅极用的引线LDg。图37是示出针对图5的其他变形例的透视俯视图。另外,图38是沿着图37的A-A线的剖面图。
半导体装置PK7不具有如图5所示的引线LDd那样以从管芯焊盘DP延伸的方式形成了的端子,管芯焊盘DP作为漏极端子发挥功能。另外,半导体装置PK7具有与半导体装置PK7具有的其他部件电分离了(换言之电浮置)的引线LD。
在半导体装置PK7那样的端子排列的情况下,电连接半导体芯片SC和栅极用的引线LDg的导线MW1被形成为在俯视时跨过部件PS4以及部件PS5。因此,在半导体装置PK7的制造工序中,在固定部件PS4、PS5时,根据防止导线MW1损伤的观点,优选在首先固定了部件PS4、PS5之后,进行导线结合工序。
图37以及图38所示的半导体装置PK7除了上述不同点以外,与使用图35以及图36说明了的半导体装置PK6相同。因此,重复的说明以及图示省略。
接下来,在上述实施方式中,说明了在一个封装(密封体MR)内搭载了一个半导体芯片SC的实施方式。但是,能够应用于在一个封装内搭载了多个半导体芯片SC的半导体装置。
在例如图39所示的半导体装置PK8中,以沿着X方向使半导体芯片SC1和半导体芯片SC2相邻的方式搭载。图39是示出针对图5的其他变形例的透视俯视图。在如半导体装置PK8那样在一个管芯焊盘DP上搭载了多个半导体芯片SC的情况下,通过以成为在上述实施方式中说明了的关系的方式,配置多个半导体芯片SC中的各半导体芯片和部件PS1,得到在上述实施方式中说明了的效果。例如,如果在管芯焊盘DP的部分DP2固定部件PS1,而在俯视时在管芯焊盘DP的边缘部与半导体芯片SC1之间配置部件PS1,则能够抑制半导体芯片SC1和管芯焊盘DP的粘结界面的损伤。另外,如果在管芯焊盘DP的部分DP2固定部件PS1,而在俯视时在管芯焊盘DP的边缘部与半导体芯片SC2之间配置部件PS1,则能够抑制半导体芯片SC2和管芯焊盘DP的粘结界面的损伤。
另外,虽然重复的说明省略,通过将作为上述实施方式或者变形例说明了的实施方式分别应用于半导体芯片SC1、SC2,得到在上述实施方式或者变形例中说明了的效果。
接下来,在上述实施方式中,说明了应用于管芯焊盘DP的下表面DPb的至少一部分从密封体MR露出了的管芯焊盘露出型的半导体装置的实施方式。但是,作为变形例,还能够在管芯焊盘DP的下表面DPb的整体被密封体MR密封了的半导体装置中,应用作为上述实施方式或者变形例说明了的技术。如在上述实施方式中说明,在管芯焊盘DP的下表面DPb的整体被密封体MR密封了的情况下,通过以包围管芯焊盘DP的方式形成了密封体MR,容易抑制管芯焊盘DP的热膨胀、热收缩。因此,管芯焊盘DP和密封体MR的紧贴界面的剥离难以产生,半导体芯片SC和管芯焊盘DP的粘结界面的损伤也难以发生。但是,在例如密封体MR和管芯焊盘DP的线膨胀系数之差大的情况下,即使管芯焊盘DP的下表面DPb的整体被密封体MR密封,也有发生管芯焊盘DP和密封体MR的剥离的可能性。在该情况下,通过应用作为上述实施方式或者变形例说明了的技术,能够抑制半导体芯片SC和管芯焊盘DP的粘结界面的损伤。
以上,根据实施方式具体地说明了由本发明者完成的发明,但本发明不限于上述实施方式,除了上述例示的变形例以外,当然能够在不脱离其要旨的范围内进行各种变更。
另外,关于在上述实施方式中说明了的半导体装置的制造方法,如果抽出技术的思想,则能够如下述那样表现。
〔附记1〕
一种半导体装置的制造方法,具有:
(a)准备具有第1主面和位于所述第1主面的相反侧的第2主面的芯片搭载部和在俯视时沿着第1方向与所述芯片搭载部并列地配置并且沿着与所述第1方向正交的第2方向分别并列配置的多个外部端子被支撑于框部的引线框架的工序;
(b)在所述(a)工序之后,在所述芯片搭载部的第1部分的所述第1主面上配置第1部件的工序;
(c)在所述(a)工序之后,将具有形成了第1电极焊盘的第1面和位于所述第1面的相反侧的第2面的半导体芯片,以使所述第2面与所述芯片搭载部的所述第1主面对置的方式,经由粘结材料搭载到所述芯片搭载部的第2部分的工序;
(d)在所述(b)以及(c)工序之后,将所述半导体芯片的所述第1电极焊盘和所述多个外部端子中的第1外部端子经由第1导电性部件电连接的工序;以及
(e)对所述半导体芯片、所述芯片搭载部的所述第1主面、所述多个外部端子各自的一部分以及所述第1导电性部件进行密封,而形成密封体的工序,
在俯视时,所述芯片搭载部的所述第2部分配置于所述第1部分与所述第1外部端子之间,
在俯视时,所述第1方向上的所述芯片搭载部的所述第1部分的长度比所述第1方向上的所述半导体芯片的长度更长,
在所述(e)工序之后,所述第1部件与所述芯片搭载部以外的端子电分离。
〔附记2〕
在附记1记载的半导体装置的制造方法中,
在所述(c)工序中,在俯视时,以使所述第1方向上的所述芯片搭载部的所述第1部分的长度比所述第2方向上的所述半导体芯片的边缘部至所述管芯焊盘的边缘部的距离更长的方式,搭载所述半导体芯片。
〔附记3〕
在附记2记载的半导体装置的制造方法中,
在所述(c)工序中,在俯视时,以使所述第1方向上的所述半导体芯片至所述第1部件的距离比所述第1方向上的所述半导体芯片的长度更短的方式,搭载所述半导体芯片。
〔附记4〕
在附记3记载的半导体装置的制造方法中,
在所述(b)工序中,在俯视时,以使所述第2方向上的所述第1部件的长度比在所述(c)工序中搭载的所述半导体芯片的所述第2方向上的长度更长的方式进行。
〔附记5〕
在附记4记载的半导体装置的制造方法中,
所述(e)工序是以使所述芯片搭载部的所述第2主面的一部分从所述密封体露出的方式进行的。
〔附记6〕
在附记3记载的半导体装置的制造方法中,
所述(b)工序是在俯视时,以沿着所述1方向配置多个所述第1部件、并且以使各个的间隔距离比所述第1方向上的所述半导体芯片的长度更短的方式进行的。
〔附记7〕
在附记1记载的半导体装置的制造方法中,
所述第1部件由与所述粘结材料相同的材料构成。
〔附记8〕
在附记7记载的半导体装置的制造方法中,
所述第1部件以及所述粘结材料是含有多个银粒子的导电性粘结材料。
〔附记9〕
在附记1记载的半导体装置的制造方法中,
所述半导体芯片的厚度比所述芯片搭载部的厚度更薄。
〔附记10〕
在附记9记载的半导体装置的制造方法中,
所述半导体芯片的厚度是100μm以下。
〔附记11〕
在附记1记载的半导体装置的制造方法中,
在所述半导体芯片的所述第1面形成了第2电极焊盘,
在所述半导体芯片的所述第2面形成了第3电极,
所述(c)工序包括经由所述粘结材料电连接所述芯片搭载部的所述第1主面和所述半导体芯片的所述第3电极的工序,
所述(d)工序包括电连接所述半导体芯片的所述第2电极焊盘和所述多个外部端子中的第2外部端子的工序,
所述(e)工序是以使所述芯片搭载部的所述第2主面的一部分从所述密封体露出的方式进行的。
〔附记12〕
在附记11记载的半导体装置的制造方法中,
所述半导体芯片包括纵向沟道构造的MOSFET,
所述第1电极焊盘与所述MOSFET的源电极电连接,
所述第2电极焊盘与所述MOSFET的栅电极电连接,
所述第3电极是所述MOSFET的栅电极。
〔附记13〕
在附记11记载的半导体装置的制造方法中,
在所述(e)工序之后,所述第1外部端子、所述第2外部端子以及所述芯片搭载部的所述第2主面的从所述密封体露出了的部分具有在将所述半导体装置安装到安装基板时能够进行锡焊的部分。
〔附记14〕
在附记1记载的半导体装置的制造方法中,
所述(c)工序包括在所述芯片搭载部的所述第1部分的所述第1主面上经由所述第1部件搭载由与所述第1部件不同的材料构成的第2部件的工序。
〔附记15〕
在附记1记载的半导体装置的制造方法中,
在所述芯片搭载部的所述第1主面上形成了金属膜,
所述(b)工序包括将所述第1部件供给到所述金属膜上的工序,
所述(c)工序包括将所述粘结材料供给到所述金属膜上的工序。
Claims (20)
1.一种半导体装置,其特征在于,具备:
半导体芯片,具有形成了第1电极焊盘的第1面和位于所述第1面的相反侧的第2面;
芯片搭载部,具有经由粘结材料搭载了所述半导体芯片的第1主面和位于所述第1主面的相反侧的第2主面;
多个外部端子,在俯视时,沿着第1方向与所述芯片搭载部并列地配置并且沿着与所述第1方向正交的第2方向分别并列配置;
第1导电性部件,电连接所述半导体芯片的所述第1电极与所述多个外部端子中的第1外部端子;以及
密封体,对所述半导体芯片、所述芯片搭载部的所述第1主面、所述多个外部端子各自的一部分以及所述第1导电性部件进行密封,
所述芯片搭载部具有第1部分和配置于所述第1部分与所述第1端子之间且在所述芯片搭载部的所述第1主面搭载了所述半导体芯片的第2部分,
在所述第1部分的所述第1主面上,固定与所述芯片搭载部以外的端子电分离了的第1部件,
在俯视时,所述第1方向上的所述芯片搭载部的所述第1部分的长度比所述第1方向上的所述半导体芯片的长度更长。
2.根据权利要求1所述的半导体装置,其特征在于,
在俯视时,所述第1方向上的所述芯片搭载部的所述第1部分的长度比所述第2方向上的所述半导体芯片的边缘部至所述管芯焊盘的边缘部的距离更长。
3.根据权利要求2所述的半导体装置,其特征在于,
在俯视时,所述第1方向上的所述半导体芯片至所述第1部件的距离比所述第1方向上的所述半导体芯片的长度更短。
4.根据权利要求3所述的半导体装置,其特征在于,
在俯视时,所述第2方向上的所述第1部件的长度比所述第2方向上的所述半导体芯片的长度更长。
5.根据权利要求4所述的半导体装置,其特征在于,
所述芯片搭载部的所述第2主面的一部分从所述密封体露出。
6.根据权利要求3所述的半导体装置,其特征在于,
在俯视时,所述第1部件沿着所述1方向固定了多个,各个的间隔距离比所述第1方向上的所述半导体芯片的长度更短。
7.根据权利要求1所述的半导体装置,其特征在于,
所述第1部件由与所述粘结材料相同的材料构成。
8.根据权利要求7所述的半导体装置,其特征在于,
所述第1部件以及所述粘结材料是含有多个银粒子(Ag填料)的导电性粘结材料。
9.根据权利要求1所述的半导体装置,其特征在于,
所述半导体芯片的厚度比所述芯片搭载部的厚度更薄。
10.根据权利要求9所述的半导体装置,其特征在于,
所述半导体芯片的厚度是100μm以下。
11.根据权利要求1所述的半导体装置,其特征在于,
在所述半导体芯片的所述第1面,形成了与所述多个外部端子中的第2外部端子电连接了的第2电极焊盘,
在所述半导体芯片的所述第2面,形成了经由所述粘结材料与所述芯片搭载部的所述第1主面电连接了的第3电极,
所述芯片搭载部的所述第2主面的一部分从所述密封体露出。
12.根据权利要求11所述的半导体装置,其特征在于,
所述半导体芯片包括纵向沟道构造的MOSFET,
所述第1电极焊盘与所述MOSFET的源电极电连接,
所述第2电极焊盘与所述MOSFET的栅电极电连接,
所述第3电极是所述MOSFET的栅电极。
13.根据权利要求11所述的半导体装置,其特征在于,
所述第1外部端子、所述第2外部端子以及所述芯片搭载部的所述第2主面的从所述密封体露出了的部分具有在将所述半导体装置安装到安装基板时能够进行锡焊的部分。
14.根据权利要求1所述的半导体装置,其特征在于,
在所述芯片搭载部的所述第1部分的所述第1主面上,经由所述第1部件固定了由与所述第1部件不同的材料构成了的第2部件。
15.根据权利要求1所述的半导体装置,其特征在于,
在所述芯片搭载部的所述第1主面上形成了金属膜,
所述粘结材料和所述第1部件被固定于所述金属膜上。
16.一种半导体装置,其特征在于,具备:
半导体芯片,具备纵向沟道构造的MOSFET,具有形成了源电极焊盘和栅电极焊盘的第1面以及位于所述第1面的相反侧且形成了漏电极的第2面;
芯片搭载部,具有经由粘结材料搭载并电连接了所述半导体芯片的第1主面和位于所述第1主面的相反侧的第2主面;
多个引线,在俯视时,沿着第1方向与所述芯片搭载部并列地配置,并且沿着与所述第1方向正交的第2方向分别并列配置;
第1导电性部件,电连接所述半导体芯片的所述源电极与所述多个引线中的源极引线;
第2导电性部件,电连接所述半导体芯片的所述栅电极和所述多个引线中的栅极引线;以及
密封体,对所述半导体芯片、所述芯片搭载部的所述第1主面、所述多个引线各自的一部分、所述第1导电性部件以及所述第2导电性部件进行密封,
所述芯片搭载部的所述第2主面的一部分从所述密封体露出,
所述芯片搭载部具有第1部分和配置于所述第1部分与所述第1端子之间且在所述芯片搭载部的所述第1主面搭载了所述半导体芯片的第2部分,
在所述第1部分的所述第1主面上,固定了与所述芯片搭载部以外的端子电分离了的、由与所述粘结材料相同的材料构成了的第1部件,
在俯视时,所述第1方向上的所述芯片搭载部的所述第1部分的长度比所述第1方向上的所述半导体芯片的长度更长。
17.根据权利要求16所述的半导体装置,其特征在于,
所述粘结材料和所述第1部件是含有多个银粒子的导电性粘结材料。
18.根据权利要求17所述的半导体装置,其特征在于,
所述第1导电性部件是金属箔,所述第2导电性部件是金属导线。
19.根据权利要求18所述的半导体装置,其特征在于,
所述芯片搭载部、所述源极引线以及所述栅极引线由以铜为主要的成分的材料构成,
在所述芯片搭载部的所述第1主面的固定了所述粘结材料和所述第1部件的部分以及所述栅极引线的连接了所述第2导电性部件的部分处,形成了金属膜,
在所述源极引线的连接了所述第1导电性部件的部分处,未形成所述金属膜。
20.根据权利要求18所述的半导体装置,其特征在于,
在俯视时,所述半导体芯片是长方形形状,
所述半导体芯片以使其长边沿着所述第2方向的方式搭载于所述芯片搭载部的所述第1主面上,
在俯视时,所述第1导电性部件与所述半导体芯片的所述长边交叉。
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US9607940B2 (en) | 2017-03-28 |
EP3018712A4 (en) | 2017-04-19 |
HK1214032A1 (zh) | 2016-07-15 |
CN105264659B (zh) | 2018-05-18 |
TW201503299A (zh) | 2015-01-16 |
WO2015001676A1 (ja) | 2015-01-08 |
US20170170100A1 (en) | 2017-06-15 |
US9922905B2 (en) | 2018-03-20 |
JPWO2015001676A1 (ja) | 2017-02-23 |
TWI620283B (zh) | 2018-04-01 |
EP3018712B1 (en) | 2021-09-01 |
US20160204057A1 (en) | 2016-07-14 |
JP6129315B2 (ja) | 2017-05-17 |
EP3018712A1 (en) | 2016-05-11 |
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